2 ppcskel - a Free Software replacement for the Nintendo/BroadOn bootloader.
5 Copyright (C) 2009 Bernhard Urban <lewurm@gmx.net>
6 Copyright (C) 2009 Sebastian Falbesoner <sebastian.falbesoner@gmail.com>
8 # This code is licensed to you under the terms of the GNU GPL, version 2;
9 # see file COPYING or http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt
12 #include "../../bootmii_ppc.h"
13 #include "../../hollywood.h"
14 #include "../../irq.h"
15 #include "../../string.h"
16 #include "../../malloc.h"
19 #include "../usbspec/usb11spec.h"
21 /* macro for accessing u32 variables that need to be in little endian byte order;
23 * whenever you read or write from an u32 field that the ohci host controller
24 * will read or write from too, use this macro for access!
26 #define LE(dword) (u32)( (((dword) & 0xFF000000) >> 24) | \
27 (((dword) & 0x00FF0000) >> 8) | \
28 (((dword) & 0x0000FF00) << 8) | \
29 (((dword) & 0x000000FF) << 24) )
31 static struct endpoint_descriptor *allocate_endpoint();
32 static struct general_td *allocate_general_td();
33 static void control_quirk();
34 static void dbg_op_state();
35 //static void dbg_td_flag(u32 flag);
36 static void configure_ports(u8 from_init);
37 static void setup_port(u32 reg, u8 from_init);
39 static struct ohci_hcca hcca_oh0;
42 static struct endpoint_descriptor *allocate_endpoint()
44 struct endpoint_descriptor *ep;
45 ep = (struct endpoint_descriptor *)memalign(16, sizeof(struct endpoint_descriptor));
46 memset(ep, 0, sizeof(struct endpoint_descriptor));
47 ep->flags = LE(OHCI_ENDPOINT_GENERAL_FORMAT);
48 ep->headp = ep->tailp = ep->nexted = LE(0);
52 static struct general_td *allocate_general_td()
54 struct general_td *td;
55 td = (struct general_td *)memalign(16, sizeof(struct general_td));
56 memset(td, 0, sizeof(struct general_td));
59 td->cbp = td->be = LE(0);
63 static void control_quirk()
65 static struct endpoint_descriptor *ed = 0; /* empty ED */
66 static struct general_td *td = 0; /* dummy TD */
73 * Allocate and keep a special empty ED with just a dummy TD.
76 ed = allocate_endpoint();
80 td = allocate_general_td(0);
87 ed->tailp = ed->headp = LE(virt_to_phys((void*) ((u32)td & OHCI_ENDPOINT_HEAD_MASK)));
88 ed->flags |= LE(OHCI_ENDPOINT_DIRECTION_OUT);
92 * The OHCI USB host controllers on the Nintendo Wii
93 * video game console stop working when new TDs are
94 * added to a scheduled control ED after a transfer has
95 * has taken place on it.
97 * Before scheduling any new control TD, we make the
98 * controller happy by always loading a special control ED
99 * with a single dummy TD and letting the controller attempt
101 * The controller won't do anything with it, as the special
102 * ED has no TDs, but it will keep the controller from failing
103 * on the next transfer.
105 head = read32(OHCI0_HC_CTRL_HEAD_ED);
107 printf("head: 0x%08X\n", head);
109 * Load the special empty ED and tell the controller to
110 * process the control list.
112 sync_after_write(ed, 16);
113 sync_after_write(td, 16);
114 write32(OHCI0_HC_CTRL_HEAD_ED, virt_to_phys(ed));
116 status = read32(OHCI0_HC_CONTROL);
117 set32(OHCI0_HC_CONTROL, OHCI_CTRL_CLE);
118 write32(OHCI0_HC_COMMAND_STATUS, OHCI_CLF);
120 /* spin until the controller is done with the control list */
121 current = read32(OHCI0_HC_CTRL_CURRENT_ED);
124 current = read32(OHCI0_HC_CTRL_CURRENT_ED);
127 printf("current: 0x%08X\n", current);
129 /* restore the old control head and control settings */
130 write32(OHCI0_HC_CONTROL, status);
131 write32(OHCI0_HC_CTRL_HEAD_ED, head);
138 static void dbg_op_state()
140 switch (read32(OHCI0_HC_CONTROL) & OHCI_CTRL_HCFS) {
141 case OHCI_USB_SUSPEND:
142 printf("ohci-- OHCI_USB_SUSPEND\n");
145 printf("ohci-- OHCI_USB_RESET\n");
148 printf("ohci-- OHCI_USB_OPER\n");
150 case OHCI_USB_RESUME:
151 printf("ohci-- OHCI_USB_RESUME\n");
156 static void dbg_td_flag(u32 flag)
158 printf("**************** dbg_td_flag: 0x%08X ***************\n", flag);
159 printf("CC: %X\tshould be 0, see page 32 (ohci spec)\n", (flag>>28)&0xf);
160 printf("EC: %X\tsee page 20 (ohci spec)\n", (flag>>26)&3);
161 printf(" T: %X\n", (flag>>24)&3);
162 printf("DI: %X\n", (flag>>21)&7);
163 printf("DP: %X\n", (flag>>19)&3);
164 printf(" R: %X\n", (flag>>18)&1);
165 printf("********************************************************\n");
168 static void general_td_fill(struct general_td *dest, const usb_transfer_descriptor *src)
171 dest->cbp = LE(virt_to_phys(src->buffer));
172 dest->be = LE(LE(dest->cbp) + src->actlen - 1);
173 /* save virtual address here */
174 dest->bufaddr = (u32) src->buffer;
177 dest->cbp = dest->be = LE(0);
181 dest->buflen = src->actlen;
183 dest->flags &= LE(~OHCI_TD_DIRECTION_PID_MASK);
186 printf("pid_setup\n");
187 dest->flags |= LE(OHCI_TD_DIRECTION_PID_SETUP);
188 dest->flags |= LE(OHCI_TD_TOGGLE_0);
189 dest->flags |= LE(OHCI_TD_BUFFER_ROUNDING);
193 dest->flags |= LE(OHCI_TD_DIRECTION_PID_OUT);
194 dest->flags |= LE(OHCI_TD_BUFFER_ROUNDING);
197 * TODO: just temporary solution! (consider it with len?)
198 * there can be also regular PID_OUT pakets
200 dest->flags |= LE(OHCI_TD_TOGGLE_1);
204 dest->flags |= LE(OHCI_TD_DIRECTION_PID_IN);
205 if(src->maxp > src->actlen) {
206 printf("round buffer!");
207 dest->flags |= LE(OHCI_TD_BUFFER_ROUNDING);
210 * let the endpoint do the togglestuff!
211 * TODO: just temporary solution!
212 * there can be also inregular PID_IN pakets (@Status Stage)
214 dest->flags |= LE(OHCI_TD_TOGGLE_CARRY);
216 /* should be done by HC!
217 * first pid_in start with DATA0 */
219 dummyconfig.headp = LE( src->togl ?
220 LE(dummyconfig.headp) | OHCI_ENDPOINT_TOGGLE_CARRY :
221 LE(dummyconfig.headp) & ~OHCI_ENDPOINT_TOGGLE_CARRY);
225 dest->flags |= LE(OHCI_TD_SET_DELAY_INTERRUPT(7));
228 static void dump_address(void *addr, u32 size, const char* str)
230 printf("%s hexdump (%d) @ 0x%08X:\n", str, size, addr);
234 static struct endpoint_descriptor _edhead;
235 struct endpoint_descriptor *edhead = 0;
238 printf("<^> <^> <^> hcdi_fire(start)\n");
243 control_quirk(); //required? YES! :O ... erm... or no? :/ ... in fact I have no idea
244 write32(OHCI0_HC_CTRL_HEAD_ED, virt_to_phys(edhead));
247 sync_after_write(edhead, sizeof(struct endpoint_descriptor));
248 dump_address(edhead, sizeof(struct endpoint_descriptor), "edhead(before)");
250 struct general_td *x = phys_to_virt(LE(edhead->headp) & OHCI_ENDPOINT_HEAD_MASK);
251 printf("STRUCT LEN: %d\n", sizeof(struct general_td));
252 while(virt_to_phys(x)) {
253 sync_after_write(x, sizeof(struct general_td));
254 dump_address(x, sizeof(struct general_td), "x(before)");
257 sync_after_write((void*) phys_to_virt(LE(x->cbp)), x->buflen);
258 dump_address((void*) phys_to_virt(LE(x->cbp)), x->buflen, "x->cbp(before)");
260 x = phys_to_virt(LE(x->nexttd));
263 /* trigger control list */
264 set32(OHCI0_HC_CONTROL, OHCI_CTRL_CLE);
265 write32(OHCI0_HC_COMMAND_STATUS, OHCI_CLF);
267 struct general_td *n=0, *prev = 0, *next = 0;
268 /* poll until edhead->headp is null */
270 sync_before_read(edhead, sizeof(struct endpoint_descriptor));
271 printf("edhead->headp: 0x%08X\n", LE(edhead->headp));
273 /* if halted, debug output plz. will break the transfer */
274 if((LE(edhead->headp) & OHCI_ENDPOINT_HALTED)) {
275 n = phys_to_virt(LE(edhead->headp)&~0xf);
276 prev = phys_to_virt((u32)prev);
279 sync_before_read((void*) n, sizeof(struct general_td));
280 printf("n: 0x%08X\n", n);
281 dump_address(n, sizeof(struct general_td), "n(after)");
283 sync_before_read((void*) n->bufaddr, n->buflen);
284 dump_address((void*) n->bufaddr, n->buflen, "n->bufaddr(after)");
286 dbg_td_flag(LE(n->flags));
288 sync_before_read((void*) prev, sizeof(struct general_td));
289 printf("prev: 0x%08X\n", prev);
290 dump_address(prev, sizeof(struct general_td), "prev(after)");
291 if(prev->buflen >0) {
292 sync_before_read((void*) prev->bufaddr, prev->buflen);
293 dump_address((void*) prev->bufaddr, prev->buflen, "prev->bufaddr(after)");
295 dbg_td_flag(LE(prev->flags));
297 printf("halted end!\n");
300 prev = (struct general_td*) (LE(edhead->headp)&~0xf);
301 } while(LE(edhead->headp)&~0xf);
303 n = phys_to_virt(read32(OHCI0_HC_DONE_HEAD) & ~1);
304 printf("hc_done_head: 0x%08X\n", read32(OHCI0_HC_DONE_HEAD));
307 /* reverse done queue */
308 while(virt_to_phys(n) && edhead->tdcount) {
309 sync_before_read((void*) n, sizeof(struct general_td));
310 printf("n: 0x%08X\n", n);
311 printf("next: 0x%08X\n", next);
312 printf("prev: 0x%08X\n", prev);
315 n = (struct general_td*) phys_to_virt(LE(n->nexttd));
316 next->nexttd = (u32) prev;
324 while(virt_to_phys(n)) {
325 dump_address(n, sizeof(struct general_td), "n(after)");
328 sync_before_read((void*) n->bufaddr, n->buflen);
329 dump_address((void*) n->bufaddr, n->buflen, "n->bufaddr(after)");
331 dbg_td_flag(LE(n->flags));
333 n = (struct general_td*) n->nexttd;
337 hcca_oh0.done_head = 0;
338 sync_after_write(&hcca_oh0, sizeof(hcca_oh0));
340 write32(OHCI0_HC_CONTROL, read32(OHCI0_HC_CONTROL)&~OHCI_CTRL_CLE);
344 printf("<^> <^> <^> hcdi_fire(end)\n");
348 * Enqueue a transfer descriptor.
350 u8 hcdi_enqueue(const usb_transfer_descriptor *td) {
351 printf("*()*()*()*()*()*()*() hcdi_enqueue(start)\n");
354 memset(edhead, 0, sizeof(struct endpoint_descriptor));
355 edhead->flags = LE(OHCI_ENDPOINT_GENERAL_FORMAT);
356 edhead->headp = edhead->tailp = edhead->nexted = LE(0);
357 edhead->flags |= LE(OHCI_ENDPOINT_LOW_SPEED |
358 OHCI_ENDPOINT_SET_DEVICE_ADDRESS(td->devaddress) |
359 OHCI_ENDPOINT_SET_ENDPOINT_NUMBER(td->endpoint) |
360 OHCI_ENDPOINT_SET_MAX_PACKET_SIZE(td->maxp));
364 struct general_td *tdhw = allocate_general_td();
365 general_td_fill(tdhw, td);
370 edhead->headp = LE(virt_to_phys((void*) ((u32)tdhw & OHCI_ENDPOINT_HEAD_MASK)));
373 /* headp in endpoint already exists
376 struct general_td *n = (struct general_td*) phys_to_virt(LE(edhead->headp) & OHCI_ENDPOINT_HEAD_MASK);
377 while(LE(n->nexttd)) {
378 n = phys_to_virt(LE(n->nexttd));
380 n->nexttd = LE(virt_to_phys((void*) ((u32)tdhw & OHCI_ENDPOINT_HEAD_MASK)));
381 printf("n: 0x%08X\n", n);
382 printf("n->nexttd: 0x%08X\n", phys_to_virt(LE(n->nexttd)));
385 printf("*()*()*()*()*()*()*() hcdi_enqueue(end)\n");
391 * Remove an transfer descriptor from transfer queue.
393 u8 hcdi_dequeue(usb_transfer_descriptor *td) {
399 printf("ohci-- init\n");
402 /* disable hc interrupts */
403 set32(OHCI0_HC_INT_DISABLE, OHCI_INTR_MIE);
405 /* save fmInterval and calculate FSMPS */
406 #define FSMP(fi) (0x7fff & ((6 * ((fi) - 210)) / 7))
407 #define FI 0x2edf /* 12000 bits per frame (-1) */
408 u32 fmint = read32(OHCI0_HC_FM_INTERVAL) & 0x3fff;
410 printf("ohci-- fminterval delta: %d\n", fmint - FI);
411 fmint |= FSMP (fmint) << 16;
413 /* enable interrupts of both usb host controllers */
414 set32(EHCI_CTL, EHCI_CTL_OH0INTE | EHCI_CTL_OH1INTE | 0xe0000);
417 write32(OHCI0_HC_COMMAND_STATUS, OHCI_HCR);
421 while ((read32(OHCI0_HC_COMMAND_STATUS) & OHCI_HCR) != 0) {
423 printf("ohci-- FAILED");
429 /* disable interrupts; 2ms timelimit here!
430 now we're in the SUSPEND state ... must go OPERATIONAL
431 within 2msec else HC enters RESUME */
433 u32 cookie = irq_kill();
435 /* Tell the controller where the control and bulk lists are
436 * The lists are empty now. */
437 write32(OHCI0_HC_CTRL_HEAD_ED, 0);
438 write32(OHCI0_HC_BULK_HEAD_ED, 0);
440 /* set hcca adress */
441 sync_after_write(&hcca_oh0, 256);
442 write32(OHCI0_HC_HCCA, virt_to_phys(&hcca_oh0));
444 /* set periodicstart */
446 u32 fmInterval = read32(OHCI0_HC_FM_INTERVAL) &0x3fff;
447 u32 fit = read32(OHCI0_HC_FM_INTERVAL) & FIT;
449 write32(OHCI0_HC_FM_INTERVAL, fmint | (fit ^ FIT));
450 write32(OHCI0_HC_PERIODIC_START, ((9*fmInterval)/10)&0x3fff);
453 if ((read32(OHCI0_HC_FM_INTERVAL) & 0x3fff0000) == 0 || !read32(OHCI0_HC_PERIODIC_START)) {
454 printf("ohci-- w00t, fail!! see ohci-hcd.c:669\n");
457 /* start HC operations */
458 write32(OHCI0_HC_CONTROL, OHCI_CONTROL_INIT | OHCI_USB_OPER);
460 /* wake on ConnectStatusChange, matching external hubs */
461 write32(OHCI0_HC_RH_STATUS, /*RH_HS_DRWE |*/ RH_HS_LPSC);
463 /* Choose the interrupts we care about now, others later on demand */
464 write32(OHCI0_HC_INT_STATUS, ~0);
465 write32(OHCI0_HC_INT_ENABLE, OHCI_INTR_INIT);
468 wait_ms ((read32(OHCI0_HC_RH_DESCRIPTOR_A) >> 23) & 0x1fe);
470 configure_ports((u8)1);
476 static void configure_ports(u8 from_init)
478 printf("OHCI0_HC_RH_DESCRIPTOR_A:\t0x%08X\n", read32(OHCI0_HC_RH_DESCRIPTOR_A));
479 printf("OHCI0_HC_RH_DESCRIPTOR_B:\t0x%08X\n", read32(OHCI0_HC_RH_DESCRIPTOR_B));
480 printf("OHCI0_HC_RH_STATUS:\t\t0x%08X\n", read32(OHCI0_HC_RH_STATUS));
481 printf("OHCI0_HC_RH_PORT_STATUS_1:\t0x%08X\n", read32(OHCI0_HC_RH_PORT_STATUS_1));
482 printf("OHCI0_HC_RH_PORT_STATUS_2:\t0x%08X\n", read32(OHCI0_HC_RH_PORT_STATUS_2));
484 setup_port(OHCI0_HC_RH_PORT_STATUS_1, from_init);
485 setup_port(OHCI0_HC_RH_PORT_STATUS_2, from_init);
486 printf("configure_ports done\n");
489 static void setup_port(u32 reg, u8 from_init)
491 u32 port = read32(reg);
492 if((port & RH_PS_CCS) && ((port & RH_PS_CSC) || from_init)) {
493 write32(reg, RH_PS_CSC);
497 /* clear CSC flag, set PES and start port reset (PRS) */
498 write32(reg, RH_PS_PES);
499 while(!(read32(reg) & RH_PS_PES)) {
504 write32(reg, RH_PS_PRS);
506 /* spin until port reset is complete */
507 while(!(read32(reg) & RH_PS_PRSC)); // hint: it may stuck here
508 printf("loop done\n");
510 (void) usb_add_device();
516 /* read interrupt status */
517 u32 flags = read32(OHCI0_HC_INT_STATUS);
519 /* when all bits are set to 1 some problem occured */
520 if (flags == 0xffffffff) {
521 printf("ohci-- Houston, we have a serious problem! :(\n");
525 /* only care about interrupts that are enabled */
526 flags &= read32(OHCI0_HC_INT_ENABLE);
530 printf("OHCI Interrupt occured: but not for you! WTF?!\n");
534 printf("OHCI Interrupt occured: ");
535 /* UnrecoverableError */
536 if (flags & OHCI_INTR_UE) {
537 printf("UnrecoverableError\n");
538 /* TODO: well, I don't know... nothing,
539 * because it won't happen anyway? ;-) */
542 /* RootHubStatusChange */
543 if (flags & OHCI_INTR_RHSC) {
544 printf("RootHubStatusChange\n");
545 /* TODO: set some next_statechange variable... */
547 write32(OHCI0_HC_INT_STATUS, OHCI_INTR_RD | OHCI_INTR_RHSC);
550 else if (flags & OHCI_INTR_RD) {
551 printf("ResumeDetected\n");
552 write32(OHCI0_HC_INT_STATUS, OHCI_INTR_RD);
553 /* TODO: figure out what the linux kernel does here... */
556 /* WritebackDoneHead */
557 if (flags & OHCI_INTR_WDH) {
558 printf("WritebackDoneHead\n");
559 /* basically the linux irq handler reverse TDs to their urbs
560 * and set done_head to null.
561 * since we are polling atm, just should do the latter task.
562 * however, this won't work for now (i don't know why...)
566 sync_before_read(&hcca_oh0, 256);
567 hcca_oh0.done_head = 0;
568 sync_after_write(&hcca_oh0, 256);
572 /* TODO: handle any pending URB/ED unlinks... */
574 #define HC_IS_RUNNING() 1 /* dirty, i know... just a temporary solution */
575 if (HC_IS_RUNNING()) {
576 write32(OHCI0_HC_INT_STATUS, flags);
577 write32(OHCI0_HC_INT_ENABLE, OHCI_INTR_MIE);
583 sync_before_read(&hcca_oh0, 256);
584 printf("***** frame_no: %d *****\n", LE(hcca_oh0.frame_no));