usb/host/ohci.c

   1 /*
   2        ppcskel - a Free Software replacement for the Nintendo/BroadOn bootloader.
   3        ohci hardware support
   4
   5 Copyright (C) 2009     Bernhard Urban <lewurm@gmx.net>
   6 Copyright (C) 2009     Sebastian Falbesoner <sebastian.falbesoner@gmail.com>
   7
   8 # This code is licensed to you under the terms of the GNU GPL, version 2;
   9 # see file COPYING or http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt
  10 */
  11
  12 #include "../../bootmii_ppc.h"
  13 #include "../../hollywood.h"
  14 #include "../../irq.h"
  15 #include "../../string.h"
  16 #include "../../malloc.h"
  17 #include "ohci.h"
  18 #include "host.h"
  19 #include "../usbspec/usb11spec.h"
  20
  21 /* activate control_quirk */
  22 #define _USE_C_Q
  23
  24 /* macro for accessing u32 variables that need to be in little endian byte order;
  25  *
  26  * whenever you read or write from an u32 field that the ohci host controller
  27  * will read or write from too, use this macro for access!
  28  */
  29 #define LE(dword) (u32)( (((dword) & 0xFF000000) >> 24) | \
  30                            (((dword) & 0x00FF0000) >> 8)  | \
  31                            (((dword) & 0x0000FF00) << 8)  | \
  32                            (((dword) & 0x000000FF) << 24) )
  33
  34 static struct general_td *allocate_general_td();
  35 static void dbg_op_state();
  36 static void configure_ports(u8 from_init);
  37 static void setup_port(u32 reg, u8 from_init);
  38
  39 static struct ohci_hcca hcca_oh0;
  40
  41
  42 static struct general_td *allocate_general_td()
  43 {
  44         struct general_td *td;
  45         td = (struct general_td *)memalign(16, sizeof(struct general_td));
  46         memset(td, 0, sizeof(struct general_td));
  47         td->flags = LE(0);
  48         td->nexttd = LE(0);
  49         td->cbp = td->be = LE(0);
  50         return td;
  51 }
  52
  53
  54 static void dbg_op_state()
  55 {
  56         switch (read32(OHCI0_HC_CONTROL) & OHCI_CTRL_HCFS) {
  57                 case OHCI_USB_SUSPEND:
  58                         printf("ohci-- OHCI_USB_SUSPEND\n");
  59                         break;
  60                 case OHCI_USB_RESET:
  61                         printf("ohci-- OHCI_USB_RESET\n");
  62                         break;
  63                 case OHCI_USB_OPER:
  64                         printf("ohci-- OHCI_USB_OPER\n");
  65                         break;
  66                 case OHCI_USB_RESUME:
  67                         printf("ohci-- OHCI_USB_RESUME\n");
  68                         break;
  69         }
  70 }
  71
  72 #ifdef _DU_OHCI_F_HALT
  73 static void dbg_td_flag(u32 flag)
  74 {
  75         printf("**************** dbg_td_flag: 0x%08X ***************\n", flag);
  76         printf("CC: %X\tshould be 0, see page 32 (ohci spec)\n", (flag>>28)&0xf);
  77         printf("EC: %X\tsee page 20 (ohci spec)\n", (flag>>26)&3);
  78         printf(" T: %X\n", (flag>>24)&3);
  79         printf("DI: %X\n", (flag>>21)&7);
  80         printf("DP: %X\n", (flag>>19)&3);
  81         printf(" R: %X\n", (flag>>18)&1);
  82         printf("********************************************************\n");
  83 }
  84 #endif
  85
  86 static void general_td_fill(struct general_td *dest, const struct usb_transfer_descriptor *src)
  87 {
  88         if(src->actlen) {
  89                 dest->cbp = LE(virt_to_phys(src->buffer));
  90                 dest->be = LE(LE(dest->cbp) + src->actlen - 1);
  91                 /* save virtual address here */
  92                 dest->bufaddr = (u32) src->buffer;
  93         }
  94         else {
  95                 dest->cbp = dest->be = LE(0);
  96                 dest->bufaddr = 0;
  97         }
  98
  99         dest->buflen = src->actlen;
 100
 101         dest->flags &= LE(~OHCI_TD_DIRECTION_PID_MASK);
 102         switch(src->pid) {
 103                 case USB_PID_SETUP:
 104 #ifdef _DU_OHCI_Q
 105                         printf("pid_setup\n");
 106 #endif
 107                         dest->flags |= LE(OHCI_TD_DIRECTION_PID_SETUP);
 108                         dest->flags |= LE(OHCI_TD_TOGGLE_0);
 109                         dest->flags |= LE(OHCI_TD_BUFFER_ROUNDING);
 110                         break;
 111                 case USB_PID_OUT:
 112 #ifdef _DU_OHCI_Q
 113                         printf("pid_out\n");
 114 #endif
 115                         dest->flags |= LE(OHCI_TD_DIRECTION_PID_OUT);
 116                         dest->flags |= LE(OHCI_TD_BUFFER_ROUNDING);
 117
 118                         /*
 119                          * TODO: just temporary solution! (consider it with len?)
 120                          * there can be also regular PID_OUT pakets
 121                          */
 122                         dest->flags |= LE(OHCI_TD_TOGGLE_1);
 123                         break;
 124                 case USB_PID_IN:
 125 #ifdef _DU_OHCI_Q
 126                         printf("pid_in\n");
 127 #endif
 128                         dest->flags |= LE(OHCI_TD_DIRECTION_PID_IN);
 129                         if(src->maxp > src->actlen) {
 130                                 dest->flags |= LE(OHCI_TD_BUFFER_ROUNDING);
 131 #ifdef _DU_OHCI_Q
 132                                 printf("round buffer!\n");
 133 #endif
 134                         }
 135                         /*
 136                          * let the endpoint do the togglestuff!
 137                          * TODO: just temporary solution!
 138                          * there can be also inregular PID_IN pakets (@Status Stage)
 139                          */
 140                         dest->flags |= LE(OHCI_TD_TOGGLE_CARRY);
 141                         break;
 142         }
 143         dest->flags |= LE(OHCI_TD_SET_DELAY_INTERRUPT(7));
 144 }
 145
 146 #ifdef _DU_OHCI_F_HALT
 147 static void dump_address(void *addr, u32 size, const char* str)
 148 {
 149         printf("%s hexdump (%d) @ 0x%08X:\n", str, size, addr);
 150         hexdump(addr, size);
 151 }
 152 #endif
 153
 154 static struct endpoint_descriptor _edhead;
 155 struct endpoint_descriptor *edhead = 0;
 156 void hcdi_fire()
 157 {
 158 #ifdef _DU_OHCI_F
 159         printf("<^>  <^>  <^> hcdi_fire(start)\n");
 160 #endif
 161
 162         if(edhead == 0)
 163                 return;
 164
 165 #ifdef _USE_C_Q
 166         /* quirk... 11ms seems to be a minimum :O */
 167         udelay(11000);
 168 #endif
 169
 170         write32(OHCI0_HC_CTRL_HEAD_ED, virt_to_phys(edhead));
 171
 172         /* sync it all */
 173         sync_after_write(edhead, sizeof(struct endpoint_descriptor));
 174 #ifdef _DU_OHCI_F
 175         dump_address(edhead, sizeof(struct endpoint_descriptor), "edhead(before)");
 176 #endif
 177
 178         struct general_td *x = phys_to_virt(LE(edhead->headp) & OHCI_ENDPOINT_HEAD_MASK);
 179         while(virt_to_phys(x)) {
 180                 sync_after_write(x, sizeof(struct general_td));
 181 #ifdef _DU_OHCI_F
 182                 dump_address(x, sizeof(struct general_td), "x(before)");
 183 #endif
 184
 185                 if(x->buflen > 0) {
 186                         sync_after_write((void*) phys_to_virt(LE(x->cbp)), x->buflen);
 187 #ifdef _DU_OHCI_F
 188                         dump_address((void*) phys_to_virt(LE(x->cbp)), x->buflen, "x->cbp(before)");
 189 #endif
 190                 }
 191                 x = phys_to_virt(LE(x->nexttd));
 192         }
 193
 194         /* trigger control list */
 195         set32(OHCI0_HC_CONTROL, OHCI_CTRL_CLE);
 196         write32(OHCI0_HC_COMMAND_STATUS, OHCI_CLF);
 197
 198         struct general_td *n=0, *prev = 0, *next = 0;
 199         /* poll until edhead->headp is null */
 200         do {
 201                 sync_before_read(edhead, sizeof(struct endpoint_descriptor));
 202 #ifdef _DU_OHCI_F
 203                 printf("edhead->headp: 0x%08X\n", LE(edhead->headp));
 204                 udelay(10000);
 205 #endif
 206
 207                 /* if halted, debug output plz. will break the transfer */
 208                 if((LE(edhead->headp) & OHCI_ENDPOINT_HALTED)) {
 209                         n = phys_to_virt(LE(edhead->headp)&~0xf);
 210                         prev = phys_to_virt((u32)prev);
 211 #ifdef _DU_OHCI_F_HALT
 212                         printf("halted!\n");
 213 #endif
 214
 215                         sync_before_read((void*) n, sizeof(struct general_td));
 216 #ifdef _DU_OHCI_F_HALT
 217                         printf("n: 0x%08X\n", n);
 218                         dump_address(n, sizeof(struct general_td), "n(after)");
 219 #endif
 220                         if(n->buflen > 0) {
 221                                 sync_before_read((void*) n->bufaddr, n->buflen);
 222 #ifdef _DU_OHCI_F_HALT
 223                                 dump_address((void*) n->bufaddr, n->buflen, "n->bufaddr(after)");
 224 #endif
 225                         }
 226 #ifdef _DU_OHCI_F_HALT
 227                         dbg_td_flag(LE(n->flags));
 228 #endif
 229
 230                         sync_before_read((void*) prev, sizeof(struct general_td));
 231 #ifdef _DU_OHCI_F_HALT
 232                         printf("prev: 0x%08X\n", prev);
 233                         dump_address(prev, sizeof(struct general_td), "prev(after)");
 234 #endif
 235                         if(prev->buflen >0) {
 236                                 sync_before_read((void*) prev->bufaddr, prev->buflen);
 237 #ifdef _DU_OHCI_F_HALT
 238                                 dump_address((void*) prev->bufaddr, prev->buflen, "prev->bufaddr(after)");
 239 #endif
 240                         }
 241 #ifdef _DU_OHCI_F_HALT
 242                         dbg_td_flag(LE(prev->flags));
 243                         printf("halted end!\n");
 244 #endif
 245                         return;
 246                 }
 247                 prev = (struct general_td*) (LE(edhead->headp)&~0xf);
 248         } while(LE(edhead->headp)&~0xf);
 249
 250         n = phys_to_virt(read32(OHCI0_HC_DONE_HEAD) & ~1);
 251 #ifdef _DU_OHCI_F
 252         printf("hc_done_head: 0x%08X\n", read32(OHCI0_HC_DONE_HEAD));
 253 #endif
 254
 255         prev = 0; next = 0;
 256         /* reverse done queue */
 257         while(virt_to_phys(n) && edhead->tdcount) {
 258                 sync_before_read((void*) n, sizeof(struct general_td));
 259 #ifdef _DU_OHCI_F
 260                 printf("n: 0x%08X\n", n);
 261                 printf("next: 0x%08X\n", next);
 262                 printf("prev: 0x%08X\n", prev);
 263 #endif
 264
 265                 next = n;
 266                 n = (struct general_td*) phys_to_virt(LE(n->nexttd));
 267                 next->nexttd = (u32) prev;
 268                 prev = next;
 269
 270                 edhead->tdcount--;
 271         }
 272
 273         n = next;
 274         prev = 0;
 275         while(virt_to_phys(n)) {
 276 #ifdef _DU_OHCI_F
 277                 dump_address(n, sizeof(struct general_td), "n(after)");
 278 #endif
 279                 if(n->buflen > 0) {
 280                         sync_before_read((void*) n->bufaddr, n->buflen);
 281 #ifdef _DU_OHCI_F
 282                         dump_address((void*) n->bufaddr, n->buflen, "n->bufaddr(after)");
 283 #endif
 284                 }
 285 #ifdef _DU_OHCI_F
 286                 dbg_td_flag(LE(n->flags));
 287 #endif
 288                 prev = n;
 289                 n = (struct general_td*) n->nexttd;
 290                 free(prev);
 291         }
 292
 293         hcca_oh0.done_head = 0;
 294         sync_after_write(&hcca_oh0, sizeof(hcca_oh0));
 295
 296         write32(OHCI0_HC_CONTROL, read32(OHCI0_HC_CONTROL)&~OHCI_CTRL_CLE);
 297
 298         edhead = 0;
 299
 300 #ifdef _DU_OHCI_F
 301         printf("<^>  <^>  <^> hcdi_fire(end)\n");
 302 #endif
 303 }
 304
 305 /**
 306  * Enqueue a transfer descriptor.
 307  */
 308 u8 hcdi_enqueue(const struct usb_transfer_descriptor *td) {
 309 #ifdef _DU_OHCI_Q
 310         printf("*()*()*()*()*()*()*() hcdi_enqueue(start)\n");
 311 #endif
 312         if(!edhead) {
 313                 edhead = &_edhead;
 314                 memset(edhead, 0, sizeof(struct endpoint_descriptor));
 315                 edhead->flags = LE(OHCI_ENDPOINT_GENERAL_FORMAT);
 316                 edhead->headp = edhead->tailp = edhead->nexted = LE(0);
 317                 edhead->flags |= LE(OHCI_ENDPOINT_LOW_SPEED |
 318                                 OHCI_ENDPOINT_SET_DEVICE_ADDRESS(td->devaddress) |
 319                                 OHCI_ENDPOINT_SET_ENDPOINT_NUMBER(td->endpoint) |
 320                                 OHCI_ENDPOINT_SET_MAX_PACKET_SIZE(td->maxp));
 321                 edhead->tdcount = 0;
 322         }
 323
 324         struct general_td *tdhw = allocate_general_td();
 325         general_td_fill(tdhw, td);
 326         edhead->tdcount ++;
 327
 328         if(!edhead->headp) {
 329                 /* first transfer */
 330                 edhead->headp = LE(virt_to_phys((void*) ((u32)tdhw & OHCI_ENDPOINT_HEAD_MASK)));
 331         }
 332         else {
 333                 /* headp in endpoint already exists
 334                  * => go to list end
 335                  */
 336                 struct general_td *n = (struct general_td*) phys_to_virt(LE(edhead->headp) & OHCI_ENDPOINT_HEAD_MASK);
 337                 while(LE(n->nexttd)) {
 338                         n = phys_to_virt(LE(n->nexttd));
 339                 }
 340                 n->nexttd = LE(virt_to_phys((void*) ((u32)tdhw & OHCI_ENDPOINT_HEAD_MASK)));
 341 #ifdef _DU_OHCI_Q
 342                 printf("n: 0x%08X\n", n);
 343                 printf("n->nexttd: 0x%08X\n", phys_to_virt(LE(n->nexttd)));
 344 #endif
 345         }
 346
 347 #ifdef _DU_OHCI_Q
 348         printf("*()*()*()*()*()*()*() hcdi_enqueue(end)\n");
 349 #endif
 350         return 0;
 351 }
 352
 353
 354 /**
 355  * Remove an transfer descriptor from transfer queue.
 356  */
 357 u8 hcdi_dequeue(struct usb_transfer_descriptor *td) {
 358         return 0;
 359 }
 360
 361 void hcdi_init()
 362 {
 363         printf("ohci-- init\n");
 364         dbg_op_state();
 365
 366         /* disable hc interrupts */
 367         set32(OHCI0_HC_INT_DISABLE, OHCI_INTR_MIE);
 368
 369         /* save fmInterval and calculate FSMPS */
 370 #define FSMP(fi) (0x7fff & ((6 * ((fi) - 210)) / 7))
 371 #define FI 0x2edf /* 12000 bits per frame (-1) */
 372         u32 fmint = read32(OHCI0_HC_FM_INTERVAL) & 0x3fff;
 373         if(fmint != FI)
 374                 printf("ohci-- fminterval delta: %d\n", fmint - FI);
 375         fmint |= FSMP (fmint) << 16;
 376
 377         /* enable interrupts of both usb host controllers */
 378         set32(EHCI_CTL, EHCI_CTL_OH0INTE | EHCI_CTL_OH1INTE | 0xe0000);
 379
 380         /* reset HC */
 381         write32(OHCI0_HC_COMMAND_STATUS, OHCI_HCR);
 382
 383         /* wait max. 30us */
 384         u32 ts = 30;
 385         while ((read32(OHCI0_HC_COMMAND_STATUS) & OHCI_HCR) != 0) {
 386                  if(--ts == 0) {
 387                         printf("ohci-- FAILED");
 388                         return;
 389                  }
 390                  udelay(1);
 391         }
 392
 393         /* disable interrupts; 2ms timelimit here!
 394            now we're in the SUSPEND state ... must go OPERATIONAL
 395            within 2msec else HC enters RESUME */
 396
 397         u32 cookie = irq_kill();
 398
 399         /* Tell the controller where the control and bulk lists are
 400          * The lists are empty now. */
 401         write32(OHCI0_HC_CTRL_HEAD_ED, 0);
 402         write32(OHCI0_HC_BULK_HEAD_ED, 0);
 403
 404         /* set hcca adress */
 405         sync_after_write(&hcca_oh0, 256);
 406         write32(OHCI0_HC_HCCA, virt_to_phys(&hcca_oh0));
 407
 408         /* set periodicstart */
 409 #define FIT (1<<31)
 410         u32 fmInterval = read32(OHCI0_HC_FM_INTERVAL) &0x3fff;
 411         u32 fit = read32(OHCI0_HC_FM_INTERVAL) & FIT;
 412
 413         write32(OHCI0_HC_FM_INTERVAL, fmint | (fit ^ FIT));
 414         write32(OHCI0_HC_PERIODIC_START, ((9*fmInterval)/10)&0x3fff);
 415
 416         /* testing bla */
 417         if ((read32(OHCI0_HC_FM_INTERVAL) & 0x3fff0000) == 0 || !read32(OHCI0_HC_PERIODIC_START)) {
 418                 printf("ohci-- w00t, fail!! see ohci-hcd.c:669\n");
 419         }
 420
 421         /* start HC operations */
 422         write32(OHCI0_HC_CONTROL, OHCI_CONTROL_INIT | OHCI_USB_OPER);
 423
 424         /* wake on ConnectStatusChange, matching external hubs */
 425         write32(OHCI0_HC_RH_STATUS, /*RH_HS_DRWE |*/ RH_HS_LPSC);
 426
 427         /* Choose the interrupts we care about now, others later on demand */
 428         write32(OHCI0_HC_INT_STATUS, ~0);
 429         write32(OHCI0_HC_INT_ENABLE, OHCI_INTR_INIT);
 430
 431         //wtf?
 432         wait_ms ((read32(OHCI0_HC_RH_DESCRIPTOR_A) >> 23) & 0x1fe);
 433
 434         configure_ports((u8)1);
 435         irq_restore(cookie);
 436
 437         dbg_op_state();
 438 }
 439
 440 static void configure_ports(u8 from_init)
 441 {
 442 #ifdef _DU_OHCI_RH
 443         printf("OHCI0_HC_RH_DESCRIPTOR_A:\t0x%08X\n", read32(OHCI0_HC_RH_DESCRIPTOR_A));
 444         printf("OHCI0_HC_RH_DESCRIPTOR_B:\t0x%08X\n", read32(OHCI0_HC_RH_DESCRIPTOR_B));
 445         printf("OHCI0_HC_RH_STATUS:\t\t0x%08X\n", read32(OHCI0_HC_RH_STATUS));
 446         printf("OHCI0_HC_RH_PORT_STATUS_1:\t0x%08X\n", read32(OHCI0_HC_RH_PORT_STATUS_1));
 447         printf("OHCI0_HC_RH_PORT_STATUS_2:\t0x%08X\n", read32(OHCI0_HC_RH_PORT_STATUS_2));
 448 #endif
 449
 450         setup_port(OHCI0_HC_RH_PORT_STATUS_1, from_init);
 451         setup_port(OHCI0_HC_RH_PORT_STATUS_2, from_init);
 452 #ifdef _DU_OHCI_RH
 453         printf("configure_ports done\n");
 454 #endif
 455 }
 456
 457 static void setup_port(u32 reg, u8 from_init)
 458 {
 459         u32 port = read32(reg);
 460         if((port & RH_PS_CCS) && ((port & RH_PS_CSC) || from_init)) {
 461                 write32(reg, RH_PS_CSC);
 462
 463                 wait_ms(120);
 464
 465                 /* clear CSC flag, set PES and start port reset (PRS) */
 466                 write32(reg, RH_PS_PES);
 467                 while(!(read32(reg) & RH_PS_PES)) {
 468 #ifdef _DU_OHCI_RH
 469                         printf("fu\n");
 470 #endif
 471                         return;
 472                 }
 473
 474                 write32(reg, RH_PS_PRS);
 475
 476                 /* spin until port reset is complete */
 477                 while(!(read32(reg) & RH_PS_PRSC)); // hint: it may stuck here
 478 #ifdef _DU_OHCI_RH
 479                 printf("loop done\n");
 480 #endif
 481
 482                 (void) usb_add_device();
 483         }
 484 }
 485
 486 void hcdi_irq()
 487 {
 488         /* read interrupt status */
 489         u32 flags = read32(OHCI0_HC_INT_STATUS);
 490
 491         /* when all bits are set to 1 some problem occured */
 492         if (flags == 0xffffffff) {
 493                 printf("ohci-- Houston, we have a serious problem! :(\n");
 494                 return;
 495         }
 496
 497         /* only care about interrupts that are enabled */
 498         flags &= read32(OHCI0_HC_INT_ENABLE);
 499
 500         /* nothing to do? */
 501         if (flags == 0) {
 502                 printf("OHCI Interrupt occured: but not for you! WTF?!\n");
 503                 return;
 504         }
 505
 506         printf("OHCI Interrupt occured: ");
 507         /* UnrecoverableError */
 508         if (flags & OHCI_INTR_UE) {
 509                 printf("UnrecoverableError\n");
 510                 /* TODO: well, I don't know... nothing,
 511                  *       because it won't happen anyway? ;-) */
 512         }
 513
 514         /* RootHubStatusChange */
 515         if (flags & OHCI_INTR_RHSC) {
 516                 printf("RootHubStatusChange\n");
 517                 /* TODO: set some next_statechange variable... */
 518                 configure_ports(0);
 519                 write32(OHCI0_HC_INT_STATUS, OHCI_INTR_RD | OHCI_INTR_RHSC);
 520         }
 521         /* ResumeDetected */
 522         else if (flags & OHCI_INTR_RD) {
 523                 printf("ResumeDetected\n");
 524                 write32(OHCI0_HC_INT_STATUS, OHCI_INTR_RD);
 525                 /* TODO: figure out what the linux kernel does here... */
 526         }
 527
 528         /* WritebackDoneHead */
 529         if (flags & OHCI_INTR_WDH) {
 530                 printf("WritebackDoneHead\n");
 531                 /* basically the linux irq handler reverse TDs to their urbs
 532                  * and set done_head to null.
 533                  * since we are polling atm, just should do the latter task.
 534                  * however, this won't work for now (i don't know why...)
 535                  * TODO!
 536                  */
 537 #if 0
 538                 sync_before_read(&hcca_oh0, 256);
 539                 hcca_oh0.done_head = 0;
 540                 sync_after_write(&hcca_oh0, 256);
 541 #endif
 542         }
 543
 544         /* TODO: handle any pending URB/ED unlinks... */
 545
 546 #define HC_IS_RUNNING() 1 /* dirty, i know... just a temporary solution */
 547         if (HC_IS_RUNNING()) {
 548                 write32(OHCI0_HC_INT_STATUS, flags);
 549                 write32(OHCI0_HC_INT_ENABLE, OHCI_INTR_MIE);
 550         }
 551 }
 552
 553 void show_frame_no()
 554 {
 555         sync_before_read(&hcca_oh0, 256);
 556         printf("***** frame_no: %d *****\n", LE(hcca_oh0.frame_no));
 557 }