usb/host/ohci.c

   1 /*
   2        ppcskel - a Free Software replacement for the Nintendo/BroadOn bootloader.
   3        ohci hardware support
   4
   5 Copyright (C) 2009     Bernhard Urban <lewurm@gmx.net>
   6 Copyright (C) 2009     Sebastian Falbesoner <sebastian.falbesoner@gmail.com>
   7
   8 # This code is licensed to you under the terms of the GNU GPL, version 2;
   9 # see file COPYING or http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt
  10 */
  11
  12 #include "../../bootmii_ppc.h"
  13 #include "../../hollywood.h"
  14 #include "../../irq.h"
  15 #include "../../string.h"
  16 #include "../../malloc.h"
  17 #include "ohci.h"
  18 #include "host.h"
  19 #include "../usbspec/usb11spec.h"
  20
  21 /* macro for accessing u32 variables that need to be in little endian byte order;
  22  *
  23  * whenever you read or write from an u32 field that the ohci host controller
  24  * will read or write from too, use this macro for access!
  25  */
  26 #define LE(dword) (u32)( (((dword) & 0xFF000000) >> 24) | \
  27                            (((dword) & 0x00FF0000) >> 8)  | \
  28                            (((dword) & 0x0000FF00) << 8)  | \
  29                            (((dword) & 0x000000FF) << 24) )
  30
  31 static struct endpoint_descriptor *allocate_endpoint();
  32 static struct general_td *allocate_general_td();
  33 static void control_quirk();
  34 static void dbg_op_state();
  35 //static void dbg_td_flag(u32 flag);
  36 static void configure_ports(u8 from_init);
  37 static void setup_port(u32 reg, u8 from_init);
  38
  39 static struct ohci_hcca hcca_oh0;
  40
  41
  42 static struct endpoint_descriptor *allocate_endpoint()
  43 {
  44         struct endpoint_descriptor *ep;
  45         ep = (struct endpoint_descriptor *)memalign(16, sizeof(struct endpoint_descriptor));
  46         memset(ep, 0, sizeof(struct endpoint_descriptor));
  47         ep->flags = LE(OHCI_ENDPOINT_GENERAL_FORMAT);
  48         ep->headp = ep->tailp = ep->nexted = LE(0);
  49         return ep;
  50 }
  51
  52 static struct general_td *allocate_general_td()
  53 {
  54         struct general_td *td;
  55         td = (struct general_td *)memalign(16, sizeof(struct general_td));
  56         memset(td, 0, sizeof(struct general_td));
  57         td->flags = LE(0);
  58         td->nexttd = LE(0);
  59         td->cbp = td->be = LE(0);
  60         return td;
  61 }
  62
  63 static void control_quirk()
  64 {
  65         static struct endpoint_descriptor *ed = 0; /* empty ED */
  66         static struct general_td *td = 0; /* dummy TD */
  67         u32 head;
  68         u32 current;
  69         u32 status;
  70
  71         /*
  72          * One time only.
  73          * Allocate and keep a special empty ED with just a dummy TD.
  74          */
  75         if (!ed) {
  76                 ed = allocate_endpoint();
  77                 if (!ed)
  78                         return;
  79
  80                 td = allocate_general_td(0);
  81                 if (!td) {
  82                         free(ed);
  83                         ed = NULL;
  84                         return;
  85                 }
  86
  87                 ed->tailp = ed->headp = LE(virt_to_phys((void*) ((u32)td & OHCI_ENDPOINT_HEAD_MASK)));
  88                 ed->flags |= LE(OHCI_ENDPOINT_DIRECTION_OUT);
  89         }
  90
  91         /*
  92          * The OHCI USB host controllers on the Nintendo Wii
  93          * video game console stop working when new TDs are
  94          * added to a scheduled control ED after a transfer has
  95          * has taken place on it.
  96          *
  97          * Before scheduling any new control TD, we make the
  98          * controller happy by always loading a special control ED
  99          * with a single dummy TD and letting the controller attempt
 100          * the transfer.
 101          * The controller won't do anything with it, as the special
 102          * ED has no TDs, but it will keep the controller from failing
 103          * on the next transfer.
 104          */
 105         head = read32(OHCI0_HC_CTRL_HEAD_ED);
 106         if (head) {
 107                 printf("head: 0x%08X\n", head);
 108                 /*
 109                  * Load the special empty ED and tell the controller to
 110                  * process the control list.
 111                  */
 112                 sync_after_write(ed, 16);
 113                 sync_after_write(td, 16);
 114                 write32(OHCI0_HC_CTRL_HEAD_ED, virt_to_phys(ed));
 115
 116                 status = read32(OHCI0_HC_CONTROL);
 117                 set32(OHCI0_HC_CONTROL, OHCI_CTRL_CLE);
 118                 write32(OHCI0_HC_COMMAND_STATUS, OHCI_CLF);
 119
 120                 /* spin until the controller is done with the control list */
 121                 current = read32(OHCI0_HC_CTRL_CURRENT_ED);
 122                 while(!current) {
 123                         udelay(10);
 124                         current = read32(OHCI0_HC_CTRL_CURRENT_ED);
 125                 }
 126
 127                 printf("current: 0x%08X\n", current);
 128
 129                 /* restore the old control head and control settings */
 130                 write32(OHCI0_HC_CONTROL, status);
 131                 write32(OHCI0_HC_CTRL_HEAD_ED, head);
 132         } else {
 133                 printf("nohead!\n");
 134         }
 135 }
 136
 137
 138 static void dbg_op_state()
 139 {
 140         switch (read32(OHCI0_HC_CONTROL) & OHCI_CTRL_HCFS) {
 141                 case OHCI_USB_SUSPEND:
 142                         printf("ohci-- OHCI_USB_SUSPEND\n");
 143                         break;
 144                 case OHCI_USB_RESET:
 145                         printf("ohci-- OHCI_USB_RESET\n");
 146                         break;
 147                 case OHCI_USB_OPER:
 148                         printf("ohci-- OHCI_USB_OPER\n");
 149                         break;
 150                 case OHCI_USB_RESUME:
 151                         printf("ohci-- OHCI_USB_RESUME\n");
 152                         break;
 153         }
 154 }
 155
 156 static void dbg_td_flag(u32 flag)
 157 {
 158         printf("**************** dbg_td_flag: 0x%08X ***************\n", flag);
 159         printf("CC: %X\tshould be 0, see page 32 (ohci spec)\n", (flag>>28)&0xf);
 160         printf("EC: %X\tsee page 20 (ohci spec)\n", (flag>>26)&3);
 161         printf(" T: %X\n", (flag>>24)&3);
 162         printf("DI: %X\n", (flag>>21)&7);
 163         printf("DP: %X\n", (flag>>19)&3);
 164         printf(" R: %X\n", (flag>>18)&1);
 165         printf("********************************************************\n");
 166 }
 167
 168 static void general_td_fill(struct general_td *dest, const usb_transfer_descriptor *src)
 169 {
 170         if(src->actlen) {
 171                 dest->cbp = LE(virt_to_phys(src->buffer));
 172                 dest->be = LE(LE(dest->cbp) + src->actlen - 1);
 173                 /* save virtual address here */
 174                 dest->bufaddr = (u32) src->buffer;
 175         }
 176         else {
 177                 dest->cbp = dest->be = LE(0);
 178                 dest->bufaddr = 0;
 179         }
 180
 181         dest->buflen = src->actlen;
 182
 183         dest->flags &= LE(~OHCI_TD_DIRECTION_PID_MASK);
 184         switch(src->pid) {
 185                 case USB_PID_SETUP:
 186                         printf("pid_setup\n");
 187                         dest->flags |= LE(OHCI_TD_DIRECTION_PID_SETUP);
 188                         dest->flags |= LE(OHCI_TD_TOGGLE_0);
 189                         dest->flags |= LE(OHCI_TD_BUFFER_ROUNDING);
 190                         break;
 191                 case USB_PID_OUT:
 192                         printf("pid_out\n");
 193                         dest->flags |= LE(OHCI_TD_DIRECTION_PID_OUT);
 194                         dest->flags |= LE(OHCI_TD_BUFFER_ROUNDING);
 195
 196                         /*
 197                          * TODO: just temporary solution! (consider it with len?)
 198                          * there can be also regular PID_OUT pakets
 199                          */
 200                         dest->flags |= LE(OHCI_TD_TOGGLE_1);
 201                         break;
 202                 case USB_PID_IN:
 203                         printf("pid_in\n");
 204                         dest->flags |= LE(OHCI_TD_DIRECTION_PID_IN);
 205                         dest->flags |= LE(OHCI_TD_BUFFER_ROUNDING);
 206                         /*
 207                          * let the endpoint do the togglestuff!
 208                          * TODO: just temporary solution!
 209                          * there can be also inregular PID_IN pakets (@Status Stage)
 210                          */
 211                         dest->flags |= LE(OHCI_TD_TOGGLE_CARRY);
 212 #if 0
 213                         /* should be done by HC!
 214                          * first pid_in start with DATA0 */
 215                          */
 216                         dummyconfig.headp = LE( src->togl ?
 217                                         LE(dummyconfig.headp) | OHCI_ENDPOINT_TOGGLE_CARRY :
 218                                         LE(dummyconfig.headp) & ~OHCI_ENDPOINT_TOGGLE_CARRY);
 219 #endif
 220                         break;
 221         }
 222         dest->flags |= LE(OHCI_TD_SET_DELAY_INTERRUPT(7));
 223 }
 224
 225 static void dump_address(void *addr, u32 size, const char* str)
 226 {
 227         printf("%s hexdump (%d) @ 0x%08X:\n", str, size, addr);
 228         hexdump(addr, size);
 229 }
 230
 231 struct endpoint_descriptor *edhead = 0;
 232 void hcdi_fire()
 233 {
 234         printf("<^>  <^>  <^> hcdi_fire(start)\n");
 235
 236         if(edhead == 0)
 237                 return;
 238
 239         control_quirk(); //required? YES! :O ... erm... or no? :/ ... in fact I have no idea
 240         write32(OHCI0_HC_CTRL_HEAD_ED, virt_to_phys(edhead));
 241
 242         /* sync it all */
 243         sync_after_write(edhead, sizeof(struct endpoint_descriptor));
 244         dump_address(edhead, sizeof(struct endpoint_descriptor), "edhead(before)");
 245
 246         struct general_td *x = phys_to_virt(LE(edhead->headp) & OHCI_ENDPOINT_HEAD_MASK);
 247         printf("STRUCT LEN: %d\n", sizeof(struct general_td));
 248         while(virt_to_phys(x)) {
 249                 sync_after_write(x, sizeof(struct general_td));
 250                 dump_address(x, sizeof(struct general_td), "x(before)");
 251
 252                 if(x->buflen > 0) {
 253                         sync_after_write((void*) phys_to_virt(LE(x->cbp)), x->buflen);
 254                         dump_address((void*) phys_to_virt(LE(x->cbp)), x->buflen, "x->cbp(before)");
 255                 }
 256                 x = phys_to_virt(LE(x->nexttd));
 257         }
 258
 259         /* trigger control list */
 260         set32(OHCI0_HC_CONTROL, OHCI_CTRL_CLE);
 261         write32(OHCI0_HC_COMMAND_STATUS, OHCI_CLF);
 262
 263         /* poll until edhead->headp is null */
 264         do {
 265                 sync_before_read(edhead, sizeof(struct endpoint_descriptor));
 266                 printf("edhead->headp: 0x%08X\n", LE(edhead->headp));
 267         } while(LE(edhead->headp)&~0xf);
 268
 269         struct general_td *n = phys_to_virt(read32(OHCI0_HC_DONE_HEAD) & ~1);
 270         printf("hc_done_head: 0x%08X\n", read32(OHCI0_HC_DONE_HEAD));
 271
 272         struct general_td *prev = 0, *next = 0;
 273         /* reverse done queue */
 274         while(virt_to_phys(n) && edhead->tdcount) {
 275                 sync_before_read((void*) n, sizeof(struct general_td));
 276                 printf("n: 0x%08X\n", n);
 277                 printf("next: 0x%08X\n", next);
 278                 printf("prev: 0x%08X\n", prev);
 279
 280                 next = n;
 281                 n = (struct general_td*) phys_to_virt(LE(n->nexttd));
 282                 next->nexttd = (u32) prev;
 283                 prev = next;
 284
 285                 edhead->tdcount--;
 286         }
 287
 288         n = next;
 289         prev = 0;
 290         while(virt_to_phys(n)) {
 291                 dump_address(n, sizeof(struct general_td), "n(after)");
 292
 293                 if(n->buflen > 0) {
 294                         sync_before_read((void*) n->bufaddr, n->buflen);
 295                         dump_address((void*) n->bufaddr, n->buflen, "n->bufaddr(after)");
 296                 }
 297                 dbg_td_flag(LE(n->flags));
 298                 prev = n;
 299                 n = (struct general_td*) n->nexttd;
 300                 free(prev);
 301         }
 302
 303         hcca_oh0.done_head = 0;
 304         sync_after_write(&hcca_oh0, sizeof(hcca_oh0));
 305
 306         write32(OHCI0_HC_CONTROL, read32(OHCI0_HC_CONTROL)&~OHCI_CTRL_CLE);
 307
 308         free(edhead);
 309         edhead = 0;
 310
 311         printf("<^>  <^>  <^> hcdi_fire(end)\n");
 312 }
 313
 314 /**
 315  * Enqueue a transfer descriptor.
 316  */
 317 u8 hcdi_enqueue(const usb_transfer_descriptor *td) {
 318         printf("*()*()*()*()*()*()*() hcdi_enqueue(start)\n");
 319         if(!edhead) {
 320                 edhead = allocate_endpoint();
 321                 edhead->flags = LE(OHCI_ENDPOINT_GENERAL_FORMAT);
 322                 edhead->headp = edhead->tailp = edhead->nexted = LE(0);
 323                 edhead->flags |= LE(OHCI_ENDPOINT_LOW_SPEED |
 324                                 OHCI_ENDPOINT_SET_DEVICE_ADDRESS(td->devaddress) |
 325                                 OHCI_ENDPOINT_SET_ENDPOINT_NUMBER(td->endpoint) |
 326                                 OHCI_ENDPOINT_SET_MAX_PACKET_SIZE(td->maxp));
 327                 edhead->tdcount = 0;
 328         }
 329
 330         struct general_td *tdhw = allocate_general_td();
 331         general_td_fill(tdhw, td);
 332         edhead->tdcount ++;
 333
 334         if(!edhead->headp) {
 335                 /* first transfer */
 336                 edhead->headp = LE(virt_to_phys((void*) ((u32)tdhw & OHCI_ENDPOINT_HEAD_MASK)));
 337         }
 338         else {
 339                 /* headp in endpoint already exists
 340                  * => go to list end
 341                  */
 342                 struct general_td *n = (struct general_td*) phys_to_virt(LE(edhead->headp) & OHCI_ENDPOINT_HEAD_MASK);
 343                 while(LE(n->nexttd)) {
 344                         n = phys_to_virt(LE(n->nexttd));
 345                 }
 346                 n->nexttd = LE(virt_to_phys((void*) ((u32)tdhw & OHCI_ENDPOINT_HEAD_MASK)));
 347                 printf("n: 0x%08X\n", n);
 348                 printf("n->nexttd: 0x%08X\n", phys_to_virt(LE(n->nexttd)));
 349         }
 350
 351         printf("*()*()*()*()*()*()*() hcdi_enqueue(end)\n");
 352         return 0;
 353 }
 354
 355
 356 /**
 357  * Remove an transfer descriptor from transfer queue.
 358  */
 359 u8 hcdi_dequeue(usb_transfer_descriptor *td) {
 360         return 0;
 361 }
 362
 363 void hcdi_init()
 364 {
 365         printf("ohci-- init\n");
 366         dbg_op_state();
 367
 368         /* disable hc interrupts */
 369         set32(OHCI0_HC_INT_DISABLE, OHCI_INTR_MIE);
 370
 371 #if 1
 372         /* after a warm start we have some really odd memory issues.
 373          * some malloc/free/sync/mmu fail?! no idea!
 374          */
 375         if((read32(OHCI0_HC_CONTROL) & OHCI_CTRL_HCFS) != OHCI_USB_RESET) {
 376                 (void) malloc(256);
 377                 printf("WTF malloc\n");
 378         }
 379 #endif
 380
 381         /* save fmInterval and calculate FSMPS */
 382 #define FSMP(fi) (0x7fff & ((6 * ((fi) - 210)) / 7))
 383 #define FI 0x2edf /* 12000 bits per frame (-1) */
 384         u32 fmint = read32(OHCI0_HC_FM_INTERVAL) & 0x3fff;
 385         if(fmint != FI)
 386                 printf("ohci-- fminterval delta: %d\n", fmint - FI);
 387         fmint |= FSMP (fmint) << 16;
 388
 389         /* enable interrupts of both usb host controllers */
 390         set32(EHCI_CTL, EHCI_CTL_OH0INTE | EHCI_CTL_OH1INTE | 0xe0000);
 391
 392         /* reset HC */
 393         write32(OHCI0_HC_COMMAND_STATUS, OHCI_HCR);
 394
 395         /* wait max. 30us */
 396         u32 ts = 30;
 397         while ((read32(OHCI0_HC_COMMAND_STATUS) & OHCI_HCR) != 0) {
 398                  if(--ts == 0) {
 399                         printf("ohci-- FAILED");
 400                         return;
 401                  }
 402                  udelay(1);
 403         }
 404
 405         /* disable interrupts; 2ms timelimit here!
 406            now we're in the SUSPEND state ... must go OPERATIONAL
 407            within 2msec else HC enters RESUME */
 408
 409         u32 cookie = irq_kill();
 410
 411         /* Tell the controller where the control and bulk lists are
 412          * The lists are empty now. */
 413         write32(OHCI0_HC_CTRL_HEAD_ED, 0);
 414         write32(OHCI0_HC_BULK_HEAD_ED, 0);
 415
 416         /* set hcca adress */
 417         sync_after_write(&hcca_oh0, 256);
 418         write32(OHCI0_HC_HCCA, virt_to_phys(&hcca_oh0));
 419
 420         /* set periodicstart */
 421 #define FIT (1<<31)
 422         u32 fmInterval = read32(OHCI0_HC_FM_INTERVAL) &0x3fff;
 423         u32 fit = read32(OHCI0_HC_FM_INTERVAL) & FIT;
 424
 425         write32(OHCI0_HC_FM_INTERVAL, fmint | (fit ^ FIT));
 426         write32(OHCI0_HC_PERIODIC_START, ((9*fmInterval)/10)&0x3fff);
 427
 428         /* testing bla */
 429         if ((read32(OHCI0_HC_FM_INTERVAL) & 0x3fff0000) == 0 || !read32(OHCI0_HC_PERIODIC_START)) {
 430                 printf("ohci-- w00t, fail!! see ohci-hcd.c:669\n");
 431         }
 432
 433         /* start HC operations */
 434         write32(OHCI0_HC_CONTROL, OHCI_CONTROL_INIT | OHCI_USB_OPER);
 435
 436         /* wake on ConnectStatusChange, matching external hubs */
 437         write32(OHCI0_HC_RH_STATUS, /*RH_HS_DRWE |*/ RH_HS_LPSC);
 438
 439         /* Choose the interrupts we care about now, others later on demand */
 440         write32(OHCI0_HC_INT_STATUS, ~0);
 441         write32(OHCI0_HC_INT_ENABLE, OHCI_INTR_INIT);
 442
 443         //wtf?
 444         wait_ms ((read32(OHCI0_HC_RH_DESCRIPTOR_A) >> 23) & 0x1fe);
 445
 446         configure_ports((u8)1);
 447         irq_restore(cookie);
 448
 449         dbg_op_state();
 450 }
 451
 452 static void configure_ports(u8 from_init)
 453 {
 454         printf("OHCI0_HC_RH_DESCRIPTOR_A:\t0x%08X\n", read32(OHCI0_HC_RH_DESCRIPTOR_A));
 455         printf("OHCI0_HC_RH_DESCRIPTOR_B:\t0x%08X\n", read32(OHCI0_HC_RH_DESCRIPTOR_B));
 456         printf("OHCI0_HC_RH_STATUS:\t\t0x%08X\n", read32(OHCI0_HC_RH_STATUS));
 457         printf("OHCI0_HC_RH_PORT_STATUS_1:\t0x%08X\n", read32(OHCI0_HC_RH_PORT_STATUS_1));
 458         printf("OHCI0_HC_RH_PORT_STATUS_2:\t0x%08X\n", read32(OHCI0_HC_RH_PORT_STATUS_2));
 459
 460         setup_port(OHCI0_HC_RH_PORT_STATUS_1, from_init);
 461         setup_port(OHCI0_HC_RH_PORT_STATUS_2, from_init);
 462         printf("configure_ports done\n");
 463 }
 464
 465 static void setup_port(u32 reg, u8 from_init)
 466 {
 467         u32 port = read32(reg);
 468         if((port & RH_PS_CCS) && ((port & RH_PS_CSC) || from_init)) {
 469                 write32(reg, RH_PS_CSC);
 470
 471                 wait_ms(120);
 472
 473                 /* clear CSC flag, set PES and start port reset (PRS) */
 474                 write32(reg, RH_PS_PES);
 475                 while(!(read32(reg) & RH_PS_PES)) {
 476                         printf("fu\n");
 477                         return;
 478                 }
 479
 480                 write32(reg, RH_PS_PRS);
 481
 482                 /* spin until port reset is complete */
 483                 while(!(read32(reg) & RH_PS_PRSC)); // hint: it may stuck here
 484                 printf("loop done\n");
 485
 486                 (void) usb_add_device();
 487         }
 488 }
 489
 490 void hcdi_irq()
 491 {
 492         /* read interrupt status */
 493         u32 flags = read32(OHCI0_HC_INT_STATUS);
 494
 495         /* when all bits are set to 1 some problem occured */
 496         if (flags == 0xffffffff) {
 497                 printf("ohci-- Houston, we have a serious problem! :(\n");
 498                 return;
 499         }
 500
 501         /* only care about interrupts that are enabled */
 502         flags &= read32(OHCI0_HC_INT_ENABLE);
 503
 504         /* nothing to do? */
 505         if (flags == 0) {
 506                 printf("OHCI Interrupt occured: but not for you! WTF?!\n");
 507                 return;
 508         }
 509
 510         printf("OHCI Interrupt occured: ");
 511         /* UnrecoverableError */
 512         if (flags & OHCI_INTR_UE) {
 513                 printf("UnrecoverableError\n");
 514                 /* TODO: well, I don't know... nothing,
 515                  *       because it won't happen anyway? ;-) */
 516         }
 517
 518         /* RootHubStatusChange */
 519         if (flags & OHCI_INTR_RHSC) {
 520                 printf("RootHubStatusChange\n");
 521                 /* TODO: set some next_statechange variable... */
 522                 configure_ports(0);
 523                 write32(OHCI0_HC_INT_STATUS, OHCI_INTR_RD | OHCI_INTR_RHSC);
 524         }
 525         /* ResumeDetected */
 526         else if (flags & OHCI_INTR_RD) {
 527                 printf("ResumeDetected\n");
 528                 write32(OHCI0_HC_INT_STATUS, OHCI_INTR_RD);
 529                 /* TODO: figure out what the linux kernel does here... */
 530         }
 531
 532         /* WritebackDoneHead */
 533         if (flags & OHCI_INTR_WDH) {
 534                 printf("WritebackDoneHead\n");
 535                 /* basically the linux irq handler reverse TDs to their urbs
 536                  * and set done_head to null.
 537                  * since we are polling atm, just should do the latter task.
 538                  * however, this won't work for now (i don't know why...)
 539                  * TODO!
 540                  */
 541 #if 0
 542                 sync_before_read(&hcca_oh0, 256);
 543                 hcca_oh0.done_head = 0;
 544                 sync_after_write(&hcca_oh0, 256);
 545 #endif
 546         }
 547
 548         /* TODO: handle any pending URB/ED unlinks... */
 549
 550 #define HC_IS_RUNNING() 1 /* dirty, i know... just a temporary solution */
 551         if (HC_IS_RUNNING()) {
 552                 write32(OHCI0_HC_INT_STATUS, flags);
 553                 write32(OHCI0_HC_INT_ENABLE, OHCI_INTR_MIE);
 554         }
 555 }
 556
 557 void show_frame_no()
 558 {
 559         sync_before_read(&hcca_oh0, 256);
 560         printf("***** frame_no: %d *****\n", LE(hcca_oh0.frame_no));
 561 }