2 ppcskel - a Free Software replacement for the Nintendo/BroadOn bootloader.
5 Copyright (C) 2009 Bernhard Urban <lewurm@gmx.net>
6 Copyright (C) 2009 Sebastian Falbesoner <sebastian.falbesoner@gmail.com>
8 # This code is licensed to you under the terms of the GNU GPL, version 2;
9 # see file COPYING or http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt
12 #include "../../bootmii_ppc.h"
13 #include "../../hollywood.h"
14 #include "../../irq.h"
15 #include "../../string.h"
16 #include "../../malloc.h"
19 #include "../usbspec/usb11spec.h"
21 /* activate control_quirk */
24 /* macro for accessing u32 variables that need to be in little endian byte order;
26 * whenever you read or write from an u32 field that the ohci host controller
27 * will read or write from too, use this macro for access!
29 #define LE(dword) (u32)( (((dword) & 0xFF000000) >> 24) | \
30 (((dword) & 0x00FF0000) >> 8) | \
31 (((dword) & 0x0000FF00) << 8) | \
32 (((dword) & 0x000000FF) << 24) )
34 static struct general_td *allocate_general_td();
35 static void dbg_op_state();
36 static void configure_ports(u8 from_init);
37 static void setup_port(u32 reg, u8 from_init);
39 static struct ohci_hcca hcca_oh0;
42 static struct general_td *allocate_general_td()
44 struct general_td *td;
45 td = (struct general_td *)memalign(16, sizeof(struct general_td));
46 memset(td, 0, sizeof(struct general_td));
49 td->cbp = td->be = LE(0);
54 static void dbg_op_state()
56 switch (read32(OHCI0_HC_CONTROL) & OHCI_CTRL_HCFS) {
57 case OHCI_USB_SUSPEND:
58 printf("ohci-- OHCI_USB_SUSPEND\n");
61 printf("ohci-- OHCI_USB_RESET\n");
64 printf("ohci-- OHCI_USB_OPER\n");
67 printf("ohci-- OHCI_USB_RESUME\n");
72 #ifdef _DU_OHCI_F_HALT
73 static void dbg_td_flag(u32 flag)
75 printf("**************** dbg_td_flag: 0x%08X ***************\n", flag);
76 printf("CC: %X\tshould be 0, see page 32 (ohci spec)\n", (flag>>28)&0xf);
77 printf("EC: %X\tsee page 20 (ohci spec)\n", (flag>>26)&3);
78 printf(" T: %X\n", (flag>>24)&3);
79 printf("DI: %X\n", (flag>>21)&7);
80 printf("DP: %X\n", (flag>>19)&3);
81 printf(" R: %X\n", (flag>>18)&1);
82 printf("********************************************************\n");
86 static void general_td_fill(struct general_td *dest, const struct usb_transfer_descriptor *src)
89 dest->cbp = LE(virt_to_phys(src->buffer));
90 dest->be = LE(LE(dest->cbp) + src->actlen - 1);
91 /* save virtual address here */
92 dest->bufaddr = (u32) src->buffer;
95 dest->cbp = dest->be = LE(0);
99 dest->buflen = src->actlen;
101 dest->flags &= LE(~OHCI_TD_DIRECTION_PID_MASK);
105 printf("pid_setup\n");
107 dest->flags |= LE(OHCI_TD_DIRECTION_PID_SETUP);
108 dest->flags |= LE(OHCI_TD_TOGGLE_0);
109 dest->flags |= LE(OHCI_TD_BUFFER_ROUNDING);
115 dest->flags |= LE(OHCI_TD_DIRECTION_PID_OUT);
116 dest->flags |= LE(OHCI_TD_BUFFER_ROUNDING);
119 * TODO: just temporary solution! (consider it with len?)
120 * there can be also regular PID_OUT pakets
122 dest->flags |= LE(OHCI_TD_TOGGLE_1);
128 dest->flags |= LE(OHCI_TD_DIRECTION_PID_IN);
129 if(src->maxp > src->actlen) {
130 dest->flags |= LE(OHCI_TD_BUFFER_ROUNDING);
132 printf("round buffer!\n");
136 * let the endpoint do the togglestuff!
137 * TODO: just temporary solution!
138 * there can be also inregular PID_IN pakets (@Status Stage)
140 dest->flags |= LE(OHCI_TD_TOGGLE_CARRY);
143 dest->flags |= LE(OHCI_TD_SET_DELAY_INTERRUPT(7));
146 #ifdef _DU_OHCI_F_HALT
147 static void dump_address(void *addr, u32 size, const char* str)
149 printf("%s hexdump (%d) @ 0x%08X:\n", str, size, addr);
154 static struct endpoint_descriptor _edhead;
155 struct endpoint_descriptor *edhead = 0;
159 printf("<^> <^> <^> hcdi_fire(start)\n");
166 /* quirk... 11ms seems to be a minimum :O */
170 write32(OHCI0_HC_CTRL_HEAD_ED, virt_to_phys(edhead));
173 sync_after_write(edhead, sizeof(struct endpoint_descriptor));
175 dump_address(edhead, sizeof(struct endpoint_descriptor), "edhead(before)");
178 struct general_td *x = phys_to_virt(LE(edhead->headp) & OHCI_ENDPOINT_HEAD_MASK);
179 while(virt_to_phys(x)) {
180 sync_after_write(x, sizeof(struct general_td));
182 dump_address(x, sizeof(struct general_td), "x(before)");
186 sync_after_write((void*) phys_to_virt(LE(x->cbp)), x->buflen);
188 dump_address((void*) phys_to_virt(LE(x->cbp)), x->buflen, "x->cbp(before)");
191 x = phys_to_virt(LE(x->nexttd));
194 /* trigger control list */
195 set32(OHCI0_HC_CONTROL, OHCI_CTRL_CLE);
196 write32(OHCI0_HC_COMMAND_STATUS, OHCI_CLF);
198 struct general_td *n=0, *prev = 0, *next = 0;
199 /* poll until edhead->headp is null */
201 sync_before_read(edhead, sizeof(struct endpoint_descriptor));
203 printf("edhead->headp: 0x%08X\n", LE(edhead->headp));
207 /* if halted, debug output plz. will break the transfer */
208 if((LE(edhead->headp) & OHCI_ENDPOINT_HALTED)) {
209 n = phys_to_virt(LE(edhead->headp)&~0xf);
210 prev = phys_to_virt((u32)prev);
211 #ifdef _DU_OHCI_F_HALT
215 sync_before_read((void*) n, sizeof(struct general_td));
216 #ifdef _DU_OHCI_F_HALT
217 printf("n: 0x%08X\n", n);
218 dump_address(n, sizeof(struct general_td), "n(after)");
221 sync_before_read((void*) n->bufaddr, n->buflen);
222 #ifdef _DU_OHCI_F_HALT
223 dump_address((void*) n->bufaddr, n->buflen, "n->bufaddr(after)");
226 #ifdef _DU_OHCI_F_HALT
227 dbg_td_flag(LE(n->flags));
230 sync_before_read((void*) prev, sizeof(struct general_td));
231 #ifdef _DU_OHCI_F_HALT
232 printf("prev: 0x%08X\n", prev);
233 dump_address(prev, sizeof(struct general_td), "prev(after)");
235 if(prev->buflen >0) {
236 sync_before_read((void*) prev->bufaddr, prev->buflen);
237 #ifdef _DU_OHCI_F_HALT
238 dump_address((void*) prev->bufaddr, prev->buflen, "prev->bufaddr(after)");
241 #ifdef _DU_OHCI_F_HALT
242 dbg_td_flag(LE(prev->flags));
243 printf("halted end!\n");
247 prev = (struct general_td*) (LE(edhead->headp)&~0xf);
248 } while(LE(edhead->headp)&~0xf);
250 n = phys_to_virt(read32(OHCI0_HC_DONE_HEAD) & ~1);
252 printf("hc_done_head: 0x%08X\n", read32(OHCI0_HC_DONE_HEAD));
256 /* reverse done queue */
257 while(virt_to_phys(n) && edhead->tdcount) {
258 sync_before_read((void*) n, sizeof(struct general_td));
260 printf("n: 0x%08X\n", n);
261 printf("next: 0x%08X\n", next);
262 printf("prev: 0x%08X\n", prev);
266 n = (struct general_td*) phys_to_virt(LE(n->nexttd));
267 next->nexttd = (u32) prev;
275 while(virt_to_phys(n)) {
277 dump_address(n, sizeof(struct general_td), "n(after)");
280 sync_before_read((void*) n->bufaddr, n->buflen);
282 dump_address((void*) n->bufaddr, n->buflen, "n->bufaddr(after)");
286 dbg_td_flag(LE(n->flags));
289 n = (struct general_td*) n->nexttd;
293 hcca_oh0.done_head = 0;
294 sync_after_write(&hcca_oh0, sizeof(hcca_oh0));
296 write32(OHCI0_HC_CONTROL, read32(OHCI0_HC_CONTROL)&~OHCI_CTRL_CLE);
301 printf("<^> <^> <^> hcdi_fire(end)\n");
306 * Enqueue a transfer descriptor.
308 u8 hcdi_enqueue(const struct usb_transfer_descriptor *td) {
310 printf("*()*()*()*()*()*()*() hcdi_enqueue(start)\n");
314 memset(edhead, 0, sizeof(struct endpoint_descriptor));
315 edhead->flags = LE(OHCI_ENDPOINT_GENERAL_FORMAT);
316 edhead->headp = edhead->tailp = edhead->nexted = LE(0);
318 edhead->flags |= LE(OHCI_ENDPOINT_FULL_SPEED);
320 edhead->flags |= LE(OHCI_ENDPOINT_LOW_SPEED);
322 edhead->flags |= LE(OHCI_ENDPOINT_SET_DEVICE_ADDRESS(td->devaddress) |
323 OHCI_ENDPOINT_SET_ENDPOINT_NUMBER(td->endpoint) |
324 OHCI_ENDPOINT_SET_MAX_PACKET_SIZE(td->maxp));
328 struct general_td *tdhw = allocate_general_td();
329 general_td_fill(tdhw, td);
334 edhead->headp = LE(virt_to_phys((void*) ((u32)tdhw & OHCI_ENDPOINT_HEAD_MASK)));
337 /* headp in endpoint already exists
340 struct general_td *n = (struct general_td*) phys_to_virt(LE(edhead->headp) & OHCI_ENDPOINT_HEAD_MASK);
341 while(LE(n->nexttd)) {
342 n = phys_to_virt(LE(n->nexttd));
344 n->nexttd = LE(virt_to_phys((void*) ((u32)tdhw & OHCI_ENDPOINT_HEAD_MASK)));
346 printf("n: 0x%08X\n", n);
347 printf("n->nexttd: 0x%08X\n", phys_to_virt(LE(n->nexttd)));
352 printf("*()*()*()*()*()*()*() hcdi_enqueue(end)\n");
359 * Remove an transfer descriptor from transfer queue.
361 u8 hcdi_dequeue(struct usb_transfer_descriptor *td) {
367 printf("ohci-- init\n");
370 /* disable hc interrupts */
371 set32(OHCI0_HC_INT_DISABLE, OHCI_INTR_MIE);
373 /* save fmInterval and calculate FSMPS */
374 #define FSMP(fi) (0x7fff & ((6 * ((fi) - 210)) / 7))
375 #define FI 0x2edf /* 12000 bits per frame (-1) */
376 u32 fmint = read32(OHCI0_HC_FM_INTERVAL) & 0x3fff;
378 printf("ohci-- fminterval delta: %d\n", fmint - FI);
379 fmint |= FSMP (fmint) << 16;
381 /* enable interrupts of both usb host controllers */
382 set32(EHCI_CTL, EHCI_CTL_OH0INTE | EHCI_CTL_OH1INTE | 0xe0000);
385 write32(OHCI0_HC_COMMAND_STATUS, OHCI_HCR);
389 while ((read32(OHCI0_HC_COMMAND_STATUS) & OHCI_HCR) != 0) {
391 printf("ohci-- FAILED");
397 /* disable interrupts; 2ms timelimit here!
398 now we're in the SUSPEND state ... must go OPERATIONAL
399 within 2msec else HC enters RESUME */
401 u32 cookie = irq_kill();
403 /* Tell the controller where the control and bulk lists are
404 * The lists are empty now. */
405 write32(OHCI0_HC_CTRL_HEAD_ED, 0);
406 write32(OHCI0_HC_BULK_HEAD_ED, 0);
408 /* set hcca adress */
409 sync_after_write(&hcca_oh0, 256);
410 write32(OHCI0_HC_HCCA, virt_to_phys(&hcca_oh0));
412 /* set periodicstart */
414 u32 fmInterval = read32(OHCI0_HC_FM_INTERVAL) &0x3fff;
415 u32 fit = read32(OHCI0_HC_FM_INTERVAL) & FIT;
417 write32(OHCI0_HC_FM_INTERVAL, fmint | (fit ^ FIT));
418 write32(OHCI0_HC_PERIODIC_START, ((9*fmInterval)/10)&0x3fff);
421 if ((read32(OHCI0_HC_FM_INTERVAL) & 0x3fff0000) == 0 || !read32(OHCI0_HC_PERIODIC_START)) {
422 printf("ohci-- w00t, fail!! see ohci-hcd.c:669\n");
425 /* start HC operations */
426 write32(OHCI0_HC_CONTROL, OHCI_CONTROL_INIT | OHCI_USB_OPER);
428 /* wake on ConnectStatusChange, matching external hubs */
429 write32(OHCI0_HC_RH_STATUS, /*RH_HS_DRWE |*/ RH_HS_LPSC);
431 /* Choose the interrupts we care about now, others later on demand */
432 write32(OHCI0_HC_INT_STATUS, ~0);
433 write32(OHCI0_HC_INT_ENABLE, OHCI_INTR_INIT);
436 wait_ms ((read32(OHCI0_HC_RH_DESCRIPTOR_A) >> 23) & 0x1fe);
438 configure_ports((u8)1);
444 static void configure_ports(u8 from_init)
447 printf("OHCI0_HC_RH_DESCRIPTOR_A:\t0x%08X\n", read32(OHCI0_HC_RH_DESCRIPTOR_A));
448 printf("OHCI0_HC_RH_DESCRIPTOR_B:\t0x%08X\n", read32(OHCI0_HC_RH_DESCRIPTOR_B));
449 printf("OHCI0_HC_RH_STATUS:\t\t0x%08X\n", read32(OHCI0_HC_RH_STATUS));
450 printf("OHCI0_HC_RH_PORT_STATUS_1:\t0x%08X\n", read32(OHCI0_HC_RH_PORT_STATUS_1));
451 printf("OHCI0_HC_RH_PORT_STATUS_2:\t0x%08X\n", read32(OHCI0_HC_RH_PORT_STATUS_2));
454 setup_port(OHCI0_HC_RH_PORT_STATUS_1, from_init);
455 setup_port(OHCI0_HC_RH_PORT_STATUS_2, from_init);
457 printf("configure_ports done\n");
461 static void setup_port(u32 reg, u8 from_init)
463 u32 port = read32(reg);
464 if((port & RH_PS_CCS) && ((port & RH_PS_CSC) || from_init)) {
465 write32(reg, RH_PS_CSC);
469 /* clear CSC flag, set PES and start port reset (PRS) */
470 write32(reg, RH_PS_PES);
471 while(!(read32(reg) & RH_PS_PES)) {
478 write32(reg, RH_PS_PRS);
480 /* spin until port reset is complete */
481 while(!(read32(reg) & RH_PS_PRSC)); // hint: it may stuck here
483 printf("loop done\n");
486 /* returns usb_device struct */
487 (void) usb_add_device((read32(reg) & RH_PS_LSDA) >> 8);
493 /* read interrupt status */
494 u32 flags = read32(OHCI0_HC_INT_STATUS);
496 /* when all bits are set to 1 some problem occured */
497 if (flags == 0xffffffff) {
498 printf("ohci-- Houston, we have a serious problem! :(\n");
502 /* only care about interrupts that are enabled */
503 flags &= read32(OHCI0_HC_INT_ENABLE);
507 printf("OHCI Interrupt occured: but not for you! WTF?!\n");
511 printf("OHCI Interrupt occured: ");
512 /* UnrecoverableError */
513 if (flags & OHCI_INTR_UE) {
514 printf("UnrecoverableError\n");
515 /* TODO: well, I don't know... nothing,
516 * because it won't happen anyway? ;-) */
519 /* RootHubStatusChange */
520 if (flags & OHCI_INTR_RHSC) {
521 printf("RootHubStatusChange\n");
522 /* TODO: set some next_statechange variable... */
524 write32(OHCI0_HC_INT_STATUS, OHCI_INTR_RD | OHCI_INTR_RHSC);
527 else if (flags & OHCI_INTR_RD) {
528 printf("ResumeDetected\n");
529 write32(OHCI0_HC_INT_STATUS, OHCI_INTR_RD);
530 /* TODO: figure out what the linux kernel does here... */
533 /* WritebackDoneHead */
534 if (flags & OHCI_INTR_WDH) {
535 printf("WritebackDoneHead\n");
536 /* basically the linux irq handler reverse TDs to their urbs
537 * and set done_head to null.
538 * since we are polling atm, just should do the latter task.
539 * however, this won't work for now (i don't know why...)
543 sync_before_read(&hcca_oh0, 256);
544 hcca_oh0.done_head = 0;
545 sync_after_write(&hcca_oh0, 256);
549 /* TODO: handle any pending URB/ED unlinks... */
551 #define HC_IS_RUNNING() 1 /* dirty, i know... just a temporary solution */
552 if (HC_IS_RUNNING()) {
553 write32(OHCI0_HC_INT_STATUS, flags);
554 write32(OHCI0_HC_INT_ENABLE, OHCI_INTR_MIE);
560 sync_before_read(&hcca_oh0, 256);
561 printf("***** frame_no: %d *****\n", LE(hcca_oh0.frame_no));