2 ppcskel - a Free Software replacement for the Nintendo/BroadOn bootloader.
5 Copyright (C) 2009 Bernhard Urban <lewurm@gmx.net>
6 Copyright (C) 2009 Sebastian Falbesoner <sebastian.falbesoner@gmail.com>
8 # This code is licensed to you under the terms of the GNU GPL, version 2;
9 # see file COPYING or http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt
12 #include "../../bootmii_ppc.h"
13 #include "../../hollywood.h"
14 #include "../../irq.h"
15 #include "../../string.h"
16 #include "../../malloc.h"
19 #include "../usbspec/usb11spec.h"
21 // macro for accessing u32 variables that need to be in little endian byte order;
22 // whenever you read or write from an u32 field that the ohci host controller
23 // will read or write from too, use this macro for access!
24 #define ACCESS_LE(dword) (u32)( (((dword) & 0xFF000000) >> 24) | \
25 (((dword) & 0x00FF0000) >> 8) | \
26 (((dword) & 0x0000FF00) << 8) | \
27 (((dword) & 0x000000FF) << 24) )
29 static struct ohci_hcca hcca_oh0;
31 static struct endpoint_descriptor *allocate_endpoint()
33 struct endpoint_descriptor *ep;
34 ep = (struct endpoint_descriptor *)calloc(sizeof(struct endpoint_descriptor), 16);
35 ep->flags = ACCESS_LE(OHCI_ENDPOINT_GENERAL_FORMAT);
36 ep->headp = ep->tailp = ep->nexted = ACCESS_LE(0);
40 static struct general_td *allocate_general_td(size_t bsize)
42 struct general_td *td;
43 td = (struct general_td *)calloc(sizeof(struct general_td), 16);
44 td->flags = ACCESS_LE(0);
45 td->nexttd = ACCESS_LE(virt_to_phys(td));
47 td->cbp = td->be = ACCESS_LE(0);
49 td->cbp = ACCESS_LE(virt_to_phys(malloc(bsize)));
50 td->be = ACCESS_LE(ACCESS_LE(td->cbp) + bsize - 1);
55 static void control_quirk()
57 static struct endpoint_descriptor *ed; /* empty ED */
58 static struct general_td *td; /* dummy TD */
65 * Allocate and keep a special empty ED with just a dummy TD.
68 ed = allocate_endpoint();
72 td = allocate_general_td(0);
79 #define ED_MASK ((u32)~0x0f)
80 ed->tailp = ed->headp = ACCESS_LE(virt_to_phys((void*) ((u32)td & ED_MASK)));
81 ed->flags |= ACCESS_LE(OHCI_ENDPOINT_DIRECTION_OUT);
85 * The OHCI USB host controllers on the Nintendo Wii
86 * video game console stop working when new TDs are
87 * added to a scheduled control ED after a transfer has
88 * has taken place on it.
90 * Before scheduling any new control TD, we make the
91 * controller happy by always loading a special control ED
92 * with a single dummy TD and letting the controller attempt
94 * The controller won't do anything with it, as the special
95 * ED has no TDs, but it will keep the controller from failing
96 * on the next transfer.
98 head = read32(OHCI0_HC_CTRL_HEAD_ED);
100 printf("head: 0x%08X\n", head);
102 * Load the special empty ED and tell the controller to
103 * process the control list.
105 sync_after_write(ed, 64);
106 sync_after_write(td, 64);
107 write32(OHCI0_HC_CTRL_HEAD_ED, virt_to_phys(ed));
109 status = read32(OHCI0_HC_CONTROL);
110 set32(OHCI0_HC_CONTROL, OHCI_CTRL_CLE);
111 write32(OHCI0_HC_COMMAND_STATUS, OHCI_CLF);
113 /* spin until the controller is done with the control list */
114 current = read32(OHCI0_HC_CTRL_CURRENT_ED);
117 current = read32(OHCI0_HC_CTRL_CURRENT_ED);
120 printf("current: 0x%08X\n", current);
122 /* restore the old control head and control settings */
123 write32(OHCI0_HC_CONTROL, status);
124 write32(OHCI0_HC_CTRL_HEAD_ED, head);
131 static void dbg_op_state()
133 switch (read32(OHCI0_HC_CONTROL) & OHCI_CTRL_HCFS) {
134 case OHCI_USB_SUSPEND:
135 printf("ohci-- OHCI_USB_SUSPEND\n");
138 printf("ohci-- OHCI_USB_RESET\n");
141 printf("ohci-- OHCI_USB_OPER\n");
143 case OHCI_USB_RESUME:
144 printf("ohci-- OHCI_USB_RESUME\n");
151 * Enqueue a transfer descriptor.
154 u8 hcdi_enqueue(usb_transfer_descriptor *td) {
157 printf( "===========================\n"
158 "===========================\n");
159 sync_before_read(&hcca_oh0, 256);
160 printf("done head (nach sync): 0x%08X\n", ACCESS_LE(hcca_oh0.done_head));
161 printf("HCCA->frame_no: %d\nhcca->hccapad1: %d\n", ((ACCESS_LE(hcca_oh0.frame_no) & 0xffff0000)>>16), ACCESS_LE(hcca_oh0.frame_no)&0xffff );
162 if(hcca_oh0.done_head) printf("WWWWWWWWOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOTTTTTTTTTTTT\n");
164 struct general_td *tmptd = allocate_general_td(td->actlen);
165 (void) memcpy((void*) (phys_to_virt(ACCESS_LE(tmptd->cbp))), td->buffer, td->actlen);
167 tmptd->flags &= ACCESS_LE(~OHCI_TD_DIRECTION_PID_MASK);
170 printf("pid_setup\n");
171 tmptd->flags |= ACCESS_LE(OHCI_TD_DIRECTION_PID_SETUP);
175 tmptd->flags |= ACCESS_LE(OHCI_TD_DIRECTION_PID_OUT);
179 tmptd->flags |= ACCESS_LE(OHCI_TD_DIRECTION_PID_IN);
182 tmptd->flags |= ACCESS_LE((td->togl) ? OHCI_TD_TOGGLE_1 : OHCI_TD_TOGGLE_0);
184 printf("tmptd hexump (before):\n");
185 hexdump(tmptd, sizeof(struct general_td));
186 printf("tmptd-cbp hexump (before):\n");
187 hexdump((void*) phys_to_virt(ACCESS_LE(tmptd->cbp)), td->actlen);
189 sync_after_write((void*) phys_to_virt(ACCESS_LE(tmptd->cbp)), td->actlen);
190 sync_after_write(tmptd, sizeof(struct general_td));
192 struct endpoint_descriptor *dummyconfig = allocate_endpoint();
194 #define ED_MASK2 ~0 /*((u32)~0x0f) */
195 #define ED_MASK ((u32)~0x0f)
196 printf("tmpdt & ED_MASK: 0x%08X\n", virt_to_phys((void*) ((u32)tmptd & ED_MASK)));
197 dummyconfig->tailp = dummyconfig->headp = ACCESS_LE(virt_to_phys((void*) ((u32)tmptd & ED_MASK)));
199 dummyconfig->flags |= ACCESS_LE(OHCI_ENDPOINT_LOW_SPEED |
200 OHCI_ENDPOINT_SET_DEVICE_ADDRESS(td->devaddress) |
201 OHCI_ENDPOINT_SET_ENDPOINT_NUMBER(td->endpoint) |
202 OHCI_ENDPOINT_SET_MAX_PACKET_SIZE(td->maxp));
204 sync_after_write(dummyconfig, 64);
205 write32(OHCI0_HC_CTRL_HEAD_ED, virt_to_phys(dummyconfig));
207 printf("OHCI_CTRL_CLE: 0x%08X\n", read32(OHCI0_HC_CONTROL)&OHCI_CTRL_CLE);
208 printf("OHCI_CLF: 0x%08X\n", read32(OHCI0_HC_COMMAND_STATUS)&OHCI_CLF);
209 set32(OHCI0_HC_CONTROL, OHCI_CTRL_CLE);
210 write32(OHCI0_HC_COMMAND_STATUS, OHCI_CLF);
212 printf("+++++++++++++++++++++++++++++\n");
213 /* spin until the controller is done with the control list */
214 u32 current = read32(OHCI0_HC_CTRL_CURRENT_ED);
215 printf("current: 0x%08X\n", current);
218 current = read32(OHCI0_HC_CTRL_CURRENT_ED);
222 current = read32(OHCI0_HC_CTRL_CURRENT_ED);
223 printf("current: 0x%08X\n", current);
224 printf("+++++++++++++++++++++++++++++\n");
227 sync_before_read(tmptd, sizeof(struct general_td));
228 printf("tmptd hexump (after):\n");
229 hexdump(tmptd, sizeof(struct general_td));
231 sync_before_read((void*) phys_to_virt(ACCESS_LE(tmptd->cbp)), td->actlen);
232 printf("tmptd-cbp hexump (after):\n");
233 hexdump((void*) phys_to_virt(ACCESS_LE(tmptd->cbp)), td->actlen);
235 sync_before_read(&hcca_oh0, 256);
236 printf("done head (nach sync): 0x%08X\n", ACCESS_LE(hcca_oh0.done_head));
243 * Remove an transfer descriptor from transfer queue.
245 u8 hcdi_dequeue(usb_transfer_descriptor *td) {
251 printf("ohci-- init\n");
254 /* disable hc interrupts */
255 set32(OHCI0_HC_INT_DISABLE, OHCI_INTR_MIE);
257 /* save fmInterval and calculate FSMPS */
258 #define FSMP(fi) (0x7fff & ((6 * ((fi) - 210)) / 7))
259 #define FI 0x2edf /* 12000 bits per frame (-1) */
260 u32 fmint = read32(OHCI0_HC_FM_INTERVAL) & 0x3fff;
262 printf("ohci-- fminterval delta: %d\n", fmint - FI);
263 fmint |= FSMP (fmint) << 16;
265 /* enable interrupts of both usb host controllers */
266 set32(EHCI_CTL, EHCI_CTL_OH0INTE | EHCI_CTL_OH1INTE | 0xe0000);
269 write32(OHCI0_HC_COMMAND_STATUS, OHCI_HCR);
273 while ((read32(OHCI0_HC_COMMAND_STATUS) & OHCI_HCR) != 0) {
275 printf("ohci-- FAILED");
281 /* disable interrupts; 2ms timelimit here!
282 now we're in the SUSPEND state ... must go OPERATIONAL
283 within 2msec else HC enters RESUME */
285 u32 cookie = irq_kill();
287 /* Tell the controller where the control and bulk lists are
288 * The lists are empty now. */
289 write32(OHCI0_HC_CTRL_HEAD_ED, 0);
290 write32(OHCI0_HC_BULK_HEAD_ED, 0);
292 /* set hcca adress */
293 sync_after_write(&hcca_oh0, 256);
294 write32(OHCI0_HC_HCCA, virt_to_phys(&hcca_oh0));
296 /* set periodicstart */
298 u32 fmInterval = read32(OHCI0_HC_FM_INTERVAL) &0x3fff;
299 u32 fit = read32(OHCI0_HC_FM_INTERVAL) & FIT;
301 write32(OHCI0_HC_FM_INTERVAL, fmint | (fit ^ FIT));
302 write32(OHCI0_HC_PERIODIC_START, ((9*fmInterval)/10)&0x3fff);
305 if ((read32(OHCI0_HC_FM_INTERVAL) & 0x3fff0000) == 0 || !read32(OHCI0_HC_PERIODIC_START)) {
306 printf("ohci-- w00t, fail!! see ohci-hcd.c:669\n");
309 /* start HC operations */
310 write32(OHCI0_HC_CONTROL, OHCI_CONTROL_INIT | OHCI_USB_OPER);
312 /* wake on ConnectStatusChange, matching external hubs */
313 set32(OHCI0_HC_RH_STATUS, RH_HS_DRWE);
315 /* Choose the interrupts we care about now, others later on demand */
316 write32(OHCI0_HC_INT_STATUS, ~0);
317 write32(OHCI0_HC_INT_ENABLE, OHCI_INTR_INIT);
326 /* read interrupt status */
327 u32 flags = read32(OHCI0_HC_INT_STATUS);
329 /* when all bits are set to 1 some problem occured */
330 if (flags == 0xffffffff) {
331 printf("ohci-- Houston, we have a serious problem! :(\n");
335 /* only care about interrupts that are enabled */
336 flags &= read32(OHCI0_HC_INT_ENABLE);
340 printf("OHCI Interrupt occured: but not for you! WTF?!\n");
344 printf("OHCI Interrupt occured: ");
345 /* UnrecoverableError */
346 if (flags & OHCI_INTR_UE) {
347 printf("UnrecoverableError\n");
348 /* TODO: well, I don't know... nothing,
349 * because it won't happen anyway? ;-) */
352 /* RootHubStatusChange */
353 if (flags & OHCI_INTR_RHSC) {
354 printf("RootHubStatusChange\n");
355 /* TODO: set some next_statechange variable... */
356 write32(OHCI0_HC_INT_STATUS, OHCI_INTR_RD | OHCI_INTR_RHSC);
359 else if (flags & OHCI_INTR_RD) {
360 printf("ResumeDetected\n");
361 write32(OHCI0_HC_INT_STATUS, OHCI_INTR_RD);
362 /* TODO: figure out what the linux kernel does here... */
365 /* WritebackDoneHead */
366 if (flags & OHCI_INTR_WDH) {
367 printf("WritebackDoneHead\n");
368 /* TODO: figure out what the linux kernel does here... */
371 /* TODO: handle any pending URB/ED unlinks... */
373 #define HC_IS_RUNNING() 1 /* dirty, i know... just a temporary solution */
374 if (HC_IS_RUNNING()) {
375 write32(OHCI0_HC_INT_STATUS, flags);
376 write32(OHCI0_HC_INT_ENABLE, OHCI_INTR_MIE);