usb/host/ohci.c

   1 /*
   2        ppcskel - a Free Software replacement for the Nintendo/BroadOn bootloader.
   3        ohci hardware support
   4
   5 Copyright (C) 2009     Bernhard Urban <lewurm@gmx.net>
   6 Copyright (C) 2009     Sebastian Falbesoner <sebastian.falbesoner@gmail.com>
   7
   8 # This code is licensed to you under the terms of the GNU GPL, version 2;
   9 # see file COPYING or http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt
  10 */
  11
  12 #include "../../bootmii_ppc.h"
  13 #include "../../hollywood.h"
  14 #include "../../irq.h"
  15 #include "../../string.h"
  16 #include "../../malloc.h"
  17 #include "ohci.h"
  18 #include "host.h"
  19 #include "../usbspec/usb11spec.h"
  20
  21 /* macro for accessing u32 variables that need to be in little endian byte order;
  22  *
  23  * whenever you read or write from an u32 field that the ohci host controller
  24  * will read or write from too, use this macro for access!
  25  */
  26 #define LE(dword) (u32)( (((dword) & 0xFF000000) >> 24) | \
  27                            (((dword) & 0x00FF0000) >> 8)  | \
  28                            (((dword) & 0x0000FF00) << 8)  | \
  29                            (((dword) & 0x000000FF) << 24) )
  30
  31 static struct endpoint_descriptor *allocate_endpoint();
  32 static struct general_td *allocate_general_td();
  33 static void control_quirk();
  34 static void dbg_op_state();
  35 static void configure_ports(u8 from_init);
  36 static void setup_port(u32 reg, u8 from_init);
  37
  38 static struct ohci_hcca hcca_oh0;
  39
  40
  41 static struct endpoint_descriptor *allocate_endpoint()
  42 {
  43         struct endpoint_descriptor *ep;
  44         ep = (struct endpoint_descriptor *)memalign(16, sizeof(struct endpoint_descriptor));
  45         memset(ep, 0, sizeof(struct endpoint_descriptor));
  46         ep->flags = LE(OHCI_ENDPOINT_GENERAL_FORMAT);
  47         ep->headp = ep->tailp = ep->nexted = LE(0);
  48         return ep;
  49 }
  50
  51 static struct general_td *allocate_general_td()
  52 {
  53         struct general_td *td;
  54         td = (struct general_td *)memalign(16, sizeof(struct general_td));
  55         memset(td, 0, sizeof(struct general_td));
  56         td->flags = LE(0);
  57         td->nexttd = LE(0);
  58         td->cbp = td->be = LE(0);
  59         return td;
  60 }
  61
  62 static void control_quirk()
  63 {
  64         static struct endpoint_descriptor *ed = 0; /* empty ED */
  65         static struct general_td *td = 0; /* dummy TD */
  66         u32 head;
  67         u32 current;
  68         u32 status;
  69
  70         /*
  71          * One time only.
  72          * Allocate and keep a special empty ED with just a dummy TD.
  73          */
  74         if (!ed) {
  75                 ed = allocate_endpoint();
  76                 if (!ed)
  77                         return;
  78
  79                 td = allocate_general_td(0);
  80                 if (!td) {
  81                         free(ed);
  82                         ed = NULL;
  83                         return;
  84                 }
  85
  86                 ed->tailp = ed->headp = LE(virt_to_phys((void*) ((u32)td & OHCI_ENDPOINT_HEAD_MASK)));
  87                 ed->flags |= LE(OHCI_ENDPOINT_DIRECTION_OUT);
  88         }
  89
  90         /*
  91          * The OHCI USB host controllers on the Nintendo Wii
  92          * video game console stop working when new TDs are
  93          * added to a scheduled control ED after a transfer has
  94          * has taken place on it.
  95          *
  96          * Before scheduling any new control TD, we make the
  97          * controller happy by always loading a special control ED
  98          * with a single dummy TD and letting the controller attempt
  99          * the transfer.
 100          * The controller won't do anything with it, as the special
 101          * ED has no TDs, but it will keep the controller from failing
 102          * on the next transfer.
 103          */
 104         head = read32(OHCI0_HC_CTRL_HEAD_ED);
 105         if (head) {
 106                 printf("head: 0x%08X\n", head);
 107                 /*
 108                  * Load the special empty ED and tell the controller to
 109                  * process the control list.
 110                  */
 111                 sync_after_write(ed, 16);
 112                 sync_after_write(td, 16);
 113                 write32(OHCI0_HC_CTRL_HEAD_ED, virt_to_phys(ed));
 114
 115                 status = read32(OHCI0_HC_CONTROL);
 116                 set32(OHCI0_HC_CONTROL, OHCI_CTRL_CLE);
 117                 write32(OHCI0_HC_COMMAND_STATUS, OHCI_CLF);
 118
 119                 /* spin until the controller is done with the control list */
 120                 current = read32(OHCI0_HC_CTRL_CURRENT_ED);
 121                 while(!current) {
 122                         udelay(10);
 123                         current = read32(OHCI0_HC_CTRL_CURRENT_ED);
 124                 }
 125
 126                 printf("current: 0x%08X\n", current);
 127
 128                 /* restore the old control head and control settings */
 129                 write32(OHCI0_HC_CONTROL, status);
 130                 write32(OHCI0_HC_CTRL_HEAD_ED, head);
 131         } else {
 132                 printf("nohead!\n");
 133         }
 134 }
 135
 136
 137 static void dbg_op_state()
 138 {
 139         switch (read32(OHCI0_HC_CONTROL) & OHCI_CTRL_HCFS) {
 140                 case OHCI_USB_SUSPEND:
 141                         printf("ohci-- OHCI_USB_SUSPEND\n");
 142                         break;
 143                 case OHCI_USB_RESET:
 144                         printf("ohci-- OHCI_USB_RESET\n");
 145                         break;
 146                 case OHCI_USB_OPER:
 147                         printf("ohci-- OHCI_USB_OPER\n");
 148                         break;
 149                 case OHCI_USB_RESUME:
 150                         printf("ohci-- OHCI_USB_RESUME\n");
 151                         break;
 152         }
 153 }
 154
 155 static void dbg_td_flag(u32 flag)
 156 {
 157         printf("**************** dbg_td_flag: 0x%08X ***************\n", flag);
 158         printf("CC: %X\tshould be 0, see page 32 (ohci spec)\n", (flag>>28)&0xf);
 159         printf("EC: %X\tsee page 20 (ohci spec)\n", (flag>>26)&3);
 160         printf(" T: %X\n", (flag>>24)&3);
 161         printf("DI: %X\n", (flag>>21)&7);
 162         printf("DP: %X\n", (flag>>19)&3);
 163         printf(" R: %X\n", (flag>>18)&1);
 164         printf("********************************************************\n");
 165 }
 166
 167 static void general_td_fill(struct general_td *dest, const usb_transfer_descriptor *src)
 168 {
 169         if(src->actlen) {
 170                 dest->cbp = LE(virt_to_phys(src->buffer));
 171                 dest->be = LE(LE(dest->cbp) + src->actlen - 1);
 172                 /* save virtual address here */
 173                 dest->bufaddr = (u32) src->buffer;
 174         }
 175         else {
 176                 dest->cbp = dest->be = LE(0);
 177                 dest->bufaddr = 0;
 178         }
 179
 180         dest->buflen = src->actlen;
 181
 182         dest->flags &= LE(~OHCI_TD_DIRECTION_PID_MASK);
 183         switch(src->pid) {
 184                 case USB_PID_SETUP:
 185                         printf("pid_setup\n");
 186                         dest->flags |= LE(OHCI_TD_DIRECTION_PID_SETUP);
 187                         dest->flags |= LE(OHCI_TD_TOGGLE_0);
 188                         dest->flags |= LE(OHCI_TD_BUFFER_ROUNDING);
 189                         break;
 190                 case USB_PID_OUT:
 191                         printf("pid_out\n");
 192                         dest->flags |= LE(OHCI_TD_DIRECTION_PID_OUT);
 193                         dest->flags |= LE(OHCI_TD_BUFFER_ROUNDING);
 194
 195                         /*
 196                          * TODO: just temporary solution! (consider it with len?)
 197                          * there can be also regular PID_OUT pakets
 198                          */
 199                         dest->flags |= LE(OHCI_TD_TOGGLE_1);
 200                         break;
 201                 case USB_PID_IN:
 202                         printf("pid_in\n");
 203                         dest->flags |= LE(OHCI_TD_DIRECTION_PID_IN);
 204                         if(src->maxp > src->actlen) {
 205                                 dest->flags |= LE(OHCI_TD_BUFFER_ROUNDING);
 206                                 printf("round buffer!");
 207                         }
 208                         /*
 209                          * let the endpoint do the togglestuff!
 210                          * TODO: just temporary solution!
 211                          * there can be also inregular PID_IN pakets (@Status Stage)
 212                          */
 213                         dest->flags |= LE(OHCI_TD_TOGGLE_CARRY);
 214 #if 0
 215                         /* should be done by HC!
 216                          * first pid_in start with DATA0 */
 217                          */
 218                         dummyconfig.headp = LE( src->togl ?
 219                                         LE(dummyconfig.headp) | OHCI_ENDPOINT_TOGGLE_CARRY :
 220                                         LE(dummyconfig.headp) & ~OHCI_ENDPOINT_TOGGLE_CARRY);
 221 #endif
 222                         break;
 223         }
 224         dest->flags |= LE(OHCI_TD_SET_DELAY_INTERRUPT(7));
 225 }
 226
 227 #ifdef _DU_OHCI_F
 228 static void dump_address(void *addr, u32 size, const char* str)
 229 {
 230         printf("%s hexdump (%d) @ 0x%08X:\n", str, size, addr);
 231         hexdump(addr, size);
 232 }
 233 #endif
 234
 235 static struct endpoint_descriptor _edhead;
 236 struct endpoint_descriptor *edhead = 0;
 237 void hcdi_fire()
 238 {
 239 #ifdef _DU_OHCI_F
 240         printf("<^>  <^>  <^> hcdi_fire(start)\n");
 241 #endif
 242
 243         if(edhead == 0)
 244                 return;
 245
 246         control_quirk(); //required? YES! :O ... erm... or no? :/ ... in fact I have no idea
 247         write32(OHCI0_HC_CTRL_HEAD_ED, virt_to_phys(edhead));
 248
 249         /* sync it all */
 250         sync_after_write(edhead, sizeof(struct endpoint_descriptor));
 251 #ifdef _DU_OHCI_F
 252         dump_address(edhead, sizeof(struct endpoint_descriptor), "edhead(before)");
 253 #endif
 254
 255         struct general_td *x = phys_to_virt(LE(edhead->headp) & OHCI_ENDPOINT_HEAD_MASK);
 256         while(virt_to_phys(x)) {
 257                 sync_after_write(x, sizeof(struct general_td));
 258 #ifdef _DU_OHCI_F
 259                 dump_address(x, sizeof(struct general_td), "x(before)");
 260 #endif
 261
 262                 if(x->buflen > 0) {
 263                         sync_after_write((void*) phys_to_virt(LE(x->cbp)), x->buflen);
 264 #ifdef _DU_OHCI_F
 265                         dump_address((void*) phys_to_virt(LE(x->cbp)), x->buflen, "x->cbp(before)");
 266 #endif
 267                 }
 268                 x = phys_to_virt(LE(x->nexttd));
 269         }
 270
 271         /* trigger control list */
 272         set32(OHCI0_HC_CONTROL, OHCI_CTRL_CLE);
 273         write32(OHCI0_HC_COMMAND_STATUS, OHCI_CLF);
 274
 275         struct general_td *n=0, *prev = 0, *next = 0;
 276         /* poll until edhead->headp is null */
 277         do {
 278                 sync_before_read(edhead, sizeof(struct endpoint_descriptor));
 279 #ifdef _DU_OHCI_F
 280                 printf("edhead->headp: 0x%08X\n", LE(edhead->headp));
 281                 udelay(10000);
 282 #endif
 283
 284                 /* if halted, debug output plz. will break the transfer */
 285                 if((LE(edhead->headp) & OHCI_ENDPOINT_HALTED)) {
 286                         n = phys_to_virt(LE(edhead->headp)&~0xf);
 287                         prev = phys_to_virt((u32)prev);
 288 #ifdef _DU_OHCI_F
 289                         printf("halted!\n");
 290 #endif
 291
 292                         sync_before_read((void*) n, sizeof(struct general_td));
 293 #ifdef _DU_OHCI_F
 294                         printf("n: 0x%08X\n", n);
 295                         dump_address(n, sizeof(struct general_td), "n(after)");
 296 #endif
 297                         if(n->buflen > 0) {
 298                                 sync_before_read((void*) n->bufaddr, n->buflen);
 299 #ifdef _DU_OHCI_F
 300                                 dump_address((void*) n->bufaddr, n->buflen, "n->bufaddr(after)");
 301 #endif
 302                         }
 303                         dbg_td_flag(LE(n->flags));
 304
 305                         sync_before_read((void*) prev, sizeof(struct general_td));
 306 #ifdef _DU_OHCI_F
 307                         printf("prev: 0x%08X\n", prev);
 308                         dump_address(prev, sizeof(struct general_td), "prev(after)");
 309 #endif
 310                         if(prev->buflen >0) {
 311                                 sync_before_read((void*) prev->bufaddr, prev->buflen);
 312 #ifdef _DU_OHCI_F
 313                                 dump_address((void*) prev->bufaddr, prev->buflen, "prev->bufaddr(after)");
 314 #endif
 315                         }
 316 #ifdef _DU_OHCI_F
 317                         dbg_td_flag(LE(prev->flags));
 318                         printf("halted end!\n");
 319 #endif
 320                         return;
 321                 }
 322                 prev = (struct general_td*) (LE(edhead->headp)&~0xf);
 323         } while(LE(edhead->headp)&~0xf);
 324
 325         n = phys_to_virt(read32(OHCI0_HC_DONE_HEAD) & ~1);
 326 #ifdef _DU_OHCI_F
 327         printf("hc_done_head: 0x%08X\n", read32(OHCI0_HC_DONE_HEAD));
 328 #endif
 329
 330         prev = 0; next = 0;
 331         /* reverse done queue */
 332         while(virt_to_phys(n) && edhead->tdcount) {
 333                 sync_before_read((void*) n, sizeof(struct general_td));
 334 #ifdef _DU_OHCI_F
 335                 printf("n: 0x%08X\n", n);
 336                 printf("next: 0x%08X\n", next);
 337                 printf("prev: 0x%08X\n", prev);
 338 #endif
 339
 340                 next = n;
 341                 n = (struct general_td*) phys_to_virt(LE(n->nexttd));
 342                 next->nexttd = (u32) prev;
 343                 prev = next;
 344
 345                 edhead->tdcount--;
 346         }
 347
 348         n = next;
 349         prev = 0;
 350         while(virt_to_phys(n)) {
 351 #ifdef _DU_OHCI_F
 352                 dump_address(n, sizeof(struct general_td), "n(after)");
 353 #endif
 354                 if(n->buflen > 0) {
 355                         sync_before_read((void*) n->bufaddr, n->buflen);
 356 #ifdef _DU_OHCI_F
 357                         dump_address((void*) n->bufaddr, n->buflen, "n->bufaddr(after)");
 358 #endif
 359                 }
 360 #ifdef _DU_OHCI_F
 361                 dbg_td_flag(LE(n->flags));
 362 #endif
 363                 prev = n;
 364                 n = (struct general_td*) n->nexttd;
 365                 free(prev);
 366         }
 367
 368         hcca_oh0.done_head = 0;
 369         sync_after_write(&hcca_oh0, sizeof(hcca_oh0));
 370
 371         write32(OHCI0_HC_CONTROL, read32(OHCI0_HC_CONTROL)&~OHCI_CTRL_CLE);
 372
 373         edhead = 0;
 374
 375 #ifdef _DU_OHCI_F
 376         printf("<^>  <^>  <^> hcdi_fire(end)\n");
 377 #endif
 378 }
 379
 380 /**
 381  * Enqueue a transfer descriptor.
 382  */
 383 u8 hcdi_enqueue(const usb_transfer_descriptor *td) {
 384 #ifdef _DU_OHCI_Q
 385         printf("*()*()*()*()*()*()*() hcdi_enqueue(start)\n");
 386 #endif
 387         if(!edhead) {
 388                 edhead = &_edhead;
 389                 memset(edhead, 0, sizeof(struct endpoint_descriptor));
 390                 edhead->flags = LE(OHCI_ENDPOINT_GENERAL_FORMAT);
 391                 edhead->headp = edhead->tailp = edhead->nexted = LE(0);
 392                 edhead->flags |= LE(OHCI_ENDPOINT_LOW_SPEED |
 393                                 OHCI_ENDPOINT_SET_DEVICE_ADDRESS(td->devaddress) |
 394                                 OHCI_ENDPOINT_SET_ENDPOINT_NUMBER(td->endpoint) |
 395                                 OHCI_ENDPOINT_SET_MAX_PACKET_SIZE(td->maxp));
 396                 edhead->tdcount = 0;
 397         }
 398
 399         struct general_td *tdhw = allocate_general_td();
 400         general_td_fill(tdhw, td);
 401         edhead->tdcount ++;
 402
 403         if(!edhead->headp) {
 404                 /* first transfer */
 405                 edhead->headp = LE(virt_to_phys((void*) ((u32)tdhw & OHCI_ENDPOINT_HEAD_MASK)));
 406         }
 407         else {
 408                 /* headp in endpoint already exists
 409                  * => go to list end
 410                  */
 411                 struct general_td *n = (struct general_td*) phys_to_virt(LE(edhead->headp) & OHCI_ENDPOINT_HEAD_MASK);
 412                 while(LE(n->nexttd)) {
 413                         n = phys_to_virt(LE(n->nexttd));
 414                 }
 415                 n->nexttd = LE(virt_to_phys((void*) ((u32)tdhw & OHCI_ENDPOINT_HEAD_MASK)));
 416 #ifdef _DU_OHCI_Q
 417                 printf("n: 0x%08X\n", n);
 418                 printf("n->nexttd: 0x%08X\n", phys_to_virt(LE(n->nexttd)));
 419 #endif
 420         }
 421
 422 #ifdef _DU_OHCI_Q
 423         printf("*()*()*()*()*()*()*() hcdi_enqueue(end)\n");
 424 #endif
 425         return 0;
 426 }
 427
 428
 429 /**
 430  * Remove an transfer descriptor from transfer queue.
 431  */
 432 u8 hcdi_dequeue(usb_transfer_descriptor *td) {
 433         return 0;
 434 }
 435
 436 void hcdi_init()
 437 {
 438         printf("ohci-- init\n");
 439         dbg_op_state();
 440
 441         /* disable hc interrupts */
 442         set32(OHCI0_HC_INT_DISABLE, OHCI_INTR_MIE);
 443
 444         /* save fmInterval and calculate FSMPS */
 445 #define FSMP(fi) (0x7fff & ((6 * ((fi) - 210)) / 7))
 446 #define FI 0x2edf /* 12000 bits per frame (-1) */
 447         u32 fmint = read32(OHCI0_HC_FM_INTERVAL) & 0x3fff;
 448         if(fmint != FI)
 449                 printf("ohci-- fminterval delta: %d\n", fmint - FI);
 450         fmint |= FSMP (fmint) << 16;
 451
 452         /* enable interrupts of both usb host controllers */
 453         set32(EHCI_CTL, EHCI_CTL_OH0INTE | EHCI_CTL_OH1INTE | 0xe0000);
 454
 455         /* reset HC */
 456         write32(OHCI0_HC_COMMAND_STATUS, OHCI_HCR);
 457
 458         /* wait max. 30us */
 459         u32 ts = 30;
 460         while ((read32(OHCI0_HC_COMMAND_STATUS) & OHCI_HCR) != 0) {
 461                  if(--ts == 0) {
 462                         printf("ohci-- FAILED");
 463                         return;
 464                  }
 465                  udelay(1);
 466         }
 467
 468         /* disable interrupts; 2ms timelimit here!
 469            now we're in the SUSPEND state ... must go OPERATIONAL
 470            within 2msec else HC enters RESUME */
 471
 472         u32 cookie = irq_kill();
 473
 474         /* Tell the controller where the control and bulk lists are
 475          * The lists are empty now. */
 476         write32(OHCI0_HC_CTRL_HEAD_ED, 0);
 477         write32(OHCI0_HC_BULK_HEAD_ED, 0);
 478
 479         /* set hcca adress */
 480         sync_after_write(&hcca_oh0, 256);
 481         write32(OHCI0_HC_HCCA, virt_to_phys(&hcca_oh0));
 482
 483         /* set periodicstart */
 484 #define FIT (1<<31)
 485         u32 fmInterval = read32(OHCI0_HC_FM_INTERVAL) &0x3fff;
 486         u32 fit = read32(OHCI0_HC_FM_INTERVAL) & FIT;
 487
 488         write32(OHCI0_HC_FM_INTERVAL, fmint | (fit ^ FIT));
 489         write32(OHCI0_HC_PERIODIC_START, ((9*fmInterval)/10)&0x3fff);
 490
 491         /* testing bla */
 492         if ((read32(OHCI0_HC_FM_INTERVAL) & 0x3fff0000) == 0 || !read32(OHCI0_HC_PERIODIC_START)) {
 493                 printf("ohci-- w00t, fail!! see ohci-hcd.c:669\n");
 494         }
 495
 496         /* start HC operations */
 497         write32(OHCI0_HC_CONTROL, OHCI_CONTROL_INIT | OHCI_USB_OPER);
 498
 499         /* wake on ConnectStatusChange, matching external hubs */
 500         write32(OHCI0_HC_RH_STATUS, /*RH_HS_DRWE |*/ RH_HS_LPSC);
 501
 502         /* Choose the interrupts we care about now, others later on demand */
 503         write32(OHCI0_HC_INT_STATUS, ~0);
 504         write32(OHCI0_HC_INT_ENABLE, OHCI_INTR_INIT);
 505
 506         //wtf?
 507         wait_ms ((read32(OHCI0_HC_RH_DESCRIPTOR_A) >> 23) & 0x1fe);
 508
 509         configure_ports((u8)1);
 510         irq_restore(cookie);
 511
 512         dbg_op_state();
 513 }
 514
 515 static void configure_ports(u8 from_init)
 516 {
 517 #ifdef _DU_OHCI_RH
 518         printf("OHCI0_HC_RH_DESCRIPTOR_A:\t0x%08X\n", read32(OHCI0_HC_RH_DESCRIPTOR_A));
 519         printf("OHCI0_HC_RH_DESCRIPTOR_B:\t0x%08X\n", read32(OHCI0_HC_RH_DESCRIPTOR_B));
 520         printf("OHCI0_HC_RH_STATUS:\t\t0x%08X\n", read32(OHCI0_HC_RH_STATUS));
 521         printf("OHCI0_HC_RH_PORT_STATUS_1:\t0x%08X\n", read32(OHCI0_HC_RH_PORT_STATUS_1));
 522         printf("OHCI0_HC_RH_PORT_STATUS_2:\t0x%08X\n", read32(OHCI0_HC_RH_PORT_STATUS_2));
 523 #endif
 524
 525         setup_port(OHCI0_HC_RH_PORT_STATUS_1, from_init);
 526         setup_port(OHCI0_HC_RH_PORT_STATUS_2, from_init);
 527 #ifdef _DU_OHCI_RH
 528         printf("configure_ports done\n");
 529 #endif
 530 }
 531
 532 static void setup_port(u32 reg, u8 from_init)
 533 {
 534         u32 port = read32(reg);
 535         if((port & RH_PS_CCS) && ((port & RH_PS_CSC) || from_init)) {
 536                 write32(reg, RH_PS_CSC);
 537
 538                 wait_ms(120);
 539
 540                 /* clear CSC flag, set PES and start port reset (PRS) */
 541                 write32(reg, RH_PS_PES);
 542                 while(!(read32(reg) & RH_PS_PES)) {
 543 #ifdef _DU_OHCI_RH
 544                         printf("fu\n");
 545 #endif
 546                         return;
 547                 }
 548
 549                 write32(reg, RH_PS_PRS);
 550
 551                 /* spin until port reset is complete */
 552                 while(!(read32(reg) & RH_PS_PRSC)); // hint: it may stuck here
 553 #ifdef _DU_OHCI_RH
 554                 printf("loop done\n");
 555 #endif
 556
 557                 (void) usb_add_device();
 558         }
 559 }
 560
 561 void hcdi_irq()
 562 {
 563         /* read interrupt status */
 564         u32 flags = read32(OHCI0_HC_INT_STATUS);
 565
 566         /* when all bits are set to 1 some problem occured */
 567         if (flags == 0xffffffff) {
 568                 printf("ohci-- Houston, we have a serious problem! :(\n");
 569                 return;
 570         }
 571
 572         /* only care about interrupts that are enabled */
 573         flags &= read32(OHCI0_HC_INT_ENABLE);
 574
 575         /* nothing to do? */
 576         if (flags == 0) {
 577                 printf("OHCI Interrupt occured: but not for you! WTF?!\n");
 578                 return;
 579         }
 580
 581         printf("OHCI Interrupt occured: ");
 582         /* UnrecoverableError */
 583         if (flags & OHCI_INTR_UE) {
 584                 printf("UnrecoverableError\n");
 585                 /* TODO: well, I don't know... nothing,
 586                  *       because it won't happen anyway? ;-) */
 587         }
 588
 589         /* RootHubStatusChange */
 590         if (flags & OHCI_INTR_RHSC) {
 591                 printf("RootHubStatusChange\n");
 592                 /* TODO: set some next_statechange variable... */
 593                 configure_ports(0);
 594                 write32(OHCI0_HC_INT_STATUS, OHCI_INTR_RD | OHCI_INTR_RHSC);
 595         }
 596         /* ResumeDetected */
 597         else if (flags & OHCI_INTR_RD) {
 598                 printf("ResumeDetected\n");
 599                 write32(OHCI0_HC_INT_STATUS, OHCI_INTR_RD);
 600                 /* TODO: figure out what the linux kernel does here... */
 601         }
 602
 603         /* WritebackDoneHead */
 604         if (flags & OHCI_INTR_WDH) {
 605                 printf("WritebackDoneHead\n");
 606                 /* basically the linux irq handler reverse TDs to their urbs
 607                  * and set done_head to null.
 608                  * since we are polling atm, just should do the latter task.
 609                  * however, this won't work for now (i don't know why...)
 610                  * TODO!
 611                  */
 612 #if 0
 613                 sync_before_read(&hcca_oh0, 256);
 614                 hcca_oh0.done_head = 0;
 615                 sync_after_write(&hcca_oh0, 256);
 616 #endif
 617         }
 618
 619         /* TODO: handle any pending URB/ED unlinks... */
 620
 621 #define HC_IS_RUNNING() 1 /* dirty, i know... just a temporary solution */
 622         if (HC_IS_RUNNING()) {
 623                 write32(OHCI0_HC_INT_STATUS, flags);
 624                 write32(OHCI0_HC_INT_ENABLE, OHCI_INTR_MIE);
 625         }
 626 }
 627
 628 void show_frame_no()
 629 {
 630         sync_before_read(&hcca_oh0, 256);
 631         printf("***** frame_no: %d *****\n", LE(hcca_oh0.frame_no));
 632 }