usb/host/ohci.c

   1 /*
   2        ppcskel - a Free Software replacement for the Nintendo/BroadOn bootloader.
   3        ohci hardware support
   4
   5 Copyright (C) 2009     Bernhard Urban <lewurm@gmx.net>
   6 Copyright (C) 2009     Sebastian Falbesoner <sebastian.falbesoner@gmail.com>
   7
   8 # This code is licensed to you under the terms of the GNU GPL, version 2;
   9 # see file COPYING or http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt
  10 */
  11
  12 #include "../../bootmii_ppc.h"
  13 #include "../../hollywood.h"
  14 #include "../../irq.h"
  15 #include "../../string.h"
  16 #include "../../malloc.h"
  17 #include "ohci.h"
  18 #include "host.h"
  19 #include "../usbspec/usb11spec.h"
  20
  21 // macro for accessing u32 variables that need to be in little endian byte order;
  22 // whenever you read or write from an u32 field that the ohci host controller
  23 // will read or write from too, use this macro for access!
  24 #define ACCESS_LE(dword) (u32)( (((dword) & 0xFF000000) >> 24) | \
  25                            (((dword) & 0x00FF0000) >> 8)  | \
  26                            (((dword) & 0x0000FF00) << 8)  | \
  27                            (((dword) & 0x000000FF) << 24) )
  28
  29 static struct endpoint_descriptor *allocate_endpoint();
  30 static struct general_td *allocate_general_td(size_t);
  31 static void control_quirk();
  32 static void dbg_op_state();
  33 static void dbg_td_flag(u32 flag);
  34 static void configure_ports(u8 from_init);
  35 static void setup_port(u32 reg, u8 from_init);
  36
  37 static struct ohci_hcca hcca_oh0;
  38
  39
  40 static struct endpoint_descriptor *allocate_endpoint()
  41 {
  42         struct endpoint_descriptor *ep;
  43         //memalign instead of calloc doesn't work here?! WTF
  44         ep = (struct endpoint_descriptor *)memalign(sizeof(struct endpoint_descriptor), 16);
  45         ep->flags = ACCESS_LE(OHCI_ENDPOINT_GENERAL_FORMAT);
  46         ep->headp = ep->tailp = ep->nexted = ACCESS_LE(0);
  47         return ep;
  48 }
  49
  50 static struct general_td *allocate_general_td(size_t bsize)
  51 {
  52         struct general_td *td;
  53         td = (struct general_td *)memalign(sizeof(struct general_td), 16);
  54         td->flags = ACCESS_LE(0);
  55         // TODO !! nexttd?
  56         td->nexttd = ACCESS_LE(virt_to_phys(td));
  57         //td->nexttd = ACCESS_LE(0);
  58         if(bsize == 0) {
  59                 td->cbp = td->be = ACCESS_LE(0);
  60         } else {
  61                 //td->cbp = ACCESS_LE(virt_to_phys(memalign(bsize, 16))); //memailgn required here?
  62                 td->cbp = ACCESS_LE(virt_to_phys(malloc(bsize)));
  63                 td->be = ACCESS_LE(ACCESS_LE(td->cbp) + bsize - 1);
  64         }
  65         return td;
  66 }
  67
  68 static void control_quirk()
  69 {
  70         static struct endpoint_descriptor *ed = 0; /* empty ED */
  71         static struct general_td *td = 0; /* dummy TD */
  72         u32 head;
  73         u32 current;
  74         u32 status;
  75
  76         /*
  77          * One time only.
  78          * Allocate and keep a special empty ED with just a dummy TD.
  79          */
  80         if (!ed) {
  81                 ed = allocate_endpoint();
  82                 if (!ed)
  83                         return;
  84
  85                 td = allocate_general_td(0);
  86                 if (!td) {
  87                         free(ed);
  88                         ed = NULL;
  89                         return;
  90                 }
  91
  92 #define ED_MASK ((u32)~0x0f)
  93                 ed->tailp = ed->headp = ACCESS_LE(virt_to_phys((void*) ((u32)td & ED_MASK)));
  94                 ed->flags |= ACCESS_LE(OHCI_ENDPOINT_DIRECTION_OUT);
  95         }
  96
  97         /*
  98          * The OHCI USB host controllers on the Nintendo Wii
  99          * video game console stop working when new TDs are
 100          * added to a scheduled control ED after a transfer has
 101          * has taken place on it.
 102          *
 103          * Before scheduling any new control TD, we make the
 104          * controller happy by always loading a special control ED
 105          * with a single dummy TD and letting the controller attempt
 106          * the transfer.
 107          * The controller won't do anything with it, as the special
 108          * ED has no TDs, but it will keep the controller from failing
 109          * on the next transfer.
 110          */
 111         head = read32(OHCI0_HC_CTRL_HEAD_ED);
 112         if (head) {
 113                 printf("head: 0x%08X\n", head);
 114                 /*
 115                  * Load the special empty ED and tell the controller to
 116                  * process the control list.
 117                  */
 118                 sync_after_write(ed, 16);
 119                 sync_after_write(td, 16);
 120                 write32(OHCI0_HC_CTRL_HEAD_ED, virt_to_phys(ed));
 121
 122                 status = read32(OHCI0_HC_CONTROL);
 123                 set32(OHCI0_HC_CONTROL, OHCI_CTRL_CLE);
 124                 write32(OHCI0_HC_COMMAND_STATUS, OHCI_CLF);
 125
 126                 /* spin until the controller is done with the control list */
 127                 current = read32(OHCI0_HC_CTRL_CURRENT_ED);
 128                 while(!current) {
 129                         udelay(10);
 130                         current = read32(OHCI0_HC_CTRL_CURRENT_ED);
 131                 }
 132
 133                 printf("current: 0x%08X\n", current);
 134
 135                 /* restore the old control head and control settings */
 136                 write32(OHCI0_HC_CONTROL, status);
 137                 write32(OHCI0_HC_CTRL_HEAD_ED, head);
 138         } else {
 139                 printf("nohead!\n");
 140         }
 141 }
 142
 143
 144 static void dbg_op_state()
 145 {
 146         switch (read32(OHCI0_HC_CONTROL) & OHCI_CTRL_HCFS) {
 147                 case OHCI_USB_SUSPEND:
 148                         printf("ohci-- OHCI_USB_SUSPEND\n");
 149                         break;
 150                 case OHCI_USB_RESET:
 151                         printf("ohci-- OHCI_USB_RESET\n");
 152                         break;
 153                 case OHCI_USB_OPER:
 154                         printf("ohci-- OHCI_USB_OPER\n");
 155                         break;
 156                 case OHCI_USB_RESUME:
 157                         printf("ohci-- OHCI_USB_RESUME\n");
 158                         break;
 159         }
 160 }
 161
 162 static void dbg_td_flag(u32 flag)
 163 {
 164         printf("**************** dbg_td_flag: 0x%08X ***************\n", flag);
 165         printf("CC: %X\tshould be 0, see page 32 (ohci spec)\n", (flag>>28)&0xf);
 166         printf("EC: %X\tsee page 20 (ohci spec)\n", (flag>>26)&3);
 167         printf(" T: %X\n", (flag>>24)&3);
 168         printf("DI: %X\n", (flag>>21)&7);
 169         printf("DP: %X\n", (flag>>19)&3);
 170         printf(" R: %X\n", (flag>>18)&1);
 171         printf("********************************************************\n");
 172 }
 173
 174
 175
 176 /**
 177  * Enqueue a transfer descriptor.
 178  */
 179 u8 hcdi_enqueue(usb_transfer_descriptor *td) {
 180         control_quirk(); //required? YES! :O
 181
 182         static struct endpoint_descriptor dummyconfig;
 183         dummyconfig.flags = ACCESS_LE(OHCI_ENDPOINT_GENERAL_FORMAT);
 184         dummyconfig.headp = dummyconfig.tailp = dummyconfig.nexted = ACCESS_LE(0);
 185
 186         printf( "===========================\n"
 187                         "===========================\n");
 188         sync_before_read(&hcca_oh0, 256);
 189         printf("done head (nach sync): 0x%08X\n", ACCESS_LE(hcca_oh0.done_head));
 190         printf("HCCA->frame_no: %d\nhcca->hccapad1: %d\n",
 191                         ((ACCESS_LE(hcca_oh0.frame_no) & 0xffff)>>16),
 192                         ACCESS_LE(hcca_oh0.frame_no)&0x0000ffff );
 193
 194         struct general_td *tmptd = allocate_general_td(td->actlen);
 195         (void) memcpy((void*) (phys_to_virt(ACCESS_LE(tmptd->cbp))), td->buffer, td->actlen);
 196
 197         tmptd->flags &= ACCESS_LE(~OHCI_TD_DIRECTION_PID_MASK);
 198         switch(td->pid) {
 199                 case USB_PID_SETUP:
 200                         printf("pid_setup\n");
 201                         tmptd->flags |= ACCESS_LE(OHCI_TD_DIRECTION_PID_SETUP);
 202                         break;
 203                 case USB_PID_OUT:
 204                         printf("pid_out\n");
 205                         tmptd->flags |= ACCESS_LE(OHCI_TD_DIRECTION_PID_OUT);
 206                         break;
 207                 case USB_PID_IN:
 208                         printf("pid_in\n");
 209                         tmptd->flags |= ACCESS_LE(OHCI_TD_DIRECTION_PID_IN);
 210                         break;
 211         }
 212         tmptd->flags |= ACCESS_LE((td->togl) ? OHCI_TD_TOGGLE_1 : OHCI_TD_TOGGLE_0);
 213
 214         printf("tmptd hexdump (before) 0x%08X:\n", tmptd);
 215         hexdump(tmptd, sizeof(struct general_td));
 216         printf("tmptd->cbp hexdump (before) 0x%08X:\n", phys_to_virt(ACCESS_LE(tmptd->cbp)));
 217         hexdump((void*) phys_to_virt(ACCESS_LE(tmptd->cbp)), td->actlen);
 218
 219         sync_after_write(tmptd, sizeof(struct general_td));
 220         sync_after_write((void*) phys_to_virt(ACCESS_LE(tmptd->cbp)), td->actlen);
 221
 222
 223 #define ED_MASK2 ~0 /*((u32)~0x0f) */
 224 #define ED_MASK ((u32)~0x0f)
 225         dummyconfig.headp = ACCESS_LE(virt_to_phys((void*) ((u32)tmptd & ED_MASK)));
 226
 227         dummyconfig.flags |= ACCESS_LE(OHCI_ENDPOINT_LOW_SPEED |
 228                 OHCI_ENDPOINT_SET_DEVICE_ADDRESS(td->devaddress) |
 229                 OHCI_ENDPOINT_SET_ENDPOINT_NUMBER(td->endpoint) |
 230                 OHCI_ENDPOINT_SET_MAX_PACKET_SIZE(td->maxp));
 231
 232         printf("dummyconfig hexdump (before) 0x%08X:\n", &dummyconfig);
 233         hexdump((void*) &dummyconfig, 16);
 234
 235         sync_after_write(&dummyconfig, 16);
 236         write32(OHCI0_HC_CTRL_HEAD_ED, virt_to_phys(&dummyconfig));
 237
 238         printf("OHCI_CTRL_CLE: 0x%08X || ", read32(OHCI0_HC_CONTROL)&OHCI_CTRL_CLE);
 239         printf("OHCI_CLF: 0x%08X\n", read32(OHCI0_HC_COMMAND_STATUS)&OHCI_CLF);
 240         set32(OHCI0_HC_CONTROL, OHCI_CTRL_CLE);
 241         write32(OHCI0_HC_COMMAND_STATUS, OHCI_CLF);
 242
 243         printf("+++++++++++++++++++++++++++++\n");
 244         /* spin until the controller is done with the control list */
 245         u32 current = read32(OHCI0_HC_CTRL_CURRENT_ED);
 246         printf("current: 0x%08X\n", current);
 247         while(!current) {
 248                 udelay(2);
 249                 current = read32(OHCI0_HC_CTRL_CURRENT_ED);
 250         }
 251
 252         udelay(20000);
 253         current = read32(OHCI0_HC_CTRL_CURRENT_ED);
 254         printf("current: 0x%08X\n", current);
 255         printf("+++++++++++++++++++++++++++++\n");
 256         udelay(20000);
 257
 258         sync_before_read(tmptd, sizeof(struct general_td));
 259         printf("tmptd hexdump (after) 0x%08X:\n", tmptd);
 260         hexdump(tmptd, sizeof(struct general_td));
 261         dbg_td_flag(ACCESS_LE(tmptd->flags));
 262
 263         sync_before_read((void*) phys_to_virt(ACCESS_LE(tmptd->cbp)), td->actlen);
 264         printf("tmptd->cbp hexdump (after) 0x%08X:\n", phys_to_virt(ACCESS_LE(tmptd->cbp)));
 265         hexdump((void*) phys_to_virt(ACCESS_LE(tmptd->cbp)), td->actlen);
 266
 267         sync_before_read(&dummyconfig, 16);
 268         printf("dummyconfig hexdump (after) 0x%08X:\n", &dummyconfig);
 269         hexdump((void*) &dummyconfig, 16);
 270
 271         sync_before_read(&hcca_oh0, 256);
 272         printf("done head (nach sync): 0x%08X\n", ACCESS_LE(hcca_oh0.done_head));
 273
 274         sync_before_read((void*) phys_to_virt(ACCESS_LE(tmptd->cbp)), td->actlen);
 275         (void) memcpy((void*) (td->buffer), phys_to_virt(ACCESS_LE(tmptd->cbp)), td->actlen);
 276
 277         write32(OHCI0_HC_CONTROL, read32(OHCI0_HC_CONTROL)&~OHCI_CTRL_CLE);
 278         dummyconfig.headp = dummyconfig.tailp = dummyconfig.nexted = ACCESS_LE(0);
 279         //should be free'd after taking it from the done queue
 280         //however, it fails?! WTF
 281 #if 0
 282         printf("WTF1\n");
 283         free(tmptd);
 284         printf("WTF0\n");
 285         free((void*) tmptd->cbp);
 286         printf("WTF3\n");
 287 #endif
 288         return 0;
 289 }
 290
 291 /**
 292  * Remove an transfer descriptor from transfer queue.
 293  */
 294 u8 hcdi_dequeue(usb_transfer_descriptor *td) {
 295         return 0;
 296 }
 297
 298 void hcdi_init()
 299 {
 300         printf("ohci-- init\n");
 301         dbg_op_state();
 302
 303         /* disable hc interrupts */
 304         set32(OHCI0_HC_INT_DISABLE, OHCI_INTR_MIE);
 305
 306         /* save fmInterval and calculate FSMPS */
 307 #define FSMP(fi) (0x7fff & ((6 * ((fi) - 210)) / 7))
 308 #define FI 0x2edf /* 12000 bits per frame (-1) */
 309         u32 fmint = read32(OHCI0_HC_FM_INTERVAL) & 0x3fff;
 310         if(fmint != FI)
 311                 printf("ohci-- fminterval delta: %d\n", fmint - FI);
 312         fmint |= FSMP (fmint) << 16;
 313
 314         /* enable interrupts of both usb host controllers */
 315         set32(EHCI_CTL, EHCI_CTL_OH0INTE | EHCI_CTL_OH1INTE | 0xe0000);
 316
 317         /* reset HC */
 318         write32(OHCI0_HC_COMMAND_STATUS, OHCI_HCR);
 319
 320         /* wait max. 30us */
 321         u32 ts = 30;
 322         while ((read32(OHCI0_HC_COMMAND_STATUS) & OHCI_HCR) != 0) {
 323                  if(--ts == 0) {
 324                         printf("ohci-- FAILED");
 325                         return;
 326                  }
 327                  udelay(1);
 328         }
 329
 330         /* disable interrupts; 2ms timelimit here!
 331            now we're in the SUSPEND state ... must go OPERATIONAL
 332            within 2msec else HC enters RESUME */
 333
 334         u32 cookie = irq_kill();
 335
 336         /* Tell the controller where the control and bulk lists are
 337          * The lists are empty now. */
 338         write32(OHCI0_HC_CTRL_HEAD_ED, 0);
 339         write32(OHCI0_HC_BULK_HEAD_ED, 0);
 340
 341         /* set hcca adress */
 342         sync_after_write(&hcca_oh0, 256);
 343         write32(OHCI0_HC_HCCA, virt_to_phys(&hcca_oh0));
 344
 345         /* set periodicstart */
 346 #define FIT (1<<31)
 347         u32 fmInterval = read32(OHCI0_HC_FM_INTERVAL) &0x3fff;
 348         u32 fit = read32(OHCI0_HC_FM_INTERVAL) & FIT;
 349
 350         write32(OHCI0_HC_FM_INTERVAL, fmint | (fit ^ FIT));
 351         write32(OHCI0_HC_PERIODIC_START, ((9*fmInterval)/10)&0x3fff);
 352
 353         /* testing bla */
 354         if ((read32(OHCI0_HC_FM_INTERVAL) & 0x3fff0000) == 0 || !read32(OHCI0_HC_PERIODIC_START)) {
 355                 printf("ohci-- w00t, fail!! see ohci-hcd.c:669\n");
 356         }
 357
 358         /* start HC operations */
 359         write32(OHCI0_HC_CONTROL, OHCI_CONTROL_INIT | OHCI_USB_OPER);
 360
 361         /* wake on ConnectStatusChange, matching external hubs */
 362         write32(OHCI0_HC_RH_STATUS, /*RH_HS_DRWE |*/ RH_HS_LPSC);
 363
 364         /* Choose the interrupts we care about now, others later on demand */
 365         write32(OHCI0_HC_INT_STATUS, ~0);
 366         write32(OHCI0_HC_INT_ENABLE, OHCI_INTR_INIT);
 367
 368         //wtf?
 369         wait_ms ((read32(OHCI0_HC_RH_DESCRIPTOR_A) >> 23) & 0x1fe);
 370
 371         configure_ports((u8)1);
 372         irq_restore(cookie);
 373
 374         dbg_op_state();
 375 }
 376
 377 static void configure_ports(u8 from_init)
 378 {
 379         printf("OHCI0_HC_RH_DESCRIPTOR_A:\t0x%08X\n", read32(OHCI0_HC_RH_DESCRIPTOR_A));
 380         printf("OHCI0_HC_RH_DESCRIPTOR_B:\t0x%08X\n", read32(OHCI0_HC_RH_DESCRIPTOR_B));
 381         printf("OHCI0_HC_RH_STATUS:\t\t0x%08X\n", read32(OHCI0_HC_RH_STATUS));
 382         printf("OHCI0_HC_RH_PORT_STATUS_1:\t0x%08X\n", read32(OHCI0_HC_RH_PORT_STATUS_1));
 383         printf("OHCI0_HC_RH_PORT_STATUS_2:\t0x%08X\n", read32(OHCI0_HC_RH_PORT_STATUS_2));
 384
 385         setup_port(OHCI0_HC_RH_PORT_STATUS_1, from_init);
 386         setup_port(OHCI0_HC_RH_PORT_STATUS_2, from_init);
 387         printf("configure_ports done\n");
 388 }
 389
 390 static void setup_port(u32 reg, u8 from_init)
 391 {
 392         u32 port = read32(reg);
 393         if((port & RH_PS_CCS) && ((port & RH_PS_CSC) || from_init)) {
 394                 write32(reg, RH_PS_CSC);
 395
 396                 wait_ms(150);
 397
 398                 /* clear CSC flag, set PES and start port reset (PRS) */
 399                 write32(reg, RH_PS_PES);
 400                 while(!(read32(reg) & RH_PS_PES)) {
 401                         printf("fu\n");
 402                         return;
 403                 }
 404
 405                 write32(reg, RH_PS_PRS);
 406
 407                 /* spin until port reset is complete */
 408                 while(!(read32(reg) & RH_PS_PRSC)); // hint: it may stuck here
 409                 printf("loop done\n");
 410
 411                 (void) usb_add_device();
 412         }
 413 }
 414
 415 void hcdi_irq()
 416 {
 417         /* read interrupt status */
 418         u32 flags = read32(OHCI0_HC_INT_STATUS);
 419
 420         /* when all bits are set to 1 some problem occured */
 421         if (flags == 0xffffffff) {
 422                 printf("ohci-- Houston, we have a serious problem! :(\n");
 423                 return;
 424         }
 425
 426         /* only care about interrupts that are enabled */
 427         flags &= read32(OHCI0_HC_INT_ENABLE);
 428
 429         /* nothing to do? */
 430         if (flags == 0) {
 431                 printf("OHCI Interrupt occured: but not for you! WTF?!\n");
 432                 return;
 433         }
 434
 435         printf("OHCI Interrupt occured: ");
 436         /* UnrecoverableError */
 437         if (flags & OHCI_INTR_UE) {
 438                 printf("UnrecoverableError\n");
 439                 /* TODO: well, I don't know... nothing,
 440                  *       because it won't happen anyway? ;-) */
 441         }
 442
 443         /* RootHubStatusChange */
 444         if (flags & OHCI_INTR_RHSC) {
 445                 printf("RootHubStatusChange\n");
 446                 /* TODO: set some next_statechange variable... */
 447                 configure_ports(0);
 448                 write32(OHCI0_HC_INT_STATUS, OHCI_INTR_RD | OHCI_INTR_RHSC);
 449         }
 450         /* ResumeDetected */
 451         else if (flags & OHCI_INTR_RD) {
 452                 printf("ResumeDetected\n");
 453                 write32(OHCI0_HC_INT_STATUS, OHCI_INTR_RD);
 454                 /* TODO: figure out what the linux kernel does here... */
 455         }
 456
 457         /* WritebackDoneHead */
 458         if (flags & OHCI_INTR_WDH) {
 459                 printf("WritebackDoneHead\n");
 460                 /* basically the linux irq handler reverse TDs to their urbs
 461                  * and set done_head to null.
 462                  * since we are polling atm, just should do the latter task.
 463                  * however, this won't work for now (i don't know why...)
 464                  * TODO!
 465                  */
 466 #if 0
 467                 sync_before_read(&hcca_oh0, 256);
 468                 hcca_oh0.done_head = 0;
 469                 sync_after_write(&hcca_oh0, 256);
 470 #endif
 471         }
 472
 473         /* TODO: handle any pending URB/ED unlinks... */
 474
 475 #define HC_IS_RUNNING() 1 /* dirty, i know... just a temporary solution */
 476         if (HC_IS_RUNNING()) {
 477                 write32(OHCI0_HC_INT_STATUS, flags);
 478                 write32(OHCI0_HC_INT_ENABLE, OHCI_INTR_MIE);
 479         }
 480 }
 481