usb/host/ohci.c

   1 /*
   2        ppcskel - a Free Software replacement for the Nintendo/BroadOn bootloader.
   3        ohci hardware support
   4
   5 Copyright (C) 2009     Bernhard Urban <lewurm@gmx.net>
   6 Copyright (C) 2009     Sebastian Falbesoner <sebastian.falbesoner@gmail.com>
   7
   8 # This code is licensed to you under the terms of the GNU GPL, version 2;
   9 # see file COPYING or http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt
  10 */
  11
  12 #include "../../bootmii_ppc.h"
  13 #include "../../hollywood.h"
  14 #include "../../irq.h"
  15 #include "../../string.h"
  16 #include "../../malloc.h"
  17 #include "ohci.h"
  18 #include "host.h"
  19 #include "../usbspec/usb11spec.h"
  20
  21 // macro for accessing u32 variables that need to be in little endian byte order;
  22 // whenever you read or write from an u32 field that the ohci host controller
  23 // will read or write from too, use this macro for access!
  24 #define ACCESS_LE(dword) (u32)( (((dword) & 0xFF000000) >> 24) | \
  25                            (((dword) & 0x00FF0000) >> 8)  | \
  26                            (((dword) & 0x0000FF00) << 8)  | \
  27                            (((dword) & 0x000000FF) << 24) )
  28
  29 static struct endpoint_descriptor *allocate_endpoint();
  30 static struct general_td *allocate_general_td(size_t);
  31 static void control_quirk();
  32 static void dbg_op_state();
  33 static void dbg_td_flag(u32 flag);
  34 static void configure_ports(u8 from_init);
  35 static void setup_port(u32 reg, u8 from_init);
  36
  37 static struct ohci_hcca hcca_oh0;
  38
  39
  40 static struct endpoint_descriptor *allocate_endpoint()
  41 {
  42         struct endpoint_descriptor *ep;
  43         ep = (struct endpoint_descriptor *)memalign(16, sizeof(struct endpoint_descriptor));
  44         ep->flags = ACCESS_LE(OHCI_ENDPOINT_GENERAL_FORMAT);
  45         ep->headp = ep->tailp = ep->nexted = ACCESS_LE(0);
  46         return ep;
  47 }
  48
  49 static struct general_td *allocate_general_td(size_t bsize)
  50 {
  51         struct general_td *td;
  52         td = (struct general_td *)memalign(16, sizeof(struct general_td));
  53         td->flags = ACCESS_LE(0);
  54         // TODO !! nexttd?
  55         td->nexttd = ACCESS_LE(virt_to_phys(td));
  56         //td->nexttd = ACCESS_LE(0);
  57         if(bsize == 0) {
  58                 td->cbp = td->be = ACCESS_LE(0);
  59         } else {
  60                 //td->cbp = ACCESS_LE(virt_to_phys(memalign(16, bsize))); //memailgn required here?
  61                 //align it to 4kb? :O
  62                 td->cbp = ACCESS_LE(virt_to_phys(malloc(bsize)));
  63                 memset(phys_to_virt(ACCESS_LE(td->cbp)), 0, bsize);
  64                 td->be = ACCESS_LE(ACCESS_LE(td->cbp) + bsize - 1);
  65         }
  66         return td;
  67 }
  68
  69 static void control_quirk()
  70 {
  71         static struct endpoint_descriptor *ed = 0; /* empty ED */
  72         static struct general_td *td = 0; /* dummy TD */
  73         u32 head;
  74         u32 current;
  75         u32 status;
  76
  77         /*
  78          * One time only.
  79          * Allocate and keep a special empty ED with just a dummy TD.
  80          */
  81         if (!ed) {
  82                 ed = allocate_endpoint();
  83                 if (!ed)
  84                         return;
  85
  86                 td = allocate_general_td(0);
  87                 if (!td) {
  88                         free(ed);
  89                         ed = NULL;
  90                         return;
  91                 }
  92
  93 #define ED_MASK ((u32)~0x0f)
  94                 ed->tailp = ed->headp = ACCESS_LE(virt_to_phys((void*) ((u32)td & ED_MASK)));
  95                 ed->flags |= ACCESS_LE(OHCI_ENDPOINT_DIRECTION_OUT);
  96         }
  97
  98         /*
  99          * The OHCI USB host controllers on the Nintendo Wii
 100          * video game console stop working when new TDs are
 101          * added to a scheduled control ED after a transfer has
 102          * has taken place on it.
 103          *
 104          * Before scheduling any new control TD, we make the
 105          * controller happy by always loading a special control ED
 106          * with a single dummy TD and letting the controller attempt
 107          * the transfer.
 108          * The controller won't do anything with it, as the special
 109          * ED has no TDs, but it will keep the controller from failing
 110          * on the next transfer.
 111          */
 112         head = read32(OHCI0_HC_CTRL_HEAD_ED);
 113         if (head) {
 114                 printf("head: 0x%08X\n", head);
 115                 /*
 116                  * Load the special empty ED and tell the controller to
 117                  * process the control list.
 118                  */
 119                 sync_after_write(ed, 16);
 120                 sync_after_write(td, 16);
 121                 write32(OHCI0_HC_CTRL_HEAD_ED, virt_to_phys(ed));
 122
 123                 status = read32(OHCI0_HC_CONTROL);
 124                 set32(OHCI0_HC_CONTROL, OHCI_CTRL_CLE);
 125                 write32(OHCI0_HC_COMMAND_STATUS, OHCI_CLF);
 126
 127                 /* spin until the controller is done with the control list */
 128                 current = read32(OHCI0_HC_CTRL_CURRENT_ED);
 129                 while(!current) {
 130                         udelay(10);
 131                         current = read32(OHCI0_HC_CTRL_CURRENT_ED);
 132                 }
 133
 134                 printf("current: 0x%08X\n", current);
 135
 136                 /* restore the old control head and control settings */
 137                 write32(OHCI0_HC_CONTROL, status);
 138                 write32(OHCI0_HC_CTRL_HEAD_ED, head);
 139         } else {
 140                 printf("nohead!\n");
 141         }
 142 }
 143
 144
 145 static void dbg_op_state()
 146 {
 147         switch (read32(OHCI0_HC_CONTROL) & OHCI_CTRL_HCFS) {
 148                 case OHCI_USB_SUSPEND:
 149                         printf("ohci-- OHCI_USB_SUSPEND\n");
 150                         break;
 151                 case OHCI_USB_RESET:
 152                         printf("ohci-- OHCI_USB_RESET\n");
 153                         break;
 154                 case OHCI_USB_OPER:
 155                         printf("ohci-- OHCI_USB_OPER\n");
 156                         break;
 157                 case OHCI_USB_RESUME:
 158                         printf("ohci-- OHCI_USB_RESUME\n");
 159                         break;
 160         }
 161 }
 162
 163 static void dbg_td_flag(u32 flag)
 164 {
 165         printf("**************** dbg_td_flag: 0x%08X ***************\n", flag);
 166         printf("CC: %X\tshould be 0, see page 32 (ohci spec)\n", (flag>>28)&0xf);
 167         printf("EC: %X\tsee page 20 (ohci spec)\n", (flag>>26)&3);
 168         printf(" T: %X\n", (flag>>24)&3);
 169         printf("DI: %X\n", (flag>>21)&7);
 170         printf("DP: %X\n", (flag>>19)&3);
 171         printf(" R: %X\n", (flag>>18)&1);
 172         printf("********************************************************\n");
 173 }
 174
 175
 176
 177 /**
 178  * Enqueue a transfer descriptor.
 179  */
 180 u8 hcdi_enqueue(usb_transfer_descriptor *td) {
 181         control_quirk(); //required? YES! :O ... erm... or no? :/
 182         u32 tmptdbuffer;
 183
 184         static struct endpoint_descriptor dummyconfig;
 185         memset(&dummyconfig, 0, 16);
 186         dummyconfig.flags = ACCESS_LE(OHCI_ENDPOINT_GENERAL_FORMAT);
 187         dummyconfig.headp = dummyconfig.tailp = dummyconfig.nexted = ACCESS_LE(0);
 188
 189         printf( "===========================\n"
 190                         "===========================\n");
 191         sync_before_read(&hcca_oh0, 256);
 192         printf("done head (nach sync): 0x%08X\n", ACCESS_LE(hcca_oh0.done_head));
 193         printf("HCCA->frame_no: %d\nhcca->hccapad1: %d\n",
 194                         ((ACCESS_LE(hcca_oh0.frame_no) & 0xffff)>>16),
 195                         ACCESS_LE(hcca_oh0.frame_no)&0x0000ffff );
 196
 197         struct general_td *tmptd = allocate_general_td(td->actlen);
 198         (void) memcpy((void*) (phys_to_virt(ACCESS_LE(tmptd->cbp))), td->buffer, td->actlen);
 199
 200         tmptd->flags &= ACCESS_LE(~OHCI_TD_DIRECTION_PID_MASK);
 201         switch(td->pid) {
 202                 case USB_PID_SETUP:
 203                         printf("pid_setup\n");
 204                         tmptd->flags |= ACCESS_LE(OHCI_TD_DIRECTION_PID_SETUP |
 205                                         OHCI_TD_TOGGLE_0 |
 206                                         OHCI_TD_BUFFER_ROUNDING);
 207                         break;
 208                 case USB_PID_OUT:
 209                         printf("pid_out\n");
 210                         tmptd->flags |= ACCESS_LE(OHCI_TD_DIRECTION_PID_OUT);
 211                         tmptd->flags |= ACCESS_LE(((td->togl) ? OHCI_TD_TOGGLE_1 : OHCI_TD_TOGGLE_0));
 212                         break;
 213                 case USB_PID_IN:
 214                         printf("pid_in\n");
 215                         tmptd->flags |= ACCESS_LE(OHCI_TD_DIRECTION_PID_IN);
 216                         tmptd->flags |= ACCESS_LE(((td->togl) ? OHCI_TD_TOGGLE_1 : OHCI_TD_TOGGLE_0));
 217                         break;
 218         }
 219         tmptd->flags |= ACCESS_LE(OHCI_TD_SET_DELAY_INTERRUPT(7));
 220
 221         printf("tmptd hexdump (before) 0x%08X:\n", tmptd);
 222         hexdump(tmptd, sizeof(struct general_td));
 223         //save buffer adress here; HC may change tmptd->cbp
 224         tmptdbuffer = (u32) phys_to_virt(ACCESS_LE(tmptd->cbp));
 225         printf("tmptd->cbp hexdump (before) 0x%08X:\n", phys_to_virt(ACCESS_LE(tmptd->cbp)));
 226         hexdump((void*) phys_to_virt(ACCESS_LE(tmptd->cbp)), td->actlen);
 227
 228         sync_after_write(tmptd, sizeof(struct general_td));
 229         sync_after_write((void*) phys_to_virt(ACCESS_LE(tmptd->cbp)), td->actlen);
 230
 231 #define ED_MASK ((u32)~0x0f)
 232         dummyconfig.headp = ACCESS_LE(virt_to_phys((void*) ((u32)tmptd & ED_MASK)));
 233
 234         dummyconfig.flags |= ACCESS_LE(OHCI_ENDPOINT_LOW_SPEED |
 235                 OHCI_ENDPOINT_SET_DEVICE_ADDRESS(td->devaddress) |
 236                 OHCI_ENDPOINT_SET_ENDPOINT_NUMBER(td->endpoint) |
 237                 OHCI_ENDPOINT_SET_MAX_PACKET_SIZE(td->maxp));
 238
 239         printf("dummyconfig hexdump (before) 0x%08X:\n", &dummyconfig);
 240         hexdump((void*) &dummyconfig, 16);
 241
 242         sync_after_write(&dummyconfig, 16);
 243         write32(OHCI0_HC_CTRL_HEAD_ED, virt_to_phys(&dummyconfig));
 244
 245         printf("OHCI_CTRL_CLE: 0x%08X || ", read32(OHCI0_HC_CONTROL)&OHCI_CTRL_CLE);
 246         printf("OHCI_CLF: 0x%08X\n", read32(OHCI0_HC_COMMAND_STATUS)&OHCI_CLF);
 247         set32(OHCI0_HC_CONTROL, OHCI_CTRL_CLE);
 248         write32(OHCI0_HC_COMMAND_STATUS, OHCI_CLF);
 249
 250         //printf("+++++++++++++++++++++++++++++\n");
 251         /* spin until the controller is done with the control list */
 252         //printf("current: 0x%08X\n", current);
 253
 254         //don't use this quirk stuff here!
 255 #if 1
 256         while(!read32(OHCI0_HC_CTRL_CURRENT_ED)) {
 257         }
 258 #endif
 259
 260         udelay(20000);
 261         u32 current = read32(OHCI0_HC_CTRL_CURRENT_ED);
 262         printf("current: 0x%08X\n", current);
 263         printf("+++++++++++++++++++++++++++++\n");
 264         udelay(20000);
 265
 266         sync_before_read(tmptd, sizeof(struct general_td));
 267         printf("tmptd hexdump (after) 0x%08X:\n", tmptd);
 268         hexdump(tmptd, sizeof(struct general_td));
 269         dbg_td_flag(ACCESS_LE(tmptd->flags));
 270
 271         sync_before_read((void*) phys_to_virt(ACCESS_LE(tmptd->cbp)), td->actlen);
 272         printf("tmptd->cbp hexdump (after) 0x%08X:\n", phys_to_virt(ACCESS_LE(tmptd->cbp)));
 273         hexdump((void*) phys_to_virt(ACCESS_LE(tmptd->cbp)), td->actlen);
 274
 275         sync_before_read(&dummyconfig, 16);
 276         printf("dummyconfig hexdump (after) 0x%08X:\n", &dummyconfig);
 277         hexdump((void*) &dummyconfig, 16);
 278
 279         sync_before_read(&hcca_oh0, 256);
 280         printf("done head (nach sync): 0x%08X\n", ACCESS_LE(hcca_oh0.done_head));
 281
 282         struct general_td* donetd = phys_to_virt(ACCESS_LE(hcca_oh0.done_head)&~1);
 283         sync_before_read(donetd, 16);
 284         printf("done head hexdump: 0x%08X\n", donetd);
 285         hexdump((void*) donetd, 16);
 286
 287         u32 newlen = 0;
 288         if(td->actlen) {
 289                 sync_before_read((void*) tmptdbuffer, td->actlen);
 290                 newlen = (u32)phys_to_virt(ACCESS_LE(tmptd->cbp)) - tmptdbuffer;
 291                 printf("WOOOOT newlen: %d\n", newlen);
 292                 hexdump((void*) tmptdbuffer, newlen);
 293                 printf("OLD length: %d\n", td->actlen);
 294                 hexdump((void*) tmptdbuffer, td->actlen);
 295         }
 296
 297         sync_before_read((void*) (phys_to_virt(ACCESS_LE(tmptd->cbp))-newlen), td->actlen);
 298         printf("td->buffer: 0x%08X\np2v(A_L(tmptd->cbp: 0x%08X\ntd->actlen: %d\n", (void*) (td->buffer), phys_to_virt(ACCESS_LE(tmptd->cbp)), td->actlen);
 299         (void) memcpy((void*) (td->buffer), (void*) tmptdbuffer, td->actlen);
 300
 301         write32(OHCI0_HC_CONTROL, read32(OHCI0_HC_CONTROL)&~OHCI_CTRL_CLE);
 302         dummyconfig.headp = dummyconfig.tailp = dummyconfig.nexted = ACCESS_LE(0);
 303
 304         write32(OHCI0_HC_CTRL_HEAD_ED, virt_to_phys(0));
 305
 306
 307         /*
 308          * TD should be free'd after taking it from the done queue.
 309          * but we are very very dirty and do it anyway :p
 310          */
 311
 312         /* only when a buffer is allocated */
 313 #if 0
 314         if(td->actlen)
 315                 free((void*)tmptdbuffer);
 316         free(tmptd);
 317 #endif
 318         return 0;
 319 }
 320
 321 /**
 322  * Remove an transfer descriptor from transfer queue.
 323  */
 324 u8 hcdi_dequeue(usb_transfer_descriptor *td) {
 325         return 0;
 326 }
 327
 328 void hcdi_init()
 329 {
 330         printf("ohci-- init\n");
 331         dbg_op_state();
 332
 333         /* disable hc interrupts */
 334         set32(OHCI0_HC_INT_DISABLE, OHCI_INTR_MIE);
 335
 336         /* save fmInterval and calculate FSMPS */
 337 #define FSMP(fi) (0x7fff & ((6 * ((fi) - 210)) / 7))
 338 #define FI 0x2edf /* 12000 bits per frame (-1) */
 339         u32 fmint = read32(OHCI0_HC_FM_INTERVAL) & 0x3fff;
 340         if(fmint != FI)
 341                 printf("ohci-- fminterval delta: %d\n", fmint - FI);
 342         fmint |= FSMP (fmint) << 16;
 343
 344         /* enable interrupts of both usb host controllers */
 345         set32(EHCI_CTL, EHCI_CTL_OH0INTE | EHCI_CTL_OH1INTE | 0xe0000);
 346
 347         /* reset HC */
 348         write32(OHCI0_HC_COMMAND_STATUS, OHCI_HCR);
 349
 350         /* wait max. 30us */
 351         u32 ts = 30;
 352         while ((read32(OHCI0_HC_COMMAND_STATUS) & OHCI_HCR) != 0) {
 353                  if(--ts == 0) {
 354                         printf("ohci-- FAILED");
 355                         return;
 356                  }
 357                  udelay(1);
 358         }
 359
 360         /* disable interrupts; 2ms timelimit here!
 361            now we're in the SUSPEND state ... must go OPERATIONAL
 362            within 2msec else HC enters RESUME */
 363
 364         u32 cookie = irq_kill();
 365
 366         /* Tell the controller where the control and bulk lists are
 367          * The lists are empty now. */
 368         write32(OHCI0_HC_CTRL_HEAD_ED, 0);
 369         write32(OHCI0_HC_BULK_HEAD_ED, 0);
 370
 371         /* set hcca adress */
 372         sync_after_write(&hcca_oh0, 256);
 373         write32(OHCI0_HC_HCCA, virt_to_phys(&hcca_oh0));
 374
 375         /* set periodicstart */
 376 #define FIT (1<<31)
 377         u32 fmInterval = read32(OHCI0_HC_FM_INTERVAL) &0x3fff;
 378         u32 fit = read32(OHCI0_HC_FM_INTERVAL) & FIT;
 379
 380         write32(OHCI0_HC_FM_INTERVAL, fmint | (fit ^ FIT));
 381         write32(OHCI0_HC_PERIODIC_START, ((9*fmInterval)/10)&0x3fff);
 382
 383         /* testing bla */
 384         if ((read32(OHCI0_HC_FM_INTERVAL) & 0x3fff0000) == 0 || !read32(OHCI0_HC_PERIODIC_START)) {
 385                 printf("ohci-- w00t, fail!! see ohci-hcd.c:669\n");
 386         }
 387
 388         /* start HC operations */
 389         write32(OHCI0_HC_CONTROL, OHCI_CONTROL_INIT | OHCI_USB_OPER);
 390
 391         /* wake on ConnectStatusChange, matching external hubs */
 392         write32(OHCI0_HC_RH_STATUS, /*RH_HS_DRWE |*/ RH_HS_LPSC);
 393
 394         /* Choose the interrupts we care about now, others later on demand */
 395         write32(OHCI0_HC_INT_STATUS, ~0);
 396         write32(OHCI0_HC_INT_ENABLE, OHCI_INTR_INIT);
 397
 398         //wtf?
 399         wait_ms ((read32(OHCI0_HC_RH_DESCRIPTOR_A) >> 23) & 0x1fe);
 400
 401         configure_ports((u8)1);
 402         irq_restore(cookie);
 403
 404         dbg_op_state();
 405 }
 406
 407 static void configure_ports(u8 from_init)
 408 {
 409         printf("OHCI0_HC_RH_DESCRIPTOR_A:\t0x%08X\n", read32(OHCI0_HC_RH_DESCRIPTOR_A));
 410         printf("OHCI0_HC_RH_DESCRIPTOR_B:\t0x%08X\n", read32(OHCI0_HC_RH_DESCRIPTOR_B));
 411         printf("OHCI0_HC_RH_STATUS:\t\t0x%08X\n", read32(OHCI0_HC_RH_STATUS));
 412         printf("OHCI0_HC_RH_PORT_STATUS_1:\t0x%08X\n", read32(OHCI0_HC_RH_PORT_STATUS_1));
 413         printf("OHCI0_HC_RH_PORT_STATUS_2:\t0x%08X\n", read32(OHCI0_HC_RH_PORT_STATUS_2));
 414
 415         setup_port(OHCI0_HC_RH_PORT_STATUS_1, from_init);
 416         setup_port(OHCI0_HC_RH_PORT_STATUS_2, from_init);
 417         printf("configure_ports done\n");
 418 }
 419
 420 static void setup_port(u32 reg, u8 from_init)
 421 {
 422         u32 port = read32(reg);
 423         if((port & RH_PS_CCS) && ((port & RH_PS_CSC) || from_init)) {
 424                 write32(reg, RH_PS_CSC);
 425
 426                 wait_ms(120);
 427
 428                 /* clear CSC flag, set PES and start port reset (PRS) */
 429                 write32(reg, RH_PS_PES);
 430                 while(!(read32(reg) & RH_PS_PES)) {
 431                         printf("fu\n");
 432                         return;
 433                 }
 434
 435                 write32(reg, RH_PS_PRS);
 436
 437                 /* spin until port reset is complete */
 438                 while(!(read32(reg) & RH_PS_PRSC)); // hint: it may stuck here
 439                 printf("loop done\n");
 440
 441                 wait_ms(20);
 442
 443                 (void) usb_add_device();
 444         }
 445 }
 446
 447 void hcdi_irq()
 448 {
 449         /* read interrupt status */
 450         u32 flags = read32(OHCI0_HC_INT_STATUS);
 451
 452         /* when all bits are set to 1 some problem occured */
 453         if (flags == 0xffffffff) {
 454                 printf("ohci-- Houston, we have a serious problem! :(\n");
 455                 return;
 456         }
 457
 458         /* only care about interrupts that are enabled */
 459         flags &= read32(OHCI0_HC_INT_ENABLE);
 460
 461         /* nothing to do? */
 462         if (flags == 0) {
 463                 printf("OHCI Interrupt occured: but not for you! WTF?!\n");
 464                 return;
 465         }
 466
 467         printf("OHCI Interrupt occured: ");
 468         /* UnrecoverableError */
 469         if (flags & OHCI_INTR_UE) {
 470                 printf("UnrecoverableError\n");
 471                 /* TODO: well, I don't know... nothing,
 472                  *       because it won't happen anyway? ;-) */
 473         }
 474
 475         /* RootHubStatusChange */
 476         if (flags & OHCI_INTR_RHSC) {
 477                 printf("RootHubStatusChange\n");
 478                 /* TODO: set some next_statechange variable... */
 479                 configure_ports(0);
 480                 write32(OHCI0_HC_INT_STATUS, OHCI_INTR_RD | OHCI_INTR_RHSC);
 481         }
 482         /* ResumeDetected */
 483         else if (flags & OHCI_INTR_RD) {
 484                 printf("ResumeDetected\n");
 485                 write32(OHCI0_HC_INT_STATUS, OHCI_INTR_RD);
 486                 /* TODO: figure out what the linux kernel does here... */
 487         }
 488
 489         /* WritebackDoneHead */
 490         if (flags & OHCI_INTR_WDH) {
 491                 printf("WritebackDoneHead\n");
 492                 /* basically the linux irq handler reverse TDs to their urbs
 493                  * and set done_head to null.
 494                  * since we are polling atm, just should do the latter task.
 495                  * however, this won't work for now (i don't know why...)
 496                  * TODO!
 497                  */
 498 #if 0
 499                 sync_before_read(&hcca_oh0, 256);
 500                 hcca_oh0.done_head = 0;
 501                 sync_after_write(&hcca_oh0, 256);
 502 #endif
 503         }
 504
 505         /* TODO: handle any pending URB/ED unlinks... */
 506
 507 #define HC_IS_RUNNING() 1 /* dirty, i know... just a temporary solution */
 508         if (HC_IS_RUNNING()) {
 509                 write32(OHCI0_HC_INT_STATUS, flags);
 510                 write32(OHCI0_HC_INT_ENABLE, OHCI_INTR_MIE);
 511         }
 512 }
 513
 514 void show_frame_no()
 515 {
 516         sync_before_read(&hcca_oh0, 256);
 517         printf("***** frame_no: %d *****\n", ACCESS_LE(hcca_oh0.frame_no));
 518 }