usb/host/ohci.c

   1 /*
   2        ppcskel - a Free Software replacement for the Nintendo/BroadOn bootloader.
   3        ohci hardware support
   4
   5 Copyright (C) 2009     Bernhard Urban <lewurm@gmx.net>
   6 Copyright (C) 2009     Sebastian Falbesoner <sebastian.falbesoner@gmail.com>
   7
   8 # This code is licensed to you under the terms of the GNU GPL, version 2;
   9 # see file COPYING or http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt
  10 */
  11
  12 #include "../../bootmii_ppc.h"
  13 #include "../../hollywood.h"
  14 #include "../../irq.h"
  15 #include "../../string.h"
  16 #include "../../malloc.h"
  17 #include "ohci.h"
  18 #include "host.h"
  19 #include "../usbspec/usb11spec.h"
  20
  21 // macro for accessing u32 variables that need to be in little endian byte order;
  22 // whenever you read or write from an u32 field that the ohci host controller
  23 // will read or write from too, use this macro for access!
  24 #define ACCESS_LE(dword) (u32)( (((dword) & 0xFF000000) >> 24) | \
  25                            (((dword) & 0x00FF0000) >> 8)  | \
  26                            (((dword) & 0x0000FF00) << 8)  | \
  27                            (((dword) & 0x000000FF) << 24) )
  28
  29 static struct endpoint_descriptor *allocate_endpoint();
  30 static struct general_td *allocate_general_td(size_t);
  31 static void control_quirk();
  32 static void dbg_op_state();
  33 static void dbg_td_flag(u32 flag);
  34 static void configure_ports(u8 from_init);
  35 static void setup_port(u32 reg, u8 from_init);
  36
  37 static struct ohci_hcca hcca_oh0;
  38
  39
  40 static struct endpoint_descriptor *allocate_endpoint()
  41 {
  42         struct endpoint_descriptor *ep;
  43         ep = (struct endpoint_descriptor *)memalign(16, sizeof(struct endpoint_descriptor));
  44         ep->flags = ACCESS_LE(OHCI_ENDPOINT_GENERAL_FORMAT);
  45         ep->headp = ep->tailp = ep->nexted = ACCESS_LE(0);
  46         return ep;
  47 }
  48
  49 static struct general_td *allocate_general_td(size_t bsize)
  50 {
  51         struct general_td *td;
  52         td = (struct general_td *)memalign(16, sizeof(struct general_td));
  53         td->flags = ACCESS_LE(0);
  54         // TODO !! nexttd?
  55         td->nexttd = ACCESS_LE(virt_to_phys(td));
  56         //td->nexttd = ACCESS_LE(0);
  57         if(bsize == 0) {
  58                 td->cbp = td->be = ACCESS_LE(0);
  59         } else {
  60                 //align it to 4kb? :O
  61                 //td->cbp = ACCESS_LE(virt_to_phys(memalign(4096, bsize))); //memailgn required here?
  62                 td->cbp = ACCESS_LE(virt_to_phys(malloc(bsize)));
  63                 memset(phys_to_virt(ACCESS_LE(td->cbp)), 0, bsize);
  64                 td->be = ACCESS_LE(ACCESS_LE(td->cbp) + bsize - 1);
  65         }
  66         return td;
  67 }
  68
  69 static void control_quirk()
  70 {
  71         static struct endpoint_descriptor *ed = 0; /* empty ED */
  72         static struct general_td *td = 0; /* dummy TD */
  73         u32 head;
  74         u32 current;
  75         u32 status;
  76
  77         /*
  78          * One time only.
  79          * Allocate and keep a special empty ED with just a dummy TD.
  80          */
  81         if (!ed) {
  82                 ed = allocate_endpoint();
  83                 if (!ed)
  84                         return;
  85
  86                 td = allocate_general_td(0);
  87                 if (!td) {
  88                         free(ed);
  89                         ed = NULL;
  90                         return;
  91                 }
  92
  93 #define ED_MASK ((u32)~0x0f)
  94                 ed->tailp = ed->headp = ACCESS_LE(virt_to_phys((void*) ((u32)td & ED_MASK)));
  95                 ed->flags |= ACCESS_LE(OHCI_ENDPOINT_DIRECTION_OUT);
  96         }
  97
  98         /*
  99          * The OHCI USB host controllers on the Nintendo Wii
 100          * video game console stop working when new TDs are
 101          * added to a scheduled control ED after a transfer has
 102          * has taken place on it.
 103          *
 104          * Before scheduling any new control TD, we make the
 105          * controller happy by always loading a special control ED
 106          * with a single dummy TD and letting the controller attempt
 107          * the transfer.
 108          * The controller won't do anything with it, as the special
 109          * ED has no TDs, but it will keep the controller from failing
 110          * on the next transfer.
 111          */
 112         head = read32(OHCI0_HC_CTRL_HEAD_ED);
 113         if (head) {
 114                 printf("head: 0x%08X\n", head);
 115                 /*
 116                  * Load the special empty ED and tell the controller to
 117                  * process the control list.
 118                  */
 119                 sync_after_write(ed, 16);
 120                 sync_after_write(td, 16);
 121                 write32(OHCI0_HC_CTRL_HEAD_ED, virt_to_phys(ed));
 122
 123                 status = read32(OHCI0_HC_CONTROL);
 124                 set32(OHCI0_HC_CONTROL, OHCI_CTRL_CLE);
 125                 write32(OHCI0_HC_COMMAND_STATUS, OHCI_CLF);
 126
 127                 /* spin until the controller is done with the control list */
 128                 current = read32(OHCI0_HC_CTRL_CURRENT_ED);
 129                 while(!current) {
 130                         udelay(10);
 131                         current = read32(OHCI0_HC_CTRL_CURRENT_ED);
 132                 }
 133
 134                 printf("current: 0x%08X\n", current);
 135
 136                 /* restore the old control head and control settings */
 137                 write32(OHCI0_HC_CONTROL, status);
 138                 write32(OHCI0_HC_CTRL_HEAD_ED, head);
 139         } else {
 140                 printf("nohead!\n");
 141         }
 142 }
 143
 144
 145 static void dbg_op_state()
 146 {
 147         switch (read32(OHCI0_HC_CONTROL) & OHCI_CTRL_HCFS) {
 148                 case OHCI_USB_SUSPEND:
 149                         printf("ohci-- OHCI_USB_SUSPEND\n");
 150                         break;
 151                 case OHCI_USB_RESET:
 152                         printf("ohci-- OHCI_USB_RESET\n");
 153                         break;
 154                 case OHCI_USB_OPER:
 155                         printf("ohci-- OHCI_USB_OPER\n");
 156                         break;
 157                 case OHCI_USB_RESUME:
 158                         printf("ohci-- OHCI_USB_RESUME\n");
 159                         break;
 160         }
 161 }
 162
 163 static void dbg_td_flag(u32 flag)
 164 {
 165         printf("**************** dbg_td_flag: 0x%08X ***************\n", flag);
 166         printf("CC: %X\tshould be 0, see page 32 (ohci spec)\n", (flag>>28)&0xf);
 167         printf("EC: %X\tsee page 20 (ohci spec)\n", (flag>>26)&3);
 168         printf(" T: %X\n", (flag>>24)&3);
 169         printf("DI: %X\n", (flag>>21)&7);
 170         printf("DP: %X\n", (flag>>19)&3);
 171         printf(" R: %X\n", (flag>>18)&1);
 172         printf("********************************************************\n");
 173 }
 174
 175
 176
 177 /**
 178  * Enqueue a transfer descriptor.
 179  */
 180 u8 first = 1;
 181 u8 hcdi_enqueue(usb_transfer_descriptor *td) {
 182         printf( "===========================\n"
 183                         "===========================\n");
 184         control_quirk(); //required? YES! :O ... erm... or no? :/ ... in fact I have no idea
 185         u32 tmptdbuffer;
 186
 187         static struct endpoint_descriptor dummyconfig;
 188         if(first) {
 189                 first = 0;
 190                 memset(&dummyconfig, 0, 16);
 191                 dummyconfig.flags = ACCESS_LE(OHCI_ENDPOINT_GENERAL_FORMAT);
 192                 dummyconfig.headp = dummyconfig.tailp = dummyconfig.nexted = ACCESS_LE(0);
 193                 dummyconfig.flags |= ACCESS_LE(OHCI_ENDPOINT_LOW_SPEED |
 194                                 OHCI_ENDPOINT_SET_DEVICE_ADDRESS(td->devaddress) |
 195                                 OHCI_ENDPOINT_SET_ENDPOINT_NUMBER(td->endpoint) |
 196                                 OHCI_ENDPOINT_SET_MAX_PACKET_SIZE(td->maxp));
 197                 write32(OHCI0_HC_CTRL_HEAD_ED, virt_to_phys(&dummyconfig));
 198         } else {
 199                 sync_before_read(&dummyconfig, 16);
 200                 dummyconfig.flags |= ACCESS_LE(OHCI_ENDPOINT_SKIP);
 201                 printf("HALTED set?: %d\n", ACCESS_LE(dummyconfig.headp)&OHCI_ENDPOINT_HALTED);
 202                 sync_after_write(&dummyconfig, 16);
 203
 204                 udelay(2000);
 205                 dummyconfig.headp = ACCESS_LE(0);
 206                 sync_after_write(&dummyconfig, 16);
 207         }
 208
 209         sync_before_read(&hcca_oh0, 256);
 210         printf("done head (nach sync): 0x%08X\n", ACCESS_LE(hcca_oh0.done_head));
 211         printf("HCCA->frame_no: %d\nhcca->hccapad1: %d\n",
 212                         ((ACCESS_LE(hcca_oh0.frame_no) & 0xffff)>>16),
 213                         ACCESS_LE(hcca_oh0.frame_no)&0x0000ffff );
 214
 215         struct general_td *tmptd = allocate_general_td(td->actlen);
 216         (void) memcpy((void*) (phys_to_virt(ACCESS_LE(tmptd->cbp))), td->buffer, td->actlen);
 217
 218         tmptd->flags &= ACCESS_LE(~OHCI_TD_DIRECTION_PID_MASK);
 219         switch(td->pid) {
 220                 case USB_PID_SETUP:
 221                         printf("pid_setup\n");
 222                         tmptd->flags |= ACCESS_LE(OHCI_TD_DIRECTION_PID_SETUP);
 223                         tmptd->flags |= ACCESS_LE(OHCI_TD_TOGGLE_0);
 224                         tmptd->flags |= ACCESS_LE(OHCI_TD_BUFFER_ROUNDING);
 225                         break;
 226                 case USB_PID_OUT:
 227                         printf("pid_out\n");
 228                         tmptd->flags |= ACCESS_LE(OHCI_TD_DIRECTION_PID_OUT);
 229                         tmptd->flags |= ACCESS_LE(OHCI_TD_BUFFER_ROUNDING);
 230
 231                         /*
 232                          * TODO: just temporary solution!
 233                          * there can be also regular PID_OUT pakets
 234                          */
 235                         tmptd->flags |= ACCESS_LE(OHCI_TD_TOGGLE_1);
 236                         break;
 237                 case USB_PID_IN:
 238                         printf("pid_in\n");
 239                         tmptd->flags |= ACCESS_LE(OHCI_TD_DIRECTION_PID_IN);
 240                         tmptd->flags |= ACCESS_LE(OHCI_TD_BUFFER_ROUNDING);
 241                         /*
 242                          * let the endpoint do the togglestuff!
 243                          * TODO: just temporary solution!
 244                          * there can be also inregular PID_IN pakets (@Status Stage)
 245                          */
 246                         tmptd->flags |= ACCESS_LE(OHCI_TD_TOGGLE_CARRY);
 247 #if 0
 248                         /* should be done by HC!
 249                          * first pid_in start with DATA0 */
 250                          */
 251                         dummyconfig.headp = ACCESS_LE( td->togl ?
 252                                         ACCESS_LE(dummyconfig.headp) | OHCI_ENDPOINT_TOGGLE_CARRY :
 253                                         ACCESS_LE(dummyconfig.headp) & ~OHCI_ENDPOINT_TOGGLE_CARRY);
 254 #endif
 255                         break;
 256         }
 257         tmptd->flags |= ACCESS_LE(OHCI_TD_SET_DELAY_INTERRUPT(7));
 258
 259         printf("tmptd hexdump (before) 0x%08X:\n", tmptd);
 260         hexdump(tmptd, sizeof(struct general_td));
 261         //save buffer adress here; HC may change tmptd->cbp
 262         tmptdbuffer = (u32) phys_to_virt(ACCESS_LE(tmptd->cbp));
 263         printf("tmptd->cbp hexdump (before) 0x%08X:\n", phys_to_virt(ACCESS_LE(tmptd->cbp)));
 264         hexdump((void*) phys_to_virt(ACCESS_LE(tmptd->cbp)), td->actlen);
 265
 266         sync_after_write(tmptd, sizeof(struct general_td));
 267         sync_after_write((void*) phys_to_virt(ACCESS_LE(tmptd->cbp)), td->actlen);
 268
 269
 270 #define ED_MASK ((u32)~0x0f)
 271         dummyconfig.flags &= ACCESS_LE(~OHCI_ENDPOINT_SKIP);
 272         dummyconfig.headp |= ACCESS_LE(virt_to_phys((void*) ((u32)tmptd & ED_MASK)));
 273
 274         printf("dummyconfig hexdump (before) 0x%08X:\n", &dummyconfig);
 275         hexdump((void*) &dummyconfig, 16);
 276
 277         sync_after_write(&dummyconfig, 16);
 278
 279         printf("OHCI_CTRL_CLE: 0x%08X || ", read32(OHCI0_HC_CONTROL)&OHCI_CTRL_CLE);
 280         printf("OHCI_CLF: 0x%08X\n", read32(OHCI0_HC_COMMAND_STATUS)&OHCI_CLF);
 281         set32(OHCI0_HC_CONTROL, OHCI_CTRL_CLE);
 282         write32(OHCI0_HC_COMMAND_STATUS, OHCI_CLF);
 283
 284         //printf("+++++++++++++++++++++++++++++\n");
 285         /* spin until the controller is done with the control list */
 286         //printf("current: 0x%08X\n", current);
 287
 288         //don't use this quirk stuff here!
 289 #if 1
 290         while(!read32(OHCI0_HC_CTRL_CURRENT_ED)) {
 291         }
 292 #endif
 293
 294         udelay(20000);
 295         u32 current = read32(OHCI0_HC_CTRL_CURRENT_ED);
 296         printf("current: 0x%08X\n", current);
 297         printf("+++++++++++++++++++++++++++++\n");
 298         udelay(20000);
 299
 300         sync_before_read(tmptd, sizeof(struct general_td));
 301         printf("tmptd hexdump (after) 0x%08X:\n", tmptd);
 302         hexdump(tmptd, sizeof(struct general_td));
 303         dbg_td_flag(ACCESS_LE(tmptd->flags));
 304
 305         sync_before_read((void*) phys_to_virt(ACCESS_LE(tmptd->cbp)), td->actlen);
 306         printf("tmptd->cbp hexdump (after) 0x%08X:\n", phys_to_virt(ACCESS_LE(tmptd->cbp)));
 307         hexdump((void*) phys_to_virt(ACCESS_LE(tmptd->cbp)), td->actlen);
 308
 309         sync_before_read(&dummyconfig, 16);
 310         printf("dummyconfig hexdump (after) 0x%08X:\n", &dummyconfig);
 311         hexdump((void*) &dummyconfig, 16);
 312
 313         sync_before_read(&hcca_oh0, 256);
 314         printf("done head (nach sync): 0x%08X\n", ACCESS_LE(hcca_oh0.done_head));
 315
 316         struct general_td* donetd = phys_to_virt(ACCESS_LE(hcca_oh0.done_head)&~1);
 317         sync_before_read(donetd, 16);
 318         printf("done head hexdump: 0x%08X\n", donetd);
 319         hexdump((void*) donetd, 16);
 320
 321         u32 newlen = 0;
 322         if(td->actlen) {
 323                 sync_before_read((void*) tmptdbuffer, td->actlen);
 324                 newlen = (u32)phys_to_virt(ACCESS_LE(tmptd->cbp)) - tmptdbuffer;
 325                 printf("WOOOOT newlen: %d\n", newlen);
 326                 hexdump((void*) tmptdbuffer, newlen);
 327                 printf("OLD length: %d\n", td->actlen);
 328                 hexdump((void*) tmptdbuffer, td->actlen);
 329         }
 330
 331         sync_before_read((void*) (phys_to_virt(ACCESS_LE(tmptd->cbp))-newlen), td->actlen);
 332         printf("td->buffer: 0x%08X\np2v(A_L(tmptd->cbp: 0x%08X\ntd->actlen: %d\n", (void*) (td->buffer), phys_to_virt(ACCESS_LE(tmptd->cbp)), td->actlen);
 333         (void) memcpy((void*) (td->buffer), (void*) tmptdbuffer, td->actlen);
 334
 335         write32(OHCI0_HC_CONTROL, read32(OHCI0_HC_CONTROL)&~OHCI_CTRL_CLE);
 336
 337         /*
 338          * TD should be free'd after taking it from the done queue.
 339          * but we are very very dirty and do it anyway :p
 340          */
 341
 342         /* only when a buffer is allocated */
 343 #if 0
 344         if(td->actlen)
 345                 free((void*)tmptdbuffer);
 346         free(tmptd);
 347 #endif
 348         return 0;
 349 }
 350
 351 /**
 352  * Remove an transfer descriptor from transfer queue.
 353  */
 354 u8 hcdi_dequeue(usb_transfer_descriptor *td) {
 355         return 0;
 356 }
 357
 358 void hcdi_init()
 359 {
 360         printf("ohci-- init\n");
 361         dbg_op_state();
 362
 363         /* disable hc interrupts */
 364         set32(OHCI0_HC_INT_DISABLE, OHCI_INTR_MIE);
 365
 366         /* save fmInterval and calculate FSMPS */
 367 #define FSMP(fi) (0x7fff & ((6 * ((fi) - 210)) / 7))
 368 #define FI 0x2edf /* 12000 bits per frame (-1) */
 369         u32 fmint = read32(OHCI0_HC_FM_INTERVAL) & 0x3fff;
 370         if(fmint != FI)
 371                 printf("ohci-- fminterval delta: %d\n", fmint - FI);
 372         fmint |= FSMP (fmint) << 16;
 373
 374         /* enable interrupts of both usb host controllers */
 375         set32(EHCI_CTL, EHCI_CTL_OH0INTE | EHCI_CTL_OH1INTE | 0xe0000);
 376
 377         /* reset HC */
 378         write32(OHCI0_HC_COMMAND_STATUS, OHCI_HCR);
 379
 380         /* wait max. 30us */
 381         u32 ts = 30;
 382         while ((read32(OHCI0_HC_COMMAND_STATUS) & OHCI_HCR) != 0) {
 383                  if(--ts == 0) {
 384                         printf("ohci-- FAILED");
 385                         return;
 386                  }
 387                  udelay(1);
 388         }
 389
 390         /* disable interrupts; 2ms timelimit here!
 391            now we're in the SUSPEND state ... must go OPERATIONAL
 392            within 2msec else HC enters RESUME */
 393
 394         u32 cookie = irq_kill();
 395
 396         /* Tell the controller where the control and bulk lists are
 397          * The lists are empty now. */
 398         write32(OHCI0_HC_CTRL_HEAD_ED, 0);
 399         write32(OHCI0_HC_BULK_HEAD_ED, 0);
 400
 401         /* set hcca adress */
 402         sync_after_write(&hcca_oh0, 256);
 403         write32(OHCI0_HC_HCCA, virt_to_phys(&hcca_oh0));
 404
 405         /* set periodicstart */
 406 #define FIT (1<<31)
 407         u32 fmInterval = read32(OHCI0_HC_FM_INTERVAL) &0x3fff;
 408         u32 fit = read32(OHCI0_HC_FM_INTERVAL) & FIT;
 409
 410         write32(OHCI0_HC_FM_INTERVAL, fmint | (fit ^ FIT));
 411         write32(OHCI0_HC_PERIODIC_START, ((9*fmInterval)/10)&0x3fff);
 412
 413         /* testing bla */
 414         if ((read32(OHCI0_HC_FM_INTERVAL) & 0x3fff0000) == 0 || !read32(OHCI0_HC_PERIODIC_START)) {
 415                 printf("ohci-- w00t, fail!! see ohci-hcd.c:669\n");
 416         }
 417
 418         /* start HC operations */
 419         write32(OHCI0_HC_CONTROL, OHCI_CONTROL_INIT | OHCI_USB_OPER);
 420
 421         /* wake on ConnectStatusChange, matching external hubs */
 422         write32(OHCI0_HC_RH_STATUS, /*RH_HS_DRWE |*/ RH_HS_LPSC);
 423
 424         /* Choose the interrupts we care about now, others later on demand */
 425         write32(OHCI0_HC_INT_STATUS, ~0);
 426         write32(OHCI0_HC_INT_ENABLE, OHCI_INTR_INIT);
 427
 428         //wtf?
 429         wait_ms ((read32(OHCI0_HC_RH_DESCRIPTOR_A) >> 23) & 0x1fe);
 430
 431         configure_ports((u8)1);
 432         irq_restore(cookie);
 433
 434         dbg_op_state();
 435 }
 436
 437 static void configure_ports(u8 from_init)
 438 {
 439         printf("OHCI0_HC_RH_DESCRIPTOR_A:\t0x%08X\n", read32(OHCI0_HC_RH_DESCRIPTOR_A));
 440         printf("OHCI0_HC_RH_DESCRIPTOR_B:\t0x%08X\n", read32(OHCI0_HC_RH_DESCRIPTOR_B));
 441         printf("OHCI0_HC_RH_STATUS:\t\t0x%08X\n", read32(OHCI0_HC_RH_STATUS));
 442         printf("OHCI0_HC_RH_PORT_STATUS_1:\t0x%08X\n", read32(OHCI0_HC_RH_PORT_STATUS_1));
 443         printf("OHCI0_HC_RH_PORT_STATUS_2:\t0x%08X\n", read32(OHCI0_HC_RH_PORT_STATUS_2));
 444
 445         setup_port(OHCI0_HC_RH_PORT_STATUS_1, from_init);
 446         setup_port(OHCI0_HC_RH_PORT_STATUS_2, from_init);
 447         printf("configure_ports done\n");
 448 }
 449
 450 static void setup_port(u32 reg, u8 from_init)
 451 {
 452         u32 port = read32(reg);
 453         if((port & RH_PS_CCS) && ((port & RH_PS_CSC) || from_init)) {
 454                 write32(reg, RH_PS_CSC);
 455
 456                 wait_ms(120);
 457
 458                 /* clear CSC flag, set PES and start port reset (PRS) */
 459                 write32(reg, RH_PS_PES);
 460                 while(!(read32(reg) & RH_PS_PES)) {
 461                         printf("fu\n");
 462                         return;
 463                 }
 464
 465                 write32(reg, RH_PS_PRS);
 466
 467                 /* spin until port reset is complete */
 468                 while(!(read32(reg) & RH_PS_PRSC)); // hint: it may stuck here
 469                 printf("loop done\n");
 470
 471                 wait_ms(20);
 472
 473                 (void) usb_add_device();
 474         }
 475 }
 476
 477 void hcdi_irq()
 478 {
 479         /* read interrupt status */
 480         u32 flags = read32(OHCI0_HC_INT_STATUS);
 481
 482         /* when all bits are set to 1 some problem occured */
 483         if (flags == 0xffffffff) {
 484                 printf("ohci-- Houston, we have a serious problem! :(\n");
 485                 return;
 486         }
 487
 488         /* only care about interrupts that are enabled */
 489         flags &= read32(OHCI0_HC_INT_ENABLE);
 490
 491         /* nothing to do? */
 492         if (flags == 0) {
 493                 printf("OHCI Interrupt occured: but not for you! WTF?!\n");
 494                 return;
 495         }
 496
 497         printf("OHCI Interrupt occured: ");
 498         /* UnrecoverableError */
 499         if (flags & OHCI_INTR_UE) {
 500                 printf("UnrecoverableError\n");
 501                 /* TODO: well, I don't know... nothing,
 502                  *       because it won't happen anyway? ;-) */
 503         }
 504
 505         /* RootHubStatusChange */
 506         if (flags & OHCI_INTR_RHSC) {
 507                 printf("RootHubStatusChange\n");
 508                 /* TODO: set some next_statechange variable... */
 509                 configure_ports(0);
 510                 write32(OHCI0_HC_INT_STATUS, OHCI_INTR_RD | OHCI_INTR_RHSC);
 511         }
 512         /* ResumeDetected */
 513         else if (flags & OHCI_INTR_RD) {
 514                 printf("ResumeDetected\n");
 515                 write32(OHCI0_HC_INT_STATUS, OHCI_INTR_RD);
 516                 /* TODO: figure out what the linux kernel does here... */
 517         }
 518
 519         /* WritebackDoneHead */
 520         if (flags & OHCI_INTR_WDH) {
 521                 printf("WritebackDoneHead\n");
 522                 /* basically the linux irq handler reverse TDs to their urbs
 523                  * and set done_head to null.
 524                  * since we are polling atm, just should do the latter task.
 525                  * however, this won't work for now (i don't know why...)
 526                  * TODO!
 527                  */
 528 #if 0
 529                 sync_before_read(&hcca_oh0, 256);
 530                 hcca_oh0.done_head = 0;
 531                 sync_after_write(&hcca_oh0, 256);
 532 #endif
 533         }
 534
 535         /* TODO: handle any pending URB/ED unlinks... */
 536
 537 #define HC_IS_RUNNING() 1 /* dirty, i know... just a temporary solution */
 538         if (HC_IS_RUNNING()) {
 539                 write32(OHCI0_HC_INT_STATUS, flags);
 540                 write32(OHCI0_HC_INT_ENABLE, OHCI_INTR_MIE);
 541         }
 542 }
 543
 544 void show_frame_no()
 545 {
 546         sync_before_read(&hcca_oh0, 256);
 547         printf("***** frame_no: %d *****\n", ACCESS_LE(hcca_oh0.frame_no));
 548 }