usb/host/ohci.c

   1 /*
   2        ppcskel - a Free Software replacement for the Nintendo/BroadOn bootloader.
   3        ohci hardware support
   4
   5 Copyright (C) 2009     Bernhard Urban <lewurm@gmx.net>
   6 Copyright (C) 2009     Sebastian Falbesoner <sebastian.falbesoner@gmail.com>
   7
   8 # This code is licensed to you under the terms of the GNU GPL, version 2;
   9 # see file COPYING or http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt
  10 */
  11
  12 #include "../../bootmii_ppc.h"
  13 #include "../../hollywood.h"
  14 #include "../../irq.h"
  15 #include "../../string.h"
  16 #include "../../malloc.h"
  17 #include "ohci.h"
  18 #include "host.h"
  19 #include "../usbspec/usb11spec.h"
  20
  21 // macro for accessing u32 variables that need to be in little endian byte order;
  22 // whenever you read or write from an u32 field that the ohci host controller
  23 // will read or write from too, use this macro for access!
  24 #define ACCESS_LE(dword) (u32)( (((dword) & 0xFF000000) >> 24) | \
  25                            (((dword) & 0x00FF0000) >> 8)  | \
  26                            (((dword) & 0x0000FF00) << 8)  | \
  27                            (((dword) & 0x000000FF) << 24) )
  28
  29 static struct ohci_hcca hcca_oh0;
  30
  31 static struct endpoint_descriptor *allocate_endpoint()
  32 {
  33         struct endpoint_descriptor *ep;
  34         ep = (struct endpoint_descriptor *)calloc(sizeof(struct endpoint_descriptor), 16);
  35         ep->flags = ACCESS_LE(OHCI_ENDPOINT_GENERAL_FORMAT);
  36         ep->headp = ep->tailp = ep->nexted = ACCESS_LE(0);
  37         return ep;
  38 }
  39
  40 static struct general_td *allocate_general_td(size_t bsize)
  41 {
  42         struct general_td *td;
  43         td = (struct general_td *)calloc(sizeof(struct general_td), 16);
  44         td->flags = ACCESS_LE(0);
  45         td->nexttd = ACCESS_LE(virt_to_phys(td));
  46         if(bsize == 0) {
  47                 td->cbp = td->be = ACCESS_LE(0);
  48         } else {
  49                 td->cbp = ACCESS_LE(virt_to_phys(malloc(bsize)));
  50                 td->be = ACCESS_LE(ACCESS_LE(td->cbp) + bsize - 1);
  51         }
  52         return td;
  53 }
  54
  55 static void control_quirk()
  56 {
  57         static struct endpoint_descriptor *ed; /* empty ED */
  58         static struct general_td *td; /* dummy TD */
  59         u32 head;
  60         u32 current;
  61         u32 status;
  62
  63         /*
  64          * One time only.
  65          * Allocate and keep a special empty ED with just a dummy TD.
  66          */
  67         if (!ed) {
  68                 ed = allocate_endpoint();
  69                 if (!ed)
  70                         return;
  71
  72                 td = allocate_general_td(0);
  73                 if (!td) {
  74                         free(ed);
  75                         ed = NULL;
  76                         return;
  77                 }
  78
  79 #define ED_MASK ((u32)~0x0f)
  80                 ed->tailp = ed->headp = ACCESS_LE(virt_to_phys((void*) ((u32)td & ED_MASK)));
  81                 ed->flags |= ACCESS_LE(OHCI_ENDPOINT_DIRECTION_OUT);
  82         }
  83
  84         /*
  85          * The OHCI USB host controllers on the Nintendo Wii
  86          * video game console stop working when new TDs are
  87          * added to a scheduled control ED after a transfer has
  88          * has taken place on it.
  89          *
  90          * Before scheduling any new control TD, we make the
  91          * controller happy by always loading a special control ED
  92          * with a single dummy TD and letting the controller attempt
  93          * the transfer.
  94          * The controller won't do anything with it, as the special
  95          * ED has no TDs, but it will keep the controller from failing
  96          * on the next transfer.
  97          */
  98         head = read32(OHCI0_HC_CTRL_HEAD_ED);
  99         if (head) {
 100                 printf("head: 0x%08X\n", head);
 101                 /*
 102                  * Load the special empty ED and tell the controller to
 103                  * process the control list.
 104                  */
 105                 sync_after_write(ed, 64);
 106                 sync_after_write(td, 64);
 107                 write32(OHCI0_HC_CTRL_HEAD_ED, virt_to_phys(ed));
 108
 109                 status = read32(OHCI0_HC_CONTROL);
 110                 set32(OHCI0_HC_CONTROL, OHCI_CTRL_CLE);
 111                 write32(OHCI0_HC_COMMAND_STATUS, OHCI_CLF);
 112
 113                 /* spin until the controller is done with the control list */
 114                 current = read32(OHCI0_HC_CTRL_CURRENT_ED);
 115                 while(!current) {
 116                         udelay(10);
 117                         current = read32(OHCI0_HC_CTRL_CURRENT_ED);
 118                 }
 119
 120                 printf("current: 0x%08X\n", current);
 121
 122                 /* restore the old control head and control settings */
 123                 write32(OHCI0_HC_CONTROL, status);
 124                 write32(OHCI0_HC_CTRL_HEAD_ED, head);
 125         } else {
 126                 printf("nohead!\n");
 127         }
 128 }
 129
 130
 131 static void dbg_op_state()
 132 {
 133         switch (read32(OHCI0_HC_CONTROL) & OHCI_CTRL_HCFS) {
 134                 case OHCI_USB_SUSPEND:
 135                         printf("ohci-- OHCI_USB_SUSPEND\n");
 136                         break;
 137                 case OHCI_USB_RESET:
 138                         printf("ohci-- OHCI_USB_RESET\n");
 139                         break;
 140                 case OHCI_USB_OPER:
 141                         printf("ohci-- OHCI_USB_OPER\n");
 142                         break;
 143                 case OHCI_USB_RESUME:
 144                         printf("ohci-- OHCI_USB_RESUME\n");
 145                         break;
 146         }
 147 }
 148
 149
 150 /**
 151  * Enqueue a transfer descriptor.
 152  */
 153 u8 first = 0;
 154 u8 hcdi_enqueue(usb_transfer_descriptor *td) {
 155         control_quirk();
 156
 157         printf( "===========================\n"
 158                         "===========================\n"
 159                         "done head (vor sync): 0x%08X\n", ACCESS_LE(hcca_oh0.done_head));
 160         sync_before_read(&hcca_oh0, 256);
 161         printf("done head (nach sync): 0x%08X\n", ACCESS_LE(hcca_oh0.done_head));
 162         printf("HCCA->frame_no after %d seconds: %d\n", 0, ACCESS_LE(hcca_oh0.frame_no));
 163         printf("HCCA->frame_no WITHOUT conversion macro: %d\n", hcca_oh0.frame_no);
 164         if(!first) {
 165                 first = 1;
 166                 udelay(1000000);
 167                 sync_before_read(&hcca_oh0, 256);
 168                 printf("HCCA->frame_no after %d seconds: %d\n", 1, ACCESS_LE(hcca_oh0.frame_no));
 169                 printf("HCCA->frame_no WITHOUT conversion macro: %d\n", hcca_oh0.frame_no);
 170         }
 171
 172         struct general_td *tmptd = allocate_general_td(td->actlen);
 173         (void) memcpy((void*) (phys_to_virt(ACCESS_LE(tmptd->cbp))), td->buffer, td->actlen); /* throws dsi exception after some time :X */
 174
 175         tmptd->flags &= ACCESS_LE(~OHCI_TD_DIRECTION_PID_MASK);
 176         switch(td->pid) {
 177                 case USB_PID_SETUP:
 178                         printf("pid_setup\n");
 179                         tmptd->flags |= ACCESS_LE(OHCI_TD_DIRECTION_PID_SETUP);
 180                         break;
 181                 case USB_PID_OUT:
 182                         printf("pid_out\n");
 183                         tmptd->flags |= ACCESS_LE(OHCI_TD_DIRECTION_PID_OUT);
 184                         break;
 185                 case USB_PID_IN:
 186                         printf("pid_in\n");
 187                         tmptd->flags |= ACCESS_LE(OHCI_TD_DIRECTION_PID_IN);
 188                         break;
 189         }
 190         tmptd->flags |= ACCESS_LE((td->togl) ? OHCI_TD_TOGGLE_1 : OHCI_TD_TOGGLE_0);
 191
 192         printf("tmptd hexump (before):\n");
 193         hexdump(tmptd, sizeof(struct general_td));
 194         printf("tmptd-cbp hexump (before):\n");
 195         hexdump((void*) (phys_to_virt(ACCESS_LE(tmptd->cbp))), td->actlen);
 196
 197         sync_after_write((void*) ACCESS_LE(tmptd->cbp), td->actlen);
 198         sync_after_write(tmptd, sizeof(struct general_td));
 199
 200         struct endpoint_descriptor *dummyconfig = allocate_endpoint();
 201
 202         u32 current2 = read32(OHCI0_HC_CTRL_CURRENT_ED);
 203         printf("current2: 0x%08X\n", current2);
 204
 205 #define ED_MASK2 ~0 /*((u32)~0x0f) */
 206 #define ED_MASK ((u32)~0x0f)
 207         printf("tmpdt & ED_MASK: 0x%08X\n", virt_to_phys((void*) ((u32)tmptd & ED_MASK)));
 208         dummyconfig->tailp = dummyconfig->headp = ACCESS_LE(virt_to_phys((void*) ((u32)tmptd & ED_MASK)));
 209
 210         dummyconfig->flags |= ACCESS_LE(OHCI_ENDPOINT_LOW_SPEED |
 211                 OHCI_ENDPOINT_SET_DEVICE_ADDRESS(td->devaddress) |
 212                 OHCI_ENDPOINT_SET_ENDPOINT_NUMBER(td->endpoint) |
 213                 OHCI_ENDPOINT_SET_MAX_PACKET_SIZE(td->maxp));
 214
 215         sync_after_write(dummyconfig, 64);
 216         write32(OHCI0_HC_CTRL_HEAD_ED, virt_to_phys(dummyconfig));
 217
 218         printf("OHCI_CTRL_CLE: 0x%08X\n", read32(OHCI0_HC_CONTROL)&OHCI_CTRL_CLE);
 219         printf("OHCI_CLF: 0x%08X\n", read32(OHCI0_HC_COMMAND_STATUS)&OHCI_CLF);
 220         set32(OHCI0_HC_CONTROL, OHCI_CTRL_CLE);
 221         write32(OHCI0_HC_COMMAND_STATUS, OHCI_CLF);
 222
 223         printf("+++++++++++++++++++++++++++++\n");
 224         /* spin until the controller is done with the control list */
 225         u32 current = read32(OHCI0_HC_CTRL_CURRENT_ED);
 226         printf("current: 0x%08X\n", current);
 227         while(!current) {
 228                 udelay(10);
 229                 current = read32(OHCI0_HC_CTRL_CURRENT_ED);
 230         }
 231
 232         udelay(2000);
 233         udelay(2000);
 234         udelay(2000);
 235         current = read32(OHCI0_HC_CTRL_CURRENT_ED);
 236         printf("current: 0x%08X\n", current);
 237         printf("+++++++++++++++++++++++++++++\n");
 238         udelay(2000);
 239         udelay(2000);
 240         udelay(2000);
 241         udelay(2000);
 242         udelay(2000);
 243         udelay(2000);
 244         udelay(2000);
 245         udelay(2000);
 246
 247         sync_before_read(tmptd, sizeof(struct general_td));
 248         printf("tmptd hexump (after):\n");
 249         hexdump(tmptd, sizeof(struct general_td));
 250
 251         sync_before_read((void*) ACCESS_LE(tmptd->cbp), td->actlen);
 252         printf("tmptd-cbp hexump (after):\n");
 253         hexdump((void*) (phys_to_virt(ACCESS_LE(tmptd->cbp))), td->actlen);
 254
 255         printf("done head (vor sync): 0x%08X\n", ACCESS_LE(hcca_oh0.done_head));
 256         sync_before_read(&hcca_oh0, 256);
 257         printf("done head (nach sync): 0x%08X\n", ACCESS_LE(hcca_oh0.done_head));
 258
 259         free(tmptd);
 260         return 0;
 261 }
 262
 263 /**
 264  * Remove an transfer descriptor from transfer queue.
 265  */
 266 u8 hcdi_dequeue(usb_transfer_descriptor *td) {
 267         return 0;
 268 }
 269
 270 void hcdi_init()
 271 {
 272         printf("ohci-- init\n");
 273         dbg_op_state();
 274
 275         /* disable hc interrupts */
 276         set32(OHCI0_HC_INT_DISABLE, OHCI_INTR_MIE);
 277
 278         /* save fmInterval and calculate FSMPS */
 279 #define FSMP(fi) (0x7fff & ((6 * ((fi) - 210)) / 7))
 280 #define FI 0x2edf /* 12000 bits per frame (-1) */
 281         u32 fmint = read32(OHCI0_HC_FM_INTERVAL) & 0x3fff;
 282         if(fmint != FI)
 283                 printf("ohci-- fminterval delta: %d\n", fmint - FI);
 284         fmint |= FSMP (fmint) << 16;
 285
 286         /* enable interrupts of both usb host controllers */
 287         set32(EHCI_CTL, EHCI_CTL_OH0INTE | EHCI_CTL_OH1INTE | 0xe0000);
 288
 289         /* reset HC */
 290         write32(OHCI0_HC_COMMAND_STATUS, OHCI_HCR);
 291
 292         /* wait max. 30us */
 293         u32 ts = 30;
 294         while ((read32(OHCI0_HC_COMMAND_STATUS) & OHCI_HCR) != 0) {
 295                  if(--ts == 0) {
 296                         printf("ohci-- FAILED");
 297                         return;
 298                  }
 299                  udelay(1);
 300         }
 301
 302         /* disable interrupts; 2ms timelimit here!
 303            now we're in the SUSPEND state ... must go OPERATIONAL
 304            within 2msec else HC enters RESUME */
 305
 306         u32 cookie = irq_kill();
 307
 308         /* Tell the controller where the control and bulk lists are
 309          * The lists are empty now. */
 310         write32(OHCI0_HC_CTRL_HEAD_ED, 0);
 311         write32(OHCI0_HC_BULK_HEAD_ED, 0);
 312
 313         /* set hcca adress */
 314         sync_after_write(&hcca_oh0, 256);
 315         write32(OHCI0_HC_HCCA, virt_to_phys(&hcca_oh0));
 316
 317         /* set periodicstart */
 318 #define FIT (1<<31)
 319         u32 fmInterval = read32(OHCI0_HC_FM_INTERVAL) &0x3fff;
 320         u32 fit = read32(OHCI0_HC_FM_INTERVAL) & FIT;
 321
 322         write32(OHCI0_HC_FM_INTERVAL, fmint | (fit ^ FIT));
 323         write32(OHCI0_HC_PERIODIC_START, ((9*fmInterval)/10)&0x3fff);
 324
 325         /* testing bla */
 326         if ((read32(OHCI0_HC_FM_INTERVAL) & 0x3fff0000) == 0 || !read32(OHCI0_HC_PERIODIC_START)) {
 327                 printf("ohci-- w00t, fail!! see ohci-hcd.c:669\n");
 328         }
 329
 330         /* start HC operations */
 331         write32(OHCI0_HC_CONTROL, OHCI_CONTROL_INIT | OHCI_USB_OPER);
 332
 333         /* wake on ConnectStatusChange, matching external hubs */
 334         set32(OHCI0_HC_RH_STATUS, RH_HS_DRWE);
 335
 336         /* Choose the interrupts we care about now, others later on demand */
 337         write32(OHCI0_HC_INT_STATUS, ~0);
 338         write32(OHCI0_HC_INT_ENABLE, OHCI_INTR_INIT);
 339
 340         irq_restore(cookie);
 341
 342         dbg_op_state();
 343 }
 344
 345 void hcdi_irq()
 346 {
 347         /* read interrupt status */
 348         u32 flags = read32(OHCI0_HC_INT_STATUS);
 349
 350         /* when all bits are set to 1 some problem occured */
 351         if (flags == 0xffffffff) {
 352                 printf("ohci-- Houston, we have a serious problem! :(\n");
 353                 return;
 354         }
 355
 356         /* only care about interrupts that are enabled */
 357         flags &= read32(OHCI0_HC_INT_ENABLE);
 358
 359         /* nothing to do? */
 360         if (flags == 0)
 361                 return;
 362
 363         printf("OHCI Interrupt occured: ");
 364         /* UnrecoverableError */
 365         if (flags & OHCI_INTR_UE) {
 366                 printf("UnrecoverableError\n");
 367                 /* TODO: well, I don't know... nothing,
 368                  *       because it won't happen anyway? ;-) */
 369         }
 370
 371         /* RootHubStatusChange */
 372         if (flags & OHCI_INTR_RHSC) {
 373                 printf("RootHubStatusChange\n");
 374                 /* TODO: set some next_statechange variable... */
 375                 write32(OHCI0_HC_INT_STATUS, OHCI_INTR_RD | OHCI_INTR_RHSC);
 376         }
 377         /* ResumeDetected */
 378         else if (flags & OHCI_INTR_RD) {
 379                 printf("ResumeDetected\n");
 380                 write32(OHCI0_HC_INT_STATUS, OHCI_INTR_RD);
 381                 /* TODO: figure out what the linux kernel does here... */
 382         }
 383
 384         /* WritebackDoneHead */
 385         if (flags & OHCI_INTR_WDH) {
 386                 printf("WritebackDoneHead\n");
 387                 /* TODO: figure out what the linux kernel does here... */
 388         }
 389
 390         /* TODO: handle any pending URB/ED unlinks... */
 391
 392 #define HC_IS_RUNNING() 1 /* dirty, i know... just a temporary solution */
 393         if (HC_IS_RUNNING()) {
 394                 write32(OHCI0_HC_INT_STATUS, flags);
 395                 write32(OHCI0_HC_INT_ENABLE, OHCI_INTR_MIE);
 396         }
 397 }
 398