usb/host/ohci.c

   1 /*
   2        ppcskel - a Free Software replacement for the Nintendo/BroadOn bootloader.
   3        ohci hardware support
   4
   5 Copyright (C) 2009     Bernhard Urban <lewurm@gmx.net>
   6 Copyright (C) 2009     Sebastian Falbesoner <sebastian.falbesoner@gmail.com>
   7
   8 # This code is licensed to you under the terms of the GNU GPL, version 2;
   9 # see file COPYING or http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt
  10 */
  11
  12 #include "../../bootmii_ppc.h"
  13 #include "../../hollywood.h"
  14 #include "../../irq.h"
  15 #include "../../string.h"
  16 #include "../../malloc.h"
  17 #include "ohci.h"
  18 #include "host.h"
  19 #include "../usbspec/usb11spec.h"
  20
  21 /* activate control_quirk */
  22 #define _USE_C_Q
  23
  24 /* macro for accessing u32 variables that need to be in little endian byte order;
  25  *
  26  * whenever you read or write from an u32 field that the ohci host controller
  27  * will read or write from too, use this macro for access!
  28  */
  29 #define LE(dword) (u32)( (((dword) & 0xFF000000) >> 24) | \
  30                            (((dword) & 0x00FF0000) >> 8)  | \
  31                            (((dword) & 0x0000FF00) << 8)  | \
  32                            (((dword) & 0x000000FF) << 24) )
  33
  34 static struct general_td *allocate_general_td();
  35 static void dbg_op_state(u32 reg);
  36 static void configure_ports(u8 from_init, u32 reg);
  37 static void setup_port(u32 ohci, u32 reg, u8 from_init);
  38
  39 static struct ohci_hcca hcca_oh0;
  40 static struct ohci_hcca hcca_oh1;
  41
  42
  43 static struct general_td *allocate_general_td()
  44 {
  45         struct general_td *td;
  46         td = (struct general_td *)memalign(16, sizeof(struct general_td));
  47         memset(td, 0, sizeof(struct general_td));
  48         td->flags = LE(0);
  49         td->nexttd = LE(0);
  50         td->cbp = td->be = LE(0);
  51         return td;
  52 }
  53
  54
  55 static void dbg_op_state(u32 reg)
  56 {
  57         switch (read32(reg+OHCI_HC_CONTROL) & OHCI_CTRL_HCFS) {
  58                 case OHCI_USB_SUSPEND:
  59                         printf("ohci-- OHCI_USB_SUSPEND\n");
  60                         break;
  61                 case OHCI_USB_RESET:
  62                         printf("ohci-- OHCI_USB_RESET\n");
  63                         break;
  64                 case OHCI_USB_OPER:
  65                         printf("ohci-- OHCI_USB_OPER\n");
  66                         break;
  67                 case OHCI_USB_RESUME:
  68                         printf("ohci-- OHCI_USB_RESUME\n");
  69                         break;
  70         }
  71 }
  72
  73 #ifdef _DU_OHCI_F_HALT
  74 static void dbg_td_flag(u32 flag)
  75 {
  76         printf("**************** dbg_td_flag: 0x%08X ***************\n", flag);
  77         printf("CC: %X\tshould be 0, see page 32 (ohci spec)\n", (flag>>28)&0xf);
  78         printf("EC: %X\tsee page 20 (ohci spec)\n", (flag>>26)&3);
  79         printf(" T: %X\n", (flag>>24)&3);
  80         printf("DI: %X\n", (flag>>21)&7);
  81         printf("DP: %X\n", (flag>>19)&3);
  82         printf(" R: %X\n", (flag>>18)&1);
  83         printf("********************************************************\n");
  84 }
  85 #endif
  86
  87 static void general_td_fill(struct general_td *dest, const struct usb_transfer_descriptor *src)
  88 {
  89         if(src->actlen) {
  90                 dest->cbp = LE(virt_to_phys(src->buffer));
  91                 dest->be = LE(LE(dest->cbp) + src->actlen - 1);
  92                 /* save virtual address here */
  93                 dest->bufaddr = (u32) src->buffer;
  94         }
  95         else {
  96                 dest->cbp = dest->be = LE(0);
  97                 dest->bufaddr = 0;
  98         }
  99
 100         dest->buflen = src->actlen;
 101
 102         dest->flags &= LE(~OHCI_TD_DIRECTION_PID_MASK);
 103         switch(src->pid) {
 104                 case USB_PID_SETUP:
 105 #ifdef _DU_OHCI_Q
 106                         printf("pid_setup\n");
 107 #endif
 108                         dest->flags |= LE(OHCI_TD_DIRECTION_PID_SETUP);
 109                         dest->flags |= LE(OHCI_TD_TOGGLE_0);
 110                         dest->flags |= LE(OHCI_TD_BUFFER_ROUNDING);
 111                         break;
 112                 case USB_PID_OUT:
 113 #ifdef _DU_OHCI_Q
 114                         printf("pid_out\n");
 115 #endif
 116                         dest->flags |= LE(OHCI_TD_DIRECTION_PID_OUT);
 117                         dest->flags |= LE(OHCI_TD_BUFFER_ROUNDING);
 118
 119                         dest->flags |= src->togl ? LE(OHCI_TD_TOGGLE_1) : LE(OHCI_TD_TOGGLE_0);
 120                         break;
 121                 case USB_PID_IN:
 122 #ifdef _DU_OHCI_Q
 123                         printf("pid_in\n");
 124 #endif
 125                         dest->flags |= LE(OHCI_TD_DIRECTION_PID_IN);
 126                         if(src->maxp > src->actlen) {
 127                                 dest->flags |= LE(OHCI_TD_BUFFER_ROUNDING);
 128 #ifdef _DU_OHCI_Q
 129                                 printf("round buffer!\n");
 130 #endif
 131                         }
 132                         dest->flags |= src->togl ? LE(OHCI_TD_TOGGLE_1) : LE(OHCI_TD_TOGGLE_0);
 133                         break;
 134         }
 135         dest->flags |= LE(OHCI_TD_SET_DELAY_INTERRUPT(7));
 136 }
 137
 138 #ifdef _DU_OHCI_F_HALT
 139 static void dump_address(void *addr, u32 size, const char* str)
 140 {
 141         printf("%s hexdump (%d) @ 0x%08X:\n", str, size, addr);
 142         hexdump(addr, size);
 143 }
 144 #endif
 145
 146 static struct endpoint_descriptor _edhead;
 147 struct endpoint_descriptor *edhead = 0;
 148 void hcdi_fire(u32 reg)
 149 {
 150 #ifdef _DU_OHCI_F
 151         printf("<^>  <^>  <^> hcdi_fire(start)\n");
 152 #endif
 153
 154         if(edhead == 0)
 155                 return;
 156
 157 #ifdef _USE_C_Q
 158         /* quirk... 11ms seems to be a minimum :O */
 159         udelay(11000);
 160 #endif
 161
 162         write32(reg+OHCI_HC_CTRL_HEAD_ED, virt_to_phys(edhead));
 163
 164         /* sync it all */
 165         sync_after_write(edhead, sizeof(struct endpoint_descriptor));
 166 #ifdef _DU_OHCI_F
 167         dump_address(edhead, sizeof(struct endpoint_descriptor), "edhead(before)");
 168 #endif
 169
 170         struct general_td *x = phys_to_virt(LE(edhead->headp) & OHCI_ENDPOINT_HEAD_MASK);
 171         while(virt_to_phys(x)) {
 172                 sync_after_write(x, sizeof(struct general_td));
 173 #ifdef _DU_OHCI_F
 174                 dump_address(x, sizeof(struct general_td), "x(before)");
 175 #endif
 176
 177                 if(x->buflen > 0) {
 178                         sync_after_write((void*) phys_to_virt(LE(x->cbp)), x->buflen);
 179 #ifdef _DU_OHCI_F
 180                         dump_address((void*) phys_to_virt(LE(x->cbp)), x->buflen, "x->cbp(before)");
 181 #endif
 182                 }
 183                 x = phys_to_virt(LE(x->nexttd));
 184         }
 185
 186         /* trigger control list */
 187         set32(reg+OHCI_HC_CONTROL, OHCI_CTRL_CLE);
 188         write32(reg+OHCI_HC_COMMAND_STATUS, OHCI_CLF);
 189
 190         struct general_td *n=0, *prev = 0, *next = 0;
 191         /* poll until edhead->headp is null */
 192         do {
 193                 sync_before_read(edhead, sizeof(struct endpoint_descriptor));
 194 #ifdef _DU_OHCI_F
 195                 printf("edhead->headp: 0x%08X\n", LE(edhead->headp));
 196 #endif
 197
 198                 /* if halted, debug output plz. will break the transfer */
 199                 if((LE(edhead->headp) & OHCI_ENDPOINT_HALTED)) {
 200                         n = phys_to_virt(LE(edhead->headp)&~0xf);
 201                         prev = phys_to_virt((u32)prev);
 202 #ifdef _DU_OHCI_F_HALT
 203                         printf("halted!\n");
 204 #endif
 205
 206                         sync_before_read((void*) n, sizeof(struct general_td));
 207 #ifdef _DU_OHCI_F_HALT
 208                         printf("n: 0x%08X\n", n);
 209                         dump_address(n, sizeof(struct general_td), "n(after)");
 210 #endif
 211                         if(n->buflen > 0) {
 212                                 sync_before_read((void*) n->bufaddr, n->buflen);
 213 #ifdef _DU_OHCI_F_HALT
 214                                 dump_address((void*) n->bufaddr, n->buflen, "n->bufaddr(after)");
 215 #endif
 216                         }
 217 #ifdef _DU_OHCI_F_HALT
 218                         dbg_td_flag(LE(n->flags));
 219 #endif
 220
 221                         sync_before_read((void*) prev, sizeof(struct general_td));
 222 #ifdef _DU_OHCI_F_HALT
 223                         printf("prev: 0x%08X\n", prev);
 224                         dump_address(prev, sizeof(struct general_td), "prev(after)");
 225 #endif
 226                         if(prev->buflen >0) {
 227                                 sync_before_read((void*) prev->bufaddr, prev->buflen);
 228 #ifdef _DU_OHCI_F_HALT
 229                                 dump_address((void*) prev->bufaddr, prev->buflen, "prev->bufaddr(after)");
 230 #endif
 231                         }
 232 #ifdef _DU_OHCI_F_HALT
 233                         dbg_td_flag(LE(prev->flags));
 234                         printf("halted end!\n");
 235 #endif
 236                         goto out;
 237                 }
 238                 prev = (struct general_td*) (LE(edhead->headp)&~0xf);
 239         } while(LE(edhead->headp)&~0xf);
 240
 241         n = phys_to_virt(read32(reg+OHCI_HC_DONE_HEAD) & ~1);
 242 #ifdef _DU_OHCI_F
 243         printf("hc_done_head: 0x%08X\n", read32(reg+OHCI_HC_DONE_HEAD));
 244 #endif
 245
 246         prev = 0; next = 0;
 247         /* reverse done queue */
 248         while(virt_to_phys(n) && edhead->tdcount) {
 249                 sync_before_read((void*) n, sizeof(struct general_td));
 250 #ifdef _DU_OHCI_F
 251                 printf("n: 0x%08X\n", n);
 252                 printf("next: 0x%08X\n", next);
 253                 printf("prev: 0x%08X\n", prev);
 254 #endif
 255
 256                 next = n;
 257                 n = (struct general_td*) phys_to_virt(LE(n->nexttd));
 258                 next->nexttd = (u32) prev;
 259                 prev = next;
 260
 261                 edhead->tdcount--;
 262         }
 263
 264         n = next;
 265         prev = 0;
 266         while(virt_to_phys(n)) {
 267 #ifdef _DU_OHCI_F
 268                 dump_address(n, sizeof(struct general_td), "n(after)");
 269 #endif
 270                 if(n->buflen > 0) {
 271                         sync_before_read((void*) n->bufaddr, n->buflen);
 272 #ifdef _DU_OHCI_F
 273                         dump_address((void*) n->bufaddr, n->buflen, "n->bufaddr(after)");
 274 #endif
 275                 }
 276 #ifdef _DU_OHCI_F
 277                 dbg_td_flag(LE(n->flags));
 278 #endif
 279                 prev = n;
 280                 n = (struct general_td*) n->nexttd;
 281                 free(prev);
 282         }
 283
 284         if(reg == OHCI0_REG_BASE) {
 285                 hcca_oh0.done_head = 0;
 286                 sync_after_write(&hcca_oh0, sizeof(hcca_oh0));
 287         } else if (reg == OHCI1_REG_BASE) {
 288                 hcca_oh1.done_head = 0;
 289                 sync_after_write(&hcca_oh1, sizeof(hcca_oh1));
 290         }
 291
 292 out:
 293         write32(reg+OHCI_HC_CONTROL, read32(reg+OHCI_HC_CONTROL)&~OHCI_CTRL_CLE);
 294
 295         edhead = 0;
 296
 297 #ifdef _DU_OHCI_F
 298         printf("<^>  <^>  <^> hcdi_fire(end)\n");
 299 #endif
 300 }
 301
 302 /**
 303  * Enqueue a transfer descriptor.
 304  */
 305 u8 hcdi_enqueue(const struct usb_transfer_descriptor *td, u32 reg) {
 306 #ifdef _DU_OHCI_Q
 307         printf("*()*()*()*()*()*()*() hcdi_enqueue(start)\n");
 308 #endif
 309         if(!edhead) {
 310                 edhead = &_edhead;
 311                 memset(edhead, 0, sizeof(struct endpoint_descriptor));
 312                 edhead->flags = LE(OHCI_ENDPOINT_GENERAL_FORMAT);
 313                 edhead->headp = edhead->tailp = edhead->nexted = LE(0);
 314                 if(td->fullspeed) {
 315                         edhead->flags |= LE(OHCI_ENDPOINT_FULL_SPEED);
 316                 } else {
 317                         edhead->flags |= LE(OHCI_ENDPOINT_LOW_SPEED);
 318                 }
 319                 edhead->flags |= LE(OHCI_ENDPOINT_SET_DEVICE_ADDRESS(td->devaddress) |
 320                                 OHCI_ENDPOINT_SET_ENDPOINT_NUMBER(td->endpoint) |
 321                                 OHCI_ENDPOINT_SET_MAX_PACKET_SIZE(td->maxp));
 322                 edhead->tdcount = 0;
 323         }
 324
 325         struct general_td *tdhw = allocate_general_td();
 326         general_td_fill(tdhw, td);
 327         edhead->tdcount ++;
 328
 329         if(!edhead->headp) {
 330                 /* first transfer */
 331                 edhead->headp = LE(virt_to_phys((void*) ((u32)tdhw & OHCI_ENDPOINT_HEAD_MASK)));
 332         }
 333         else {
 334                 /* headp in endpoint already exists
 335                  * => go to list end
 336                  */
 337                 struct general_td *n = (struct general_td*) phys_to_virt(LE(edhead->headp) & OHCI_ENDPOINT_HEAD_MASK);
 338                 while(LE(n->nexttd)) {
 339                         n = phys_to_virt(LE(n->nexttd));
 340                 }
 341                 n->nexttd = LE(virt_to_phys((void*) ((u32)tdhw & OHCI_ENDPOINT_HEAD_MASK)));
 342 #ifdef _DU_OHCI_Q
 343                 printf("n: 0x%08X\n", n);
 344                 printf("n->nexttd: 0x%08X\n", phys_to_virt(LE(n->nexttd)));
 345 #endif
 346         }
 347
 348 #ifdef _DU_OHCI_Q
 349         printf("*()*()*()*()*()*()*() hcdi_enqueue(end)\n");
 350 #endif
 351         return 0;
 352 }
 353
 354
 355 /**
 356  * Remove an transfer descriptor from transfer queue.
 357  */
 358 u8 hcdi_dequeue(struct usb_transfer_descriptor *td, u32 reg) {
 359         return 0;
 360 }
 361
 362 void hcdi_init(u32 reg)
 363 {
 364         printf("ohci-- init\n");
 365         dbg_op_state(reg);
 366
 367         /* disable hc interrupts */
 368         set32(reg+OHCI_HC_INT_DISABLE, OHCI_INTR_MIE);
 369
 370         /* save fmInterval and calculate FSMPS */
 371 #define FSMP(fi) (0x7fff & ((6 * ((fi) - 210)) / 7))
 372 #define FI 0x2edf /* 12000 bits per frame (-1) */
 373         u32 fmint = read32(reg+OHCI_HC_FM_INTERVAL) & 0x3fff;
 374         if(fmint != FI)
 375                 printf("ohci-- fminterval delta: %d\n", fmint - FI);
 376         fmint |= FSMP (fmint) << 16;
 377
 378         /* enable interrupts of both usb host controllers */
 379         set32(EHCI_CTL, EHCI_CTL_OH0INTE | EHCI_CTL_OH1INTE | 0xe0000);
 380
 381         /* reset HC */
 382         write32(reg+OHCI_HC_COMMAND_STATUS, OHCI_HCR);
 383
 384         /* wait max. 30us */
 385         u32 ts = 30;
 386         while ((read32(reg+OHCI_HC_COMMAND_STATUS) & OHCI_HCR) != 0) {
 387                  if(--ts == 0) {
 388                         printf("ohci-- FAILED");
 389                         return;
 390                  }
 391                  udelay(1);
 392         }
 393
 394         /* disable interrupts; 2ms timelimit here!
 395            now we're in the SUSPEND state ... must go OPERATIONAL
 396            within 2msec else HC enters RESUME */
 397
 398         u32 cookie = irq_kill();
 399
 400         /* Tell the controller where the control and bulk lists are
 401          * The lists are empty now. */
 402         write32(reg+OHCI_HC_CTRL_HEAD_ED, 0);
 403         write32(reg+OHCI_HC_BULK_HEAD_ED, 0);
 404
 405         /* set hcca adress */
 406         if(reg == OHCI0_REG_BASE) {
 407                 sync_after_write(&hcca_oh0, 256);
 408                 write32(reg+OHCI_HC_HCCA, virt_to_phys(&hcca_oh0));
 409         } else {
 410                 sync_after_write(&hcca_oh1, 256);
 411                 write32(reg+OHCI_HC_HCCA, virt_to_phys(&hcca_oh1));
 412         }
 413
 414         /* set periodicstart */
 415 #define FIT (1<<31)
 416         u32 fmInterval = read32(reg+OHCI_HC_FM_INTERVAL) &0x3fff;
 417         u32 fit = read32(reg+OHCI_HC_FM_INTERVAL) & FIT;
 418
 419         write32(reg+OHCI_HC_FM_INTERVAL, fmint | (fit ^ FIT));
 420         write32(reg+OHCI_HC_PERIODIC_START, ((9*fmInterval)/10)&0x3fff);
 421
 422         /* testing bla */
 423         if ((read32(reg+OHCI_HC_FM_INTERVAL) & 0x3fff0000) == 0 || !read32(reg+OHCI_HC_PERIODIC_START)) {
 424                 printf("ohci-- w00t, fail!! see ohci-hcd.c:669\n");
 425         }
 426
 427         /* start HC operations */
 428         write32(reg+OHCI_HC_CONTROL, OHCI_CONTROL_INIT | OHCI_USB_OPER);
 429
 430         /* wake on ConnectStatusChange, matching external hubs */
 431         write32(reg+OHCI_HC_RH_STATUS, /*RH_HS_DRWE |*/ RH_HS_LPSC);
 432
 433         /* Choose the interrupts we care about now, others later on demand */
 434         write32(reg+OHCI_HC_INT_STATUS, ~0);
 435         write32(reg+OHCI_HC_INT_ENABLE, OHCI_INTR_INIT);
 436
 437         //wtf?
 438         wait_ms ((read32(reg+OHCI_HC_RH_DESCRIPTOR_A) >> 23) & 0x1fe);
 439
 440         configure_ports((u8)1, reg);
 441         irq_restore(cookie);
 442
 443         dbg_op_state(reg);
 444 }
 445
 446 static void configure_ports(u8 from_init, u32 reg)
 447 {
 448 #ifdef _DU_OHCI_RH
 449         printf("=== Roothub @ %s ===\n", reg == OHCI0_REG_BASE ? "OHCI0" : "OHCI1");
 450         printf("OHCI_HC_RH_DESCRIPTOR_A:\t0x%08X\n", read32(reg+OHCI_HC_RH_DESCRIPTOR_A));
 451         printf("OHCI_HC_RH_DESCRIPTOR_B:\t0x%08X\n", read32(reg+OHCI_HC_RH_DESCRIPTOR_B));
 452         printf("OHCI_HC_RH_STATUS:\t\t0x%08X\n", read32(reg+OHCI_HC_RH_STATUS));
 453         printf("OHCI_HC_RH_PORT_STATUS_1:\t0x%08X\n", read32(reg+OHCI_HC_RH_PORT_STATUS_1));
 454         printf("OHCI_HC_RH_PORT_STATUS_2:\t0x%08X\n", read32(reg+OHCI_HC_RH_PORT_STATUS_2));
 455 #endif
 456
 457         setup_port(reg, reg+OHCI_HC_RH_PORT_STATUS_1, from_init);
 458         setup_port(reg, reg+OHCI_HC_RH_PORT_STATUS_2, from_init);
 459 #ifdef _DU_OHCI_RH
 460         printf("configure_ports done\n");
 461 #endif
 462 }
 463
 464 static void setup_port(u32 ohci, u32 reg, u8 from_init)
 465 {
 466         u32 port = read32(reg);
 467         if((port & RH_PS_CCS) && ((port & RH_PS_CSC) || from_init)) {
 468                 write32(reg, RH_PS_CSC);
 469
 470                 wait_ms(120);
 471
 472                 /* clear CSC flag, set PES and start port reset (PRS) */
 473                 write32(reg, RH_PS_PES);
 474                 while(!(read32(reg) & RH_PS_PES)) {
 475 #ifdef _DU_OHCI_RH
 476                         printf("fu\n");
 477 #endif
 478                         return;
 479                 }
 480
 481                 write32(reg, RH_PS_PRS);
 482
 483                 /* spin until port reset is complete */
 484                 while(!(read32(reg) & RH_PS_PRSC)); // hint: it may stuck here
 485 #ifdef _DU_OHCI_RH
 486                 printf("loop done\n");
 487 #endif
 488
 489                 /* returns usb_device struct */
 490                 (void) usb_add_device((read32(reg) & RH_PS_LSDA) >> 8, ohci);
 491         }
 492 }
 493
 494 void hcdi_irq(u32 reg)
 495 {
 496         /* read interrupt status */
 497         u32 flags = read32(reg+OHCI_HC_INT_STATUS);
 498
 499         /* when all bits are set to 1 some problem occured */
 500         if (flags == 0xffffffff) {
 501                 printf("ohci-- Houston, we have a serious problem! :(\n");
 502                 return;
 503         }
 504
 505         /* only care about interrupts that are enabled */
 506         flags &= read32(reg+OHCI_HC_INT_ENABLE);
 507
 508         /* nothing to do? */
 509         if (flags == 0) {
 510                 printf("OHCI Interrupt occured: but not for you! WTF?!\n");
 511                 return;
 512         }
 513
 514         printf("OHCI Interrupt occured: ");
 515         /* UnrecoverableError */
 516         if (flags & OHCI_INTR_UE) {
 517                 printf("UnrecoverableError\n");
 518                 /* TODO: well, I don't know... nothing,
 519                  *       because it won't happen anyway? ;-) */
 520         }
 521
 522         /* RootHubStatusChange */
 523         if (flags & OHCI_INTR_RHSC) {
 524                 printf("RootHubStatusChange\n");
 525                 /* TODO: set some next_statechange variable... */
 526                 configure_ports(0, reg);
 527                 write32(reg+OHCI_HC_INT_STATUS, OHCI_INTR_RD | OHCI_INTR_RHSC);
 528         }
 529         /* ResumeDetected */
 530         else if (flags & OHCI_INTR_RD) {
 531                 printf("ResumeDetected\n");
 532                 write32(reg+OHCI_HC_INT_STATUS, OHCI_INTR_RD);
 533                 /* TODO: figure out what the linux kernel does here... */
 534         }
 535
 536         /* WritebackDoneHead */
 537         if (flags & OHCI_INTR_WDH) {
 538                 printf("WritebackDoneHead\n");
 539                 /* basically the linux irq handler reverse TDs to their urbs
 540                  * and set done_head to null.
 541                  * since we are polling atm, just should do the latter task.
 542                  * however, this won't work for now (i don't know why...)
 543                  * TODO!
 544                  */
 545 #if 0
 546                 sync_before_read(&hcca_oh0, 256);
 547                 hcca_oh0.done_head = 0;
 548                 sync_after_write(&hcca_oh0, 256);
 549 #endif
 550         }
 551
 552         /* TODO: handle any pending URB/ED unlinks... */
 553
 554 #define HC_IS_RUNNING() 1 /* dirty, i know... just a temporary solution */
 555         if (HC_IS_RUNNING()) {
 556                 write32(reg+OHCI_HC_INT_STATUS, flags);
 557                 write32(reg+OHCI_HC_INT_ENABLE, OHCI_INTR_MIE);
 558         }
 559 }
 560
 561 void show_frame_no(u32 reg)
 562 {
 563         if(reg == OHCI0_REG_BASE) {
 564                 sync_before_read(&hcca_oh0, 256);
 565                 printf("***** frame_no: %d *****\n", LE(hcca_oh0.frame_no));
 566         } else if (reg == OHCI1_REG_BASE) {
 567                 sync_before_read(&hcca_oh1, 256);
 568                 printf("***** frame_no: %d *****\n", LE(hcca_oh1.frame_no));
 569         }
 570 }