usb/host/ohci.c

   1 /*
   2        ppcskel - a Free Software replacement for the Nintendo/BroadOn bootloader.
   3        ohci hardware support
   4
   5 Copyright (C) 2009     Bernhard Urban <lewurm@gmx.net>
   6 Copyright (C) 2009     Sebastian Falbesoner <sebastian.falbesoner@gmail.com>
   7
   8 # This code is licensed to you under the terms of the GNU GPL, version 2;
   9 # see file COPYING or http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt
  10 */
  11
  12 #include "../../bootmii_ppc.h"
  13 #include "../../hollywood.h"
  14 #include "../../irq.h"
  15 #include "../../string.h"
  16 #include "../../malloc.h"
  17 #include "ohci.h"
  18 #include "host.h"
  19 #include "../usbspec/usb11spec.h"
  20
  21 static struct ohci_hcca hcca_oh0;
  22
  23 static struct endpoint_descriptor *allocate_endpoint()
  24 {
  25         struct endpoint_descriptor *ep;
  26         ep = (struct endpoint_descriptor *)calloc(sizeof(struct endpoint_descriptor), 16);
  27         ep->flags = OHCI_ENDPOINT_GENERAL_FORMAT;
  28         ep->headp = ep->tailp = ep->nexted = 0;
  29         return ep;
  30 }
  31
  32 static struct general_td *allocate_general_td(size_t bsize)
  33 {
  34         struct general_td *td;
  35         td = (struct general_td *)calloc(sizeof(struct general_td), 16);
  36         td->flags = 0;
  37         td->nexttd = virt_to_phys(td);
  38         if(bsize == 0) {
  39                 td->cbp = td->be = 0;
  40         } else {
  41                 td->cbp = virt_to_phys(malloc(bsize));
  42                 td->be = td->cbp + bsize - 1;
  43         }
  44         return td;
  45 }
  46
  47 static void control_quirk()
  48 {
  49         static struct endpoint_descriptor *ed; /* empty ED */
  50         static struct general_td *td; /* dummy TD */
  51         u32 head;
  52         u32 current;
  53         u32 status;
  54
  55         /*
  56          * One time only.
  57          * Allocate and keep a special empty ED with just a dummy TD.
  58          */
  59         if (!ed) {
  60                 ed = allocate_endpoint();
  61                 if (!ed)
  62                         return;
  63
  64                 td = allocate_general_td(0);
  65                 if (!td) {
  66                         free(ed);
  67                         ed = NULL;
  68                         return;
  69                 }
  70
  71 #define ED_MASK ((u32)~0x0f)
  72                 ed->tailp = ed->headp = virt_to_phys((void*) ((u32)td & ED_MASK));
  73                 ed->flags |= OHCI_ENDPOINT_DIRECTION_OUT;
  74         }
  75
  76         /*
  77          * The OHCI USB host controllers on the Nintendo Wii
  78          * video game console stop working when new TDs are
  79          * added to a scheduled control ED after a transfer has
  80          * has taken place on it.
  81          *
  82          * Before scheduling any new control TD, we make the
  83          * controller happy by always loading a special control ED
  84          * with a single dummy TD and letting the controller attempt
  85          * the transfer.
  86          * The controller won't do anything with it, as the special
  87          * ED has no TDs, but it will keep the controller from failing
  88          * on the next transfer.
  89          */
  90         head = read32(OHCI0_HC_CTRL_HEAD_ED);
  91         if (head) {
  92                 printf("head: 0x%08X\n", head);
  93                 /*
  94                  * Load the special empty ED and tell the controller to
  95                  * process the control list.
  96                  */
  97                 sync_after_write(ed, 64);
  98                 sync_after_write(td, 64);
  99                 write32(OHCI0_HC_CTRL_HEAD_ED, virt_to_phys(ed));
 100
 101                 status = read32(OHCI0_HC_CONTROL);
 102                 set32(OHCI0_HC_CONTROL, OHCI_CTRL_CLE);
 103                 write32(OHCI0_HC_COMMAND_STATUS, OHCI_CLF);
 104
 105                 /* spin until the controller is done with the control list */
 106                 current = read32(OHCI0_HC_CTRL_CURRENT_ED);
 107                 while(!current) {
 108                         udelay(10);
 109                         current = read32(OHCI0_HC_CTRL_CURRENT_ED);
 110                 }
 111
 112                 printf("current: 0x%08X\n", current);
 113
 114                 /* restore the old control head and control settings */
 115                 write32(OHCI0_HC_CONTROL, status);
 116                 write32(OHCI0_HC_CTRL_HEAD_ED, head);
 117         } else {
 118                 printf("nohead!\n");
 119         }
 120 }
 121
 122
 123 static void dbg_op_state()
 124 {
 125         switch (read32(OHCI0_HC_CONTROL) & OHCI_CTRL_HCFS) {
 126                 case OHCI_USB_SUSPEND:
 127                         printf("ohci-- OHCI_USB_SUSPEND\n");
 128                         break;
 129                 case OHCI_USB_RESET:
 130                         printf("ohci-- OHCI_USB_RESET\n");
 131                         break;
 132                 case OHCI_USB_OPER:
 133                         printf("ohci-- OHCI_USB_OPER\n");
 134                         break;
 135                 case OHCI_USB_RESUME:
 136                         printf("ohci-- OHCI_USB_RESUME\n");
 137                         break;
 138         }
 139 }
 140
 141
 142 /**
 143  * Enqueue a transfer descriptor.
 144  */
 145 u8 hcdi_enqueue(usb_transfer_descriptor *td) {
 146         control_quirk();
 147
 148         printf( "===========================\n"
 149                         "===========================\n"
 150                         "done head (vor sync): 0x%08X\n", hcca_oh0.done_head);
 151         sync_before_read(&hcca_oh0, 256);
 152         printf("done head (nach sync): 0x%08X\n", hcca_oh0.done_head);
 153
 154         struct general_td *tmptd = allocate_general_td(td->actlen);
 155         (void) memcpy((void*) phys_to_virt(tmptd->cbp), td->buffer, td->actlen); /* throws dsi exception after some time :X */
 156
 157         tmptd->flags &= ~OHCI_TD_DIRECTION_PID_MASK;
 158         switch(td->pid) {
 159                 case USB_PID_SETUP:
 160                         printf("pid_setup\n");
 161                         tmptd->flags |= OHCI_TD_DIRECTION_PID_SETUP;
 162                         break;
 163                 case USB_PID_OUT:
 164                         printf("pid_out\n");
 165                         tmptd->flags |= OHCI_TD_DIRECTION_PID_OUT;
 166                         break;
 167                 case USB_PID_IN:
 168                         printf("pid_in\n");
 169                         tmptd->flags |= OHCI_TD_DIRECTION_PID_IN;
 170                         break;
 171         }
 172         tmptd->flags |= (td->togl) ? OHCI_TD_TOGGLE_1 : OHCI_TD_TOGGLE_0;
 173
 174         printf("tmptd hexump (before):\n");
 175         hexdump(tmptd, sizeof(struct general_td));
 176         printf("tmptd-cbp hexump (before):\n");
 177         hexdump((void*) phys_to_virt(tmptd->cbp), td->actlen);
 178
 179         sync_after_write((void*) (tmptd->cbp), td->actlen);
 180         sync_after_write(tmptd, sizeof(struct general_td));
 181
 182         struct endpoint_descriptor *dummyconfig = allocate_endpoint();
 183
 184         u32 current2 = read32(OHCI0_HC_CTRL_CURRENT_ED);
 185         printf("current2: 0x%08X\n", current2);
 186
 187 #define ED_MASK2 ~0 /*((u32)~0x0f) */
 188 #define ED_MASK ((u32)~0x0f)
 189         printf("tmpdt & ED_MASK: 0x%08X\n", virt_to_phys((void*) ((u32)tmptd & ED_MASK)));
 190         dummyconfig->tailp = dummyconfig->headp = virt_to_phys((void*) ((u32)tmptd & ED_MASK));
 191
 192         dummyconfig->flags |= OHCI_ENDPOINT_LOW_SPEED |
 193                 OHCI_ENDPOINT_SET_DEVICE_ADDRESS(td->devaddress) |
 194                 OHCI_ENDPOINT_SET_ENDPOINT_NUMBER(td->endpoint) |
 195                 OHCI_ENDPOINT_SET_MAX_PACKET_SIZE(td->maxp);
 196
 197         sync_after_write(dummyconfig, 64);
 198         write32(OHCI0_HC_CTRL_HEAD_ED, virt_to_phys(dummyconfig));
 199
 200         printf("OHCI_CTRL_CLE: 0x%08X\n", read32(OHCI0_HC_CONTROL)&OHCI_CTRL_CLE);
 201         printf("OHCI_CLF: 0x%08X\n", read32(OHCI0_HC_COMMAND_STATUS)&OHCI_CLF);
 202         set32(OHCI0_HC_CONTROL, OHCI_CTRL_CLE);
 203         write32(OHCI0_HC_COMMAND_STATUS, OHCI_CLF);
 204
 205         printf("+++++++++++++++++++++++++++++\n");
 206         /* spin until the controller is done with the control list */
 207         u32 current = read32(OHCI0_HC_CTRL_CURRENT_ED);
 208         printf("current: 0x%08X\n", current);
 209         while(!current) {
 210                 udelay(10);
 211                 current = read32(OHCI0_HC_CTRL_CURRENT_ED);
 212         }
 213
 214         udelay(2000);
 215         udelay(2000);
 216         udelay(2000);
 217         current = read32(OHCI0_HC_CTRL_CURRENT_ED);
 218         printf("current: 0x%08X\n", current);
 219         printf("+++++++++++++++++++++++++++++\n");
 220         udelay(2000);
 221         udelay(2000);
 222         udelay(2000);
 223         udelay(2000);
 224         udelay(2000);
 225         udelay(2000);
 226         udelay(2000);
 227         udelay(2000);
 228
 229         sync_before_read(tmptd, sizeof(struct general_td));
 230         printf("tmptd hexump (after):\n");
 231         hexdump(tmptd, sizeof(struct general_td));
 232
 233         sync_before_read((void*) (tmptd->cbp), td->actlen);
 234         printf("tmptd-cbp hexump (after):\n");
 235         hexdump((void*) phys_to_virt(tmptd->cbp), td->actlen);
 236
 237         printf("done head (vor sync): 0x%08X\n", hcca_oh0.done_head);
 238         sync_before_read(&hcca_oh0, 256);
 239         printf("done head (nach sync): 0x%08X\n", hcca_oh0.done_head);
 240
 241         free(tmptd);
 242         return 0;
 243 }
 244
 245 /**
 246  * Remove an transfer descriptor from transfer queue.
 247  */
 248 u8 hcdi_dequeue(usb_transfer_descriptor *td) {
 249         return 0;
 250 }
 251
 252 void hcdi_init()
 253 {
 254         printf("ohci-- init\n");
 255         dbg_op_state();
 256
 257         /* disable hc interrupts */
 258         set32(OHCI0_HC_INT_DISABLE, OHCI_INTR_MIE);
 259
 260         /* save fmInterval and calculate FSMPS */
 261 #define FSMP(fi) (0x7fff & ((6 * ((fi) - 210)) / 7))
 262 #define FI 0x2edf /* 12000 bits per frame (-1) */
 263         u32 fmint = read32(OHCI0_HC_FM_INTERVAL) & 0x3fff;
 264         if(fmint != FI)
 265                 printf("ohci-- fminterval delta: %d\n", fmint - FI);
 266         fmint |= FSMP (fmint) << 16;
 267
 268         /* enable interrupts of both usb host controllers */
 269         set32(EHCI_CTL, EHCI_CTL_OH0INTE | EHCI_CTL_OH1INTE | 0xe0000);
 270
 271         /* reset HC */
 272         write32(OHCI0_HC_COMMAND_STATUS, OHCI_HCR);
 273
 274         /* wait max. 30us */
 275         u32 ts = 30;
 276         while ((read32(OHCI0_HC_COMMAND_STATUS) & OHCI_HCR) != 0) {
 277                  if(--ts == 0) {
 278                         printf("ohci-- FAILED");
 279                         return;
 280                  }
 281                  udelay(1);
 282         }
 283
 284         /* disable interrupts; 2ms timelimit here!
 285            now we're in the SUSPEND state ... must go OPERATIONAL
 286            within 2msec else HC enters RESUME */
 287
 288         u32 cookie = irq_kill();
 289
 290         /* Tell the controller where the control and bulk lists are
 291          * The lists are empty now. */
 292         write32(OHCI0_HC_CTRL_HEAD_ED, 0);
 293         write32(OHCI0_HC_BULK_HEAD_ED, 0);
 294
 295         /* set hcca adress */
 296         sync_after_write(&hcca_oh0, 256);
 297         write32(OHCI0_HC_HCCA, virt_to_phys(&hcca_oh0));
 298
 299         /* set periodicstart */
 300 #define FIT (1<<31)
 301         u32 fmInterval = read32(OHCI0_HC_FM_INTERVAL) &0x3fff;
 302         u32 fit = read32(OHCI0_HC_FM_INTERVAL) & FIT;
 303
 304         write32(OHCI0_HC_FM_INTERVAL, fmint | (fit ^ FIT));
 305         write32(OHCI0_HC_PERIODIC_START, ((9*fmInterval)/10)&0x3fff);
 306
 307         /* testing bla */
 308         if ((read32(OHCI0_HC_FM_INTERVAL) & 0x3fff0000) == 0 || !read32(OHCI0_HC_PERIODIC_START)) {
 309                 printf("ohci-- w00t, fail!! see ohci-hcd.c:669\n");
 310         }
 311
 312         /* start HC operations */
 313         write32(OHCI0_HC_CONTROL, OHCI_CONTROL_INIT | OHCI_USB_OPER);
 314
 315         /* wake on ConnectStatusChange, matching external hubs */
 316         set32(OHCI0_HC_RH_STATUS, RH_HS_DRWE);
 317
 318         /* Choose the interrupts we care about now, others later on demand */
 319         write32(OHCI0_HC_INT_STATUS, ~0);
 320         write32(OHCI0_HC_INT_ENABLE, OHCI_INTR_INIT);
 321
 322         irq_restore(cookie);
 323
 324         dbg_op_state();
 325 }
 326
 327 void hcdi_irq()
 328 {
 329         /* read interrupt status */
 330         u32 flags = read32(OHCI0_HC_INT_STATUS);
 331
 332         /* when all bits are set to 1 some problem occured */
 333         if (flags == 0xffffffff) {
 334                 printf("ohci-- Houston, we have a serious problem! :(\n");
 335                 return;
 336         }
 337
 338         /* only care about interrupts that are enabled */
 339         flags &= read32(OHCI0_HC_INT_ENABLE);
 340
 341         /* nothing to do? */
 342         if (flags == 0)
 343                 return;
 344
 345         printf("OHCI Interrupt occured: ");
 346         /* UnrecoverableError */
 347         if (flags & OHCI_INTR_UE) {
 348                 printf("UnrecoverableError\n");
 349                 /* TODO: well, I don't know... nothing,
 350                  *       because it won't happen anyway? ;-) */
 351         }
 352
 353         /* RootHubStatusChange */
 354         if (flags & OHCI_INTR_RHSC) {
 355                 printf("RootHubStatusChange\n");
 356                 /* TODO: set some next_statechange variable... */
 357                 write32(OHCI0_HC_INT_STATUS, OHCI_INTR_RD | OHCI_INTR_RHSC);
 358         }
 359         /* ResumeDetected */
 360         else if (flags & OHCI_INTR_RD) {
 361                 printf("ResumeDetected\n");
 362                 write32(OHCI0_HC_INT_STATUS, OHCI_INTR_RD);
 363                 /* TODO: figure out what the linux kernel does here... */
 364         }
 365
 366         /* WritebackDoneHead */
 367         if (flags & OHCI_INTR_WDH) {
 368                 printf("WritebackDoneHead\n");
 369                 /* TODO: figure out what the linux kernel does here... */
 370         }
 371
 372         /* TODO: handle any pending URB/ED unlinks... */
 373
 374 #define HC_IS_RUNNING() 1 /* dirty, i know... just a temporary solution */
 375         if (HC_IS_RUNNING()) {
 376                 write32(OHCI0_HC_INT_STATUS, flags);
 377                 write32(OHCI0_HC_INT_ENABLE, OHCI_INTR_MIE);
 378         }
 379 }
 380