usb/host/ohci.c

   1 /*
   2        ppcskel - a Free Software replacement for the Nintendo/BroadOn bootloader.
   3        ohci hardware support
   4
   5 Copyright (C) 2009     Bernhard Urban <lewurm@gmx.net>
   6 Copyright (C) 2009     Sebastian Falbesoner <sebastian.falbesoner@gmail.com>
   7
   8 # This code is licensed to you under the terms of the GNU GPL, version 2;
   9 # see file COPYING or http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt
  10 */
  11
  12 #include "../../bootmii_ppc.h"
  13 #include "../../hollywood.h"
  14 #include "../../irq.h"
  15 #include "../../string.h"
  16 #include "../../malloc.h"
  17 #include "ohci.h"
  18 #include "host.h"
  19 #include "../usbspec/usb11spec.h"
  20
  21 // macro for accessing u32 variables that need to be in little endian byte order;
  22 // whenever you read or write from an u32 field that the ohci host controller
  23 // will read or write from too, use this macro for access!
  24 #define ACCESS_LE(dword) (u32)( (((dword) & 0xFF000000) >> 24) | \
  25                            (((dword) & 0x00FF0000) >> 8)  | \
  26                            (((dword) & 0x0000FF00) << 8)  | \
  27                            (((dword) & 0x000000FF) << 24) )
  28
  29 static struct ohci_hcca hcca_oh0;
  30
  31 static struct endpoint_descriptor *allocate_endpoint()
  32 {
  33         struct endpoint_descriptor *ep;
  34         //memalign instead of calloc doesn't work here?! WTF
  35         ep = (struct endpoint_descriptor *)memalign(sizeof(struct endpoint_descriptor), 16);
  36         ep->flags = ACCESS_LE(OHCI_ENDPOINT_GENERAL_FORMAT);
  37         ep->headp = ep->tailp = ep->nexted = ACCESS_LE(0);
  38         return ep;
  39 }
  40
  41 static struct general_td *allocate_general_td(size_t bsize)
  42 {
  43         struct general_td *td;
  44         td = (struct general_td *)memalign(sizeof(struct general_td), 16);
  45         td->flags = ACCESS_LE(0);
  46         //td->nexttd = ACCESS_LE(virt_to_phys(td));
  47         td->nexttd = ACCESS_LE(0);
  48         if(bsize == 0) {
  49                 td->cbp = td->be = ACCESS_LE(0);
  50         } else {
  51                 td->cbp = ACCESS_LE(virt_to_phys(memalign(bsize, 16))); //memailgn required here?
  52                 //td->cbp = ACCESS_LE(virt_to_phys(malloc(bsize)));
  53                 td->be = ACCESS_LE(ACCESS_LE(td->cbp) + bsize - 1);
  54         }
  55         return td;
  56 }
  57
  58 static void control_quirk()
  59 {
  60         static struct endpoint_descriptor *ed = 0; /* empty ED */
  61         static struct general_td *td = 0; /* dummy TD */
  62         u32 head;
  63         u32 current;
  64         u32 status;
  65
  66         /*
  67          * One time only.
  68          * Allocate and keep a special empty ED with just a dummy TD.
  69          */
  70         if (!ed) {
  71                 ed = allocate_endpoint();
  72                 if (!ed)
  73                         return;
  74
  75                 td = allocate_general_td(0);
  76                 if (!td) {
  77                         free(ed);
  78                         ed = NULL;
  79                         return;
  80                 }
  81
  82 #define ED_MASK ((u32)~0x0f)
  83                 ed->tailp = ed->headp = ACCESS_LE(virt_to_phys((void*) ((u32)td & ED_MASK)));
  84                 ed->flags |= ACCESS_LE(OHCI_ENDPOINT_DIRECTION_OUT);
  85         }
  86
  87         /*
  88          * The OHCI USB host controllers on the Nintendo Wii
  89          * video game console stop working when new TDs are
  90          * added to a scheduled control ED after a transfer has
  91          * has taken place on it.
  92          *
  93          * Before scheduling any new control TD, we make the
  94          * controller happy by always loading a special control ED
  95          * with a single dummy TD and letting the controller attempt
  96          * the transfer.
  97          * The controller won't do anything with it, as the special
  98          * ED has no TDs, but it will keep the controller from failing
  99          * on the next transfer.
 100          */
 101         head = read32(OHCI0_HC_CTRL_HEAD_ED);
 102         if (head) {
 103                 printf("head: 0x%08X\n", head);
 104                 /*
 105                  * Load the special empty ED and tell the controller to
 106                  * process the control list.
 107                  */
 108                 sync_after_write(ed, 16);
 109                 sync_after_write(td, 16);
 110                 write32(OHCI0_HC_CTRL_HEAD_ED, virt_to_phys(ed));
 111
 112                 status = read32(OHCI0_HC_CONTROL);
 113                 set32(OHCI0_HC_CONTROL, OHCI_CTRL_CLE);
 114                 write32(OHCI0_HC_COMMAND_STATUS, OHCI_CLF);
 115
 116                 /* spin until the controller is done with the control list */
 117                 current = read32(OHCI0_HC_CTRL_CURRENT_ED);
 118                 while(!current) {
 119                         udelay(10);
 120                         current = read32(OHCI0_HC_CTRL_CURRENT_ED);
 121                 }
 122
 123                 printf("current: 0x%08X\n", current);
 124
 125                 /* restore the old control head and control settings */
 126                 write32(OHCI0_HC_CONTROL, status);
 127                 write32(OHCI0_HC_CTRL_HEAD_ED, head);
 128         } else {
 129                 printf("nohead!\n");
 130         }
 131 }
 132
 133
 134 static void dbg_op_state()
 135 {
 136         switch (read32(OHCI0_HC_CONTROL) & OHCI_CTRL_HCFS) {
 137                 case OHCI_USB_SUSPEND:
 138                         printf("ohci-- OHCI_USB_SUSPEND\n");
 139                         break;
 140                 case OHCI_USB_RESET:
 141                         printf("ohci-- OHCI_USB_RESET\n");
 142                         break;
 143                 case OHCI_USB_OPER:
 144                         printf("ohci-- OHCI_USB_OPER\n");
 145                         break;
 146                 case OHCI_USB_RESUME:
 147                         printf("ohci-- OHCI_USB_RESUME\n");
 148                         break;
 149         }
 150 }
 151
 152
 153 /**
 154  * Enqueue a transfer descriptor.
 155  */
 156 u8 first = 0;
 157 u8 hcdi_enqueue(usb_transfer_descriptor *td) {
 158         control_quirk();
 159
 160         printf( "===========================\n"
 161                         "===========================\n");
 162         sync_before_read(&hcca_oh0, 256);
 163         printf("done head (nach sync): 0x%08X\n", ACCESS_LE(hcca_oh0.done_head));
 164         printf("HCCA->frame_no: %d\nhcca->hccapad1: %d\n",
 165                         ((ACCESS_LE(hcca_oh0.frame_no) & 0xffff0000)>>16),
 166                         ACCESS_LE(hcca_oh0.frame_no)&0xffff );
 167         if(hcca_oh0.done_head) printf("WWWWWWWWOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOTTTTTTTTTTTT\n");
 168
 169         struct general_td *tmptd = allocate_general_td(td->actlen);
 170         (void) memcpy((void*) (phys_to_virt(ACCESS_LE(tmptd->cbp))), td->buffer, td->actlen);
 171
 172         tmptd->flags &= ACCESS_LE(~OHCI_TD_DIRECTION_PID_MASK);
 173         switch(td->pid) {
 174                 case USB_PID_SETUP:
 175                         printf("pid_setup\n");
 176                         tmptd->flags |= ACCESS_LE(OHCI_TD_DIRECTION_PID_SETUP);
 177                         break;
 178                 case USB_PID_OUT:
 179                         printf("pid_out\n");
 180                         tmptd->flags |= ACCESS_LE(OHCI_TD_DIRECTION_PID_OUT);
 181                         break;
 182                 case USB_PID_IN:
 183                         printf("pid_in\n");
 184                         tmptd->flags |= ACCESS_LE(OHCI_TD_DIRECTION_PID_IN);
 185                         break;
 186         }
 187         tmptd->flags |= ACCESS_LE((td->togl) ? OHCI_TD_TOGGLE_1 : OHCI_TD_TOGGLE_0);
 188
 189         printf("tmptd hexdump (before) 0x%08X:\n", tmptd);
 190         hexdump(tmptd, sizeof(struct general_td));
 191         printf("tmptd->cbp hexdump (before) 0x%08X:\n", phys_to_virt(ACCESS_LE(tmptd->cbp)));
 192         hexdump((void*) phys_to_virt(ACCESS_LE(tmptd->cbp)), td->actlen);
 193
 194         sync_after_write(tmptd, sizeof(struct general_td));
 195         sync_after_write((void*) phys_to_virt(ACCESS_LE(tmptd->cbp)), td->actlen);
 196
 197         struct endpoint_descriptor *dummyconfig = allocate_endpoint();
 198
 199 #define ED_MASK2 ~0 /*((u32)~0x0f) */
 200 #define ED_MASK ((u32)~0x0f)
 201         /*dummyconfig->tailp =*/ dummyconfig->headp = ACCESS_LE(virt_to_phys((void*) ((u32)tmptd & ED_MASK)));
 202
 203         dummyconfig->flags |= ACCESS_LE(OHCI_ENDPOINT_LOW_SPEED |
 204                 OHCI_ENDPOINT_SET_DEVICE_ADDRESS(td->devaddress) |
 205                 OHCI_ENDPOINT_SET_ENDPOINT_NUMBER(td->endpoint) |
 206                 OHCI_ENDPOINT_SET_MAX_PACKET_SIZE(td->maxp));
 207
 208         printf("dummyconfig hexdump (before) 0x%08X:\n", dummyconfig);
 209         hexdump((void*) dummyconfig, 16);
 210
 211         sync_after_write(dummyconfig, 16);
 212         write32(OHCI0_HC_CTRL_HEAD_ED, virt_to_phys(dummyconfig));
 213
 214         printf("OHCI_CTRL_CLE: 0x%08X || ", read32(OHCI0_HC_CONTROL)&OHCI_CTRL_CLE);
 215         printf("OHCI_CLF: 0x%08X\n", read32(OHCI0_HC_COMMAND_STATUS)&OHCI_CLF);
 216         set32(OHCI0_HC_CONTROL, OHCI_CTRL_CLE);
 217         write32(OHCI0_HC_COMMAND_STATUS, OHCI_CLF);
 218
 219         printf("+++++++++++++++++++++++++++++\n");
 220         /* spin until the controller is done with the control list */
 221         u32 current = read32(OHCI0_HC_CTRL_CURRENT_ED);
 222         printf("current: 0x%08X\n", current);
 223         while(!current) {
 224         //      udelay(1000000);
 225                 udelay(2);
 226                 current = read32(OHCI0_HC_CTRL_CURRENT_ED);
 227         //      printf("OHCI_CTRL_CLE: 0x%08X || ", read32(OHCI0_HC_CONTROL)&OHCI_CTRL_CLE);
 228         //      printf("OHCI_CLF: 0x%08X\n", read32(OHCI0_HC_COMMAND_STATUS)&OHCI_CLF);
 229         }
 230
 231         udelay(20000);
 232         current = read32(OHCI0_HC_CTRL_CURRENT_ED);
 233         printf("current: 0x%08X\n", current);
 234         printf("+++++++++++++++++++++++++++++\n");
 235         udelay(20000);
 236
 237
 238         sync_before_read(tmptd, sizeof(struct general_td));
 239         printf("tmptd hexdump (after) 0x%08X:\n", tmptd);
 240         hexdump(tmptd, sizeof(struct general_td));
 241
 242         sync_before_read((void*) phys_to_virt(ACCESS_LE(tmptd->cbp)), td->actlen);
 243         printf("tmptd->cbp hexdump (after) 0x%08X:\n", phys_to_virt(ACCESS_LE(tmptd->cbp)));
 244         hexdump((void*) phys_to_virt(ACCESS_LE(tmptd->cbp)), td->actlen);
 245
 246         sync_before_read(dummyconfig, 16);
 247         printf("dummyconfig hexdump (after) 0x%08X:\n", dummyconfig);
 248         hexdump((void*) dummyconfig, 16);
 249
 250         sync_before_read(&hcca_oh0, 256);
 251         printf("done head (nach sync): 0x%08X\n", ACCESS_LE(hcca_oh0.done_head));
 252
 253         //should be free'd after taking it from the done queue
 254         //free(tmptd);
 255         return 0;
 256 }
 257
 258 /**
 259  * Remove an transfer descriptor from transfer queue.
 260  */
 261 u8 hcdi_dequeue(usb_transfer_descriptor *td) {
 262         return 0;
 263 }
 264
 265 void hcdi_init()
 266 {
 267         printf("ohci-- init\n");
 268         dbg_op_state();
 269
 270         /* disable hc interrupts */
 271         set32(OHCI0_HC_INT_DISABLE, OHCI_INTR_MIE);
 272
 273         /* save fmInterval and calculate FSMPS */
 274 #define FSMP(fi) (0x7fff & ((6 * ((fi) - 210)) / 7))
 275 #define FI 0x2edf /* 12000 bits per frame (-1) */
 276         u32 fmint = read32(OHCI0_HC_FM_INTERVAL) & 0x3fff;
 277         if(fmint != FI)
 278                 printf("ohci-- fminterval delta: %d\n", fmint - FI);
 279         fmint |= FSMP (fmint) << 16;
 280
 281         /* enable interrupts of both usb host controllers */
 282         set32(EHCI_CTL, EHCI_CTL_OH0INTE | EHCI_CTL_OH1INTE | 0xe0000);
 283
 284         /* reset HC */
 285         write32(OHCI0_HC_COMMAND_STATUS, OHCI_HCR);
 286
 287         /* wait max. 30us */
 288         u32 ts = 30;
 289         while ((read32(OHCI0_HC_COMMAND_STATUS) & OHCI_HCR) != 0) {
 290                  if(--ts == 0) {
 291                         printf("ohci-- FAILED");
 292                         return;
 293                  }
 294                  udelay(1);
 295         }
 296
 297         /* disable interrupts; 2ms timelimit here!
 298            now we're in the SUSPEND state ... must go OPERATIONAL
 299            within 2msec else HC enters RESUME */
 300
 301         u32 cookie = irq_kill();
 302
 303         /* Tell the controller where the control and bulk lists are
 304          * The lists are empty now. */
 305         write32(OHCI0_HC_CTRL_HEAD_ED, 0);
 306         write32(OHCI0_HC_BULK_HEAD_ED, 0);
 307
 308         /* set hcca adress */
 309         sync_after_write(&hcca_oh0, 256);
 310         write32(OHCI0_HC_HCCA, virt_to_phys(&hcca_oh0));
 311
 312         /* set periodicstart */
 313 #define FIT (1<<31)
 314         u32 fmInterval = read32(OHCI0_HC_FM_INTERVAL) &0x3fff;
 315         u32 fit = read32(OHCI0_HC_FM_INTERVAL) & FIT;
 316
 317         write32(OHCI0_HC_FM_INTERVAL, fmint | (fit ^ FIT));
 318         write32(OHCI0_HC_PERIODIC_START, ((9*fmInterval)/10)&0x3fff);
 319
 320         /* testing bla */
 321         if ((read32(OHCI0_HC_FM_INTERVAL) & 0x3fff0000) == 0 || !read32(OHCI0_HC_PERIODIC_START)) {
 322                 printf("ohci-- w00t, fail!! see ohci-hcd.c:669\n");
 323         }
 324
 325         /* start HC operations */
 326         write32(OHCI0_HC_CONTROL, OHCI_CONTROL_INIT | OHCI_USB_OPER);
 327
 328         /* wake on ConnectStatusChange, matching external hubs */
 329         set32(OHCI0_HC_RH_STATUS, RH_HS_DRWE);
 330
 331         /* Choose the interrupts we care about now, others later on demand */
 332         write32(OHCI0_HC_INT_STATUS, ~0);
 333         write32(OHCI0_HC_INT_ENABLE, OHCI_INTR_INIT);
 334
 335         irq_restore(cookie);
 336
 337         dbg_op_state();
 338 }
 339
 340 void hcdi_irq()
 341 {
 342         /* read interrupt status */
 343         u32 flags = read32(OHCI0_HC_INT_STATUS);
 344
 345         /* when all bits are set to 1 some problem occured */
 346         if (flags == 0xffffffff) {
 347                 printf("ohci-- Houston, we have a serious problem! :(\n");
 348                 return;
 349         }
 350
 351         /* only care about interrupts that are enabled */
 352         flags &= read32(OHCI0_HC_INT_ENABLE);
 353
 354         /* nothing to do? */
 355         if (flags == 0) {
 356                 printf("OHCI Interrupt occured: but not for you! WTF?!\n");
 357                 return;
 358         }
 359
 360         printf("OHCI Interrupt occured: ");
 361         /* UnrecoverableError */
 362         if (flags & OHCI_INTR_UE) {
 363                 printf("UnrecoverableError\n");
 364                 /* TODO: well, I don't know... nothing,
 365                  *       because it won't happen anyway? ;-) */
 366         }
 367
 368         /* RootHubStatusChange */
 369         if (flags & OHCI_INTR_RHSC) {
 370                 printf("RootHubStatusChange\n");
 371                 /* TODO: set some next_statechange variable... */
 372                 write32(OHCI0_HC_INT_STATUS, OHCI_INTR_RD | OHCI_INTR_RHSC);
 373         }
 374         /* ResumeDetected */
 375         else if (flags & OHCI_INTR_RD) {
 376                 printf("ResumeDetected\n");
 377                 write32(OHCI0_HC_INT_STATUS, OHCI_INTR_RD);
 378                 /* TODO: figure out what the linux kernel does here... */
 379         }
 380
 381         /* WritebackDoneHead */
 382         if (flags & OHCI_INTR_WDH) {
 383                 printf("WritebackDoneHead\n");
 384                 /* TODO: figure out what the linux kernel does here... */
 385         }
 386
 387         /* TODO: handle any pending URB/ED unlinks... */
 388
 389 #define HC_IS_RUNNING() 1 /* dirty, i know... just a temporary solution */
 390         if (HC_IS_RUNNING()) {
 391                 write32(OHCI0_HC_INT_STATUS, flags);
 392                 write32(OHCI0_HC_INT_ENABLE, OHCI_INTR_MIE);
 393         }
 394 }
 395