usb/host/ohci.c

   1 /*
   2        ppcskel - a Free Software replacement for the Nintendo/BroadOn bootloader.
   3        ohci hardware support
   4
   5 Copyright (C) 2009     Bernhard Urban <lewurm@gmx.net>
   6 Copyright (C) 2009     Sebastian Falbesoner <sebastian.falbesoner@gmail.com>
   7
   8 # This code is licensed to you under the terms of the GNU GPL, version 2;
   9 # see file COPYING or http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt
  10 */
  11
  12 #include "../../bootmii_ppc.h"
  13 #include "../../hollywood.h"
  14 #include "../../irq.h"
  15 #include "../../string.h"
  16 #include "../../malloc.h"
  17 #include "ohci.h"
  18 #include "host.h"
  19 #include "../usbspec/usb11spec.h"
  20
  21 /* activate control_quirk (from MIKE) */
  22 //#define _USE_C_Q
  23
  24 /* macro for accessing u32 variables that need to be in little endian byte order;
  25  *
  26  * whenever you read or write from an u32 field that the ohci host controller
  27  * will read or write from too, use this macro for access!
  28  */
  29 #define LE(dword) (u32)( (((dword) & 0xFF000000) >> 24) | \
  30                            (((dword) & 0x00FF0000) >> 8)  | \
  31                            (((dword) & 0x0000FF00) << 8)  | \
  32                            (((dword) & 0x000000FF) << 24) )
  33
  34 static struct general_td *allocate_general_td();
  35 static void dbg_op_state();
  36 static void configure_ports(u8 from_init);
  37 static void setup_port(u32 reg, u8 from_init);
  38
  39 static struct ohci_hcca hcca_oh0;
  40
  41
  42 #ifdef _USE_C_Q
  43 static struct endpoint_descriptor *allocate_endpoint()
  44 {
  45         struct endpoint_descriptor *ep;
  46         ep = (struct endpoint_descriptor *)memalign(16, sizeof(struct endpoint_descriptor));
  47         memset(ep, 0, sizeof(struct endpoint_descriptor));
  48         ep->flags = LE(OHCI_ENDPOINT_GENERAL_FORMAT);
  49         ep->headp = ep->tailp = ep->nexted = LE(0);
  50         return ep;
  51 }
  52 #endif
  53
  54 static struct general_td *allocate_general_td()
  55 {
  56         struct general_td *td;
  57         td = (struct general_td *)memalign(16, sizeof(struct general_td));
  58         memset(td, 0, sizeof(struct general_td));
  59         td->flags = LE(0);
  60         td->nexttd = LE(0);
  61         td->cbp = td->be = LE(0);
  62         return td;
  63 }
  64
  65 #ifdef _USE_C_Q
  66 static void control_quirk()
  67 {
  68         static struct endpoint_descriptor *ed = 0; /* empty ED */
  69         static struct general_td *td = 0; /* dummy TD */
  70         u32 head;
  71         u32 current;
  72         u32 status;
  73
  74         /*
  75          * One time only.
  76          * Allocate and keep a special empty ED with just a dummy TD.
  77          */
  78         if (!ed) {
  79                 ed = allocate_endpoint();
  80                 if (!ed)
  81                         return;
  82
  83                 td = allocate_general_td(0);
  84                 if (!td) {
  85                         free(ed);
  86                         ed = NULL;
  87                         return;
  88                 }
  89
  90                 ed->tailp = ed->headp = LE(virt_to_phys((void*) ((u32)td & OHCI_ENDPOINT_HEAD_MASK)));
  91                 ed->flags |= LE(OHCI_ENDPOINT_DIRECTION_OUT);
  92         }
  93
  94         /*
  95          * The OHCI USB host controllers on the Nintendo Wii
  96          * video game console stop working when new TDs are
  97          * added to a scheduled control ED after a transfer has
  98          * has taken place on it.
  99          *
 100          * Before scheduling any new control TD, we make the
 101          * controller happy by always loading a special control ED
 102          * with a single dummy TD and letting the controller attempt
 103          * the transfer.
 104          * The controller won't do anything with it, as the special
 105          * ED has no TDs, but it will keep the controller from failing
 106          * on the next transfer.
 107          */
 108         head = read32(OHCI0_HC_CTRL_HEAD_ED);
 109         if (head) {
 110                 printf("head: 0x%08X\n", head);
 111                 /*
 112                  * Load the special empty ED and tell the controller to
 113                  * process the control list.
 114                  */
 115                 sync_after_write(ed, 16);
 116                 sync_after_write(td, 16);
 117                 write32(OHCI0_HC_CTRL_HEAD_ED, virt_to_phys(ed));
 118
 119                 status = read32(OHCI0_HC_CONTROL);
 120                 set32(OHCI0_HC_CONTROL, OHCI_CTRL_CLE);
 121                 write32(OHCI0_HC_COMMAND_STATUS, OHCI_CLF);
 122
 123                 /* spin until the controller is done with the control list */
 124                 current = read32(OHCI0_HC_CTRL_CURRENT_ED);
 125                 while(!current) {
 126                         udelay(10);
 127                         current = read32(OHCI0_HC_CTRL_CURRENT_ED);
 128                 }
 129
 130                 printf("current: 0x%08X\n", current);
 131
 132                 /* restore the old control head and control settings */
 133                 write32(OHCI0_HC_CONTROL, status);
 134                 write32(OHCI0_HC_CTRL_HEAD_ED, head);
 135         } else {
 136                 printf("nohead!\n");
 137         }
 138 }
 139 #endif
 140
 141
 142 static void dbg_op_state()
 143 {
 144         switch (read32(OHCI0_HC_CONTROL) & OHCI_CTRL_HCFS) {
 145                 case OHCI_USB_SUSPEND:
 146                         printf("ohci-- OHCI_USB_SUSPEND\n");
 147                         break;
 148                 case OHCI_USB_RESET:
 149                         printf("ohci-- OHCI_USB_RESET\n");
 150                         break;
 151                 case OHCI_USB_OPER:
 152                         printf("ohci-- OHCI_USB_OPER\n");
 153                         break;
 154                 case OHCI_USB_RESUME:
 155                         printf("ohci-- OHCI_USB_RESUME\n");
 156                         break;
 157         }
 158 }
 159
 160 static void dbg_td_flag(u32 flag)
 161 {
 162         printf("**************** dbg_td_flag: 0x%08X ***************\n", flag);
 163         printf("CC: %X\tshould be 0, see page 32 (ohci spec)\n", (flag>>28)&0xf);
 164         printf("EC: %X\tsee page 20 (ohci spec)\n", (flag>>26)&3);
 165         printf(" T: %X\n", (flag>>24)&3);
 166         printf("DI: %X\n", (flag>>21)&7);
 167         printf("DP: %X\n", (flag>>19)&3);
 168         printf(" R: %X\n", (flag>>18)&1);
 169         printf("********************************************************\n");
 170 }
 171
 172 static void general_td_fill(struct general_td *dest, const usb_transfer_descriptor *src)
 173 {
 174         if(src->actlen) {
 175                 dest->cbp = LE(virt_to_phys(src->buffer));
 176                 dest->be = LE(LE(dest->cbp) + src->actlen - 1);
 177                 /* save virtual address here */
 178                 dest->bufaddr = (u32) src->buffer;
 179         }
 180         else {
 181                 dest->cbp = dest->be = LE(0);
 182                 dest->bufaddr = 0;
 183         }
 184
 185         dest->buflen = src->actlen;
 186
 187         dest->flags &= LE(~OHCI_TD_DIRECTION_PID_MASK);
 188         switch(src->pid) {
 189                 case USB_PID_SETUP:
 190                         printf("pid_setup\n");
 191                         dest->flags |= LE(OHCI_TD_DIRECTION_PID_SETUP);
 192                         dest->flags |= LE(OHCI_TD_TOGGLE_0);
 193                         dest->flags |= LE(OHCI_TD_BUFFER_ROUNDING);
 194                         break;
 195                 case USB_PID_OUT:
 196                         printf("pid_out\n");
 197                         dest->flags |= LE(OHCI_TD_DIRECTION_PID_OUT);
 198                         dest->flags |= LE(OHCI_TD_BUFFER_ROUNDING);
 199
 200                         /*
 201                          * TODO: just temporary solution! (consider it with len?)
 202                          * there can be also regular PID_OUT pakets
 203                          */
 204                         dest->flags |= LE(OHCI_TD_TOGGLE_1);
 205                         break;
 206                 case USB_PID_IN:
 207                         printf("pid_in\n");
 208                         dest->flags |= LE(OHCI_TD_DIRECTION_PID_IN);
 209                         if(src->maxp > src->actlen) {
 210                                 dest->flags |= LE(OHCI_TD_BUFFER_ROUNDING);
 211                                 printf("round buffer!\n");
 212                         }
 213                         /*
 214                          * let the endpoint do the togglestuff!
 215                          * TODO: just temporary solution!
 216                          * there can be also inregular PID_IN pakets (@Status Stage)
 217                          */
 218                         dest->flags |= LE(OHCI_TD_TOGGLE_CARRY);
 219                         break;
 220         }
 221         dest->flags |= LE(OHCI_TD_SET_DELAY_INTERRUPT(7));
 222 }
 223
 224 #ifdef _DU_OHCI_F
 225 static void dump_address(void *addr, u32 size, const char* str)
 226 {
 227         printf("%s hexdump (%d) @ 0x%08X:\n", str, size, addr);
 228         hexdump(addr, size);
 229 }
 230 #endif
 231
 232 static struct endpoint_descriptor _edhead;
 233 struct endpoint_descriptor *edhead = 0;
 234 void hcdi_fire()
 235 {
 236 #ifdef _DU_OHCI_F
 237         printf("<^>  <^>  <^> hcdi_fire(start)\n");
 238 #endif
 239
 240         if(edhead == 0)
 241                 return;
 242
 243 #ifdef _USE_C_Q
 244         required? YES! :O ... erm... or no? :/ ... in fact I have no idea
 245         control_quirk();
 246 #endif
 247
 248         write32(OHCI0_HC_CTRL_HEAD_ED, virt_to_phys(edhead));
 249
 250         /* sync it all */
 251         sync_after_write(edhead, sizeof(struct endpoint_descriptor));
 252 #ifdef _DU_OHCI_F
 253         dump_address(edhead, sizeof(struct endpoint_descriptor), "edhead(before)");
 254 #endif
 255
 256         struct general_td *x = phys_to_virt(LE(edhead->headp) & OHCI_ENDPOINT_HEAD_MASK);
 257         while(virt_to_phys(x)) {
 258                 sync_after_write(x, sizeof(struct general_td));
 259 #ifdef _DU_OHCI_F
 260                 dump_address(x, sizeof(struct general_td), "x(before)");
 261 #endif
 262
 263                 if(x->buflen > 0) {
 264                         sync_after_write((void*) phys_to_virt(LE(x->cbp)), x->buflen);
 265 #ifdef _DU_OHCI_F
 266                         dump_address((void*) phys_to_virt(LE(x->cbp)), x->buflen, "x->cbp(before)");
 267 #endif
 268                 }
 269                 x = phys_to_virt(LE(x->nexttd));
 270         }
 271
 272         /* trigger control list */
 273         set32(OHCI0_HC_CONTROL, OHCI_CTRL_CLE);
 274         write32(OHCI0_HC_COMMAND_STATUS, OHCI_CLF);
 275
 276         struct general_td *n=0, *prev = 0, *next = 0;
 277         /* poll until edhead->headp is null */
 278         do {
 279                 sync_before_read(edhead, sizeof(struct endpoint_descriptor));
 280 #ifdef _DU_OHCI_F
 281                 printf("edhead->headp: 0x%08X\n", LE(edhead->headp));
 282                 udelay(10000);
 283 #endif
 284
 285                 /* if halted, debug output plz. will break the transfer */
 286                 if((LE(edhead->headp) & OHCI_ENDPOINT_HALTED)) {
 287                         n = phys_to_virt(LE(edhead->headp)&~0xf);
 288                         prev = phys_to_virt((u32)prev);
 289 #ifdef _DU_OHCI_F
 290                         printf("halted!\n");
 291 #endif
 292
 293                         sync_before_read((void*) n, sizeof(struct general_td));
 294 #ifdef _DU_OHCI_F
 295                         printf("n: 0x%08X\n", n);
 296                         dump_address(n, sizeof(struct general_td), "n(after)");
 297 #endif
 298                         if(n->buflen > 0) {
 299                                 sync_before_read((void*) n->bufaddr, n->buflen);
 300 #ifdef _DU_OHCI_F
 301                                 dump_address((void*) n->bufaddr, n->buflen, "n->bufaddr(after)");
 302 #endif
 303                         }
 304                         dbg_td_flag(LE(n->flags));
 305
 306                         sync_before_read((void*) prev, sizeof(struct general_td));
 307 #ifdef _DU_OHCI_F
 308                         printf("prev: 0x%08X\n", prev);
 309                         dump_address(prev, sizeof(struct general_td), "prev(after)");
 310 #endif
 311                         if(prev->buflen >0) {
 312                                 sync_before_read((void*) prev->bufaddr, prev->buflen);
 313 #ifdef _DU_OHCI_F
 314                                 dump_address((void*) prev->bufaddr, prev->buflen, "prev->bufaddr(after)");
 315 #endif
 316                         }
 317 #ifdef _DU_OHCI_F
 318                         dbg_td_flag(LE(prev->flags));
 319                         printf("halted end!\n");
 320 #endif
 321                         return;
 322                 }
 323                 prev = (struct general_td*) (LE(edhead->headp)&~0xf);
 324         } while(LE(edhead->headp)&~0xf);
 325
 326         n = phys_to_virt(read32(OHCI0_HC_DONE_HEAD) & ~1);
 327 #ifdef _DU_OHCI_F
 328         printf("hc_done_head: 0x%08X\n", read32(OHCI0_HC_DONE_HEAD));
 329 #endif
 330
 331         prev = 0; next = 0;
 332         /* reverse done queue */
 333         while(virt_to_phys(n) && edhead->tdcount) {
 334                 sync_before_read((void*) n, sizeof(struct general_td));
 335 #ifdef _DU_OHCI_F
 336                 printf("n: 0x%08X\n", n);
 337                 printf("next: 0x%08X\n", next);
 338                 printf("prev: 0x%08X\n", prev);
 339 #endif
 340
 341                 next = n;
 342                 n = (struct general_td*) phys_to_virt(LE(n->nexttd));
 343                 next->nexttd = (u32) prev;
 344                 prev = next;
 345
 346                 edhead->tdcount--;
 347         }
 348
 349         n = next;
 350         prev = 0;
 351         while(virt_to_phys(n)) {
 352 #ifdef _DU_OHCI_F
 353                 dump_address(n, sizeof(struct general_td), "n(after)");
 354 #endif
 355                 if(n->buflen > 0) {
 356                         sync_before_read((void*) n->bufaddr, n->buflen);
 357 #ifdef _DU_OHCI_F
 358                         dump_address((void*) n->bufaddr, n->buflen, "n->bufaddr(after)");
 359 #endif
 360                 }
 361 #ifdef _DU_OHCI_F
 362                 dbg_td_flag(LE(n->flags));
 363 #endif
 364                 prev = n;
 365                 n = (struct general_td*) n->nexttd;
 366                 free(prev);
 367         }
 368
 369         hcca_oh0.done_head = 0;
 370         sync_after_write(&hcca_oh0, sizeof(hcca_oh0));
 371
 372         write32(OHCI0_HC_CONTROL, read32(OHCI0_HC_CONTROL)&~OHCI_CTRL_CLE);
 373
 374         edhead = 0;
 375
 376 #ifdef _DU_OHCI_F
 377         printf("<^>  <^>  <^> hcdi_fire(end)\n");
 378 #endif
 379 }
 380
 381 /**
 382  * Enqueue a transfer descriptor.
 383  */
 384 u8 hcdi_enqueue(const usb_transfer_descriptor *td) {
 385 #ifdef _DU_OHCI_Q
 386         printf("*()*()*()*()*()*()*() hcdi_enqueue(start)\n");
 387 #endif
 388         if(!edhead) {
 389                 edhead = &_edhead;
 390                 memset(edhead, 0, sizeof(struct endpoint_descriptor));
 391                 edhead->flags = LE(OHCI_ENDPOINT_GENERAL_FORMAT);
 392                 edhead->headp = edhead->tailp = edhead->nexted = LE(0);
 393                 edhead->flags |= LE(OHCI_ENDPOINT_LOW_SPEED |
 394                                 OHCI_ENDPOINT_SET_DEVICE_ADDRESS(td->devaddress) |
 395                                 OHCI_ENDPOINT_SET_ENDPOINT_NUMBER(td->endpoint) |
 396                                 OHCI_ENDPOINT_SET_MAX_PACKET_SIZE(td->maxp));
 397                 edhead->tdcount = 0;
 398         }
 399
 400         struct general_td *tdhw = allocate_general_td();
 401         general_td_fill(tdhw, td);
 402         edhead->tdcount ++;
 403
 404         if(!edhead->headp) {
 405                 /* first transfer */
 406                 edhead->headp = LE(virt_to_phys((void*) ((u32)tdhw & OHCI_ENDPOINT_HEAD_MASK)));
 407         }
 408         else {
 409                 /* headp in endpoint already exists
 410                  * => go to list end
 411                  */
 412                 struct general_td *n = (struct general_td*) phys_to_virt(LE(edhead->headp) & OHCI_ENDPOINT_HEAD_MASK);
 413                 while(LE(n->nexttd)) {
 414                         n = phys_to_virt(LE(n->nexttd));
 415                 }
 416                 n->nexttd = LE(virt_to_phys((void*) ((u32)tdhw & OHCI_ENDPOINT_HEAD_MASK)));
 417 #ifdef _DU_OHCI_Q
 418                 printf("n: 0x%08X\n", n);
 419                 printf("n->nexttd: 0x%08X\n", phys_to_virt(LE(n->nexttd)));
 420 #endif
 421         }
 422
 423 #ifdef _DU_OHCI_Q
 424         printf("*()*()*()*()*()*()*() hcdi_enqueue(end)\n");
 425 #endif
 426         return 0;
 427 }
 428
 429
 430 /**
 431  * Remove an transfer descriptor from transfer queue.
 432  */
 433 u8 hcdi_dequeue(usb_transfer_descriptor *td) {
 434         return 0;
 435 }
 436
 437 void hcdi_init()
 438 {
 439         printf("ohci-- init\n");
 440         dbg_op_state();
 441
 442         /* disable hc interrupts */
 443         set32(OHCI0_HC_INT_DISABLE, OHCI_INTR_MIE);
 444
 445         /* save fmInterval and calculate FSMPS */
 446 #define FSMP(fi) (0x7fff & ((6 * ((fi) - 210)) / 7))
 447 #define FI 0x2edf /* 12000 bits per frame (-1) */
 448         u32 fmint = read32(OHCI0_HC_FM_INTERVAL) & 0x3fff;
 449         if(fmint != FI)
 450                 printf("ohci-- fminterval delta: %d\n", fmint - FI);
 451         fmint |= FSMP (fmint) << 16;
 452
 453         /* enable interrupts of both usb host controllers */
 454         set32(EHCI_CTL, EHCI_CTL_OH0INTE | EHCI_CTL_OH1INTE | 0xe0000);
 455
 456         /* reset HC */
 457         write32(OHCI0_HC_COMMAND_STATUS, OHCI_HCR);
 458
 459         /* wait max. 30us */
 460         u32 ts = 30;
 461         while ((read32(OHCI0_HC_COMMAND_STATUS) & OHCI_HCR) != 0) {
 462                  if(--ts == 0) {
 463                         printf("ohci-- FAILED");
 464                         return;
 465                  }
 466                  udelay(1);
 467         }
 468
 469         /* disable interrupts; 2ms timelimit here!
 470            now we're in the SUSPEND state ... must go OPERATIONAL
 471            within 2msec else HC enters RESUME */
 472
 473         u32 cookie = irq_kill();
 474
 475         /* Tell the controller where the control and bulk lists are
 476          * The lists are empty now. */
 477         write32(OHCI0_HC_CTRL_HEAD_ED, 0);
 478         write32(OHCI0_HC_BULK_HEAD_ED, 0);
 479
 480         /* set hcca adress */
 481         sync_after_write(&hcca_oh0, 256);
 482         write32(OHCI0_HC_HCCA, virt_to_phys(&hcca_oh0));
 483
 484         /* set periodicstart */
 485 #define FIT (1<<31)
 486         u32 fmInterval = read32(OHCI0_HC_FM_INTERVAL) &0x3fff;
 487         u32 fit = read32(OHCI0_HC_FM_INTERVAL) & FIT;
 488
 489         write32(OHCI0_HC_FM_INTERVAL, fmint | (fit ^ FIT));
 490         write32(OHCI0_HC_PERIODIC_START, ((9*fmInterval)/10)&0x3fff);
 491
 492         /* testing bla */
 493         if ((read32(OHCI0_HC_FM_INTERVAL) & 0x3fff0000) == 0 || !read32(OHCI0_HC_PERIODIC_START)) {
 494                 printf("ohci-- w00t, fail!! see ohci-hcd.c:669\n");
 495         }
 496
 497         /* start HC operations */
 498         write32(OHCI0_HC_CONTROL, OHCI_CONTROL_INIT | OHCI_USB_OPER);
 499
 500         /* wake on ConnectStatusChange, matching external hubs */
 501         write32(OHCI0_HC_RH_STATUS, /*RH_HS_DRWE |*/ RH_HS_LPSC);
 502
 503         /* Choose the interrupts we care about now, others later on demand */
 504         write32(OHCI0_HC_INT_STATUS, ~0);
 505         write32(OHCI0_HC_INT_ENABLE, OHCI_INTR_INIT);
 506
 507         //wtf?
 508         wait_ms ((read32(OHCI0_HC_RH_DESCRIPTOR_A) >> 23) & 0x1fe);
 509
 510         configure_ports((u8)1);
 511         irq_restore(cookie);
 512
 513         dbg_op_state();
 514 }
 515
 516 static void configure_ports(u8 from_init)
 517 {
 518 #ifdef _DU_OHCI_RH
 519         printf("OHCI0_HC_RH_DESCRIPTOR_A:\t0x%08X\n", read32(OHCI0_HC_RH_DESCRIPTOR_A));
 520         printf("OHCI0_HC_RH_DESCRIPTOR_B:\t0x%08X\n", read32(OHCI0_HC_RH_DESCRIPTOR_B));
 521         printf("OHCI0_HC_RH_STATUS:\t\t0x%08X\n", read32(OHCI0_HC_RH_STATUS));
 522         printf("OHCI0_HC_RH_PORT_STATUS_1:\t0x%08X\n", read32(OHCI0_HC_RH_PORT_STATUS_1));
 523         printf("OHCI0_HC_RH_PORT_STATUS_2:\t0x%08X\n", read32(OHCI0_HC_RH_PORT_STATUS_2));
 524 #endif
 525
 526         setup_port(OHCI0_HC_RH_PORT_STATUS_1, from_init);
 527         setup_port(OHCI0_HC_RH_PORT_STATUS_2, from_init);
 528 #ifdef _DU_OHCI_RH
 529         printf("configure_ports done\n");
 530 #endif
 531 }
 532
 533 static void setup_port(u32 reg, u8 from_init)
 534 {
 535         u32 port = read32(reg);
 536         if((port & RH_PS_CCS) && ((port & RH_PS_CSC) || from_init)) {
 537                 write32(reg, RH_PS_CSC);
 538
 539                 wait_ms(120);
 540
 541                 /* clear CSC flag, set PES and start port reset (PRS) */
 542                 write32(reg, RH_PS_PES);
 543                 while(!(read32(reg) & RH_PS_PES)) {
 544 #ifdef _DU_OHCI_RH
 545                         printf("fu\n");
 546 #endif
 547                         return;
 548                 }
 549
 550                 write32(reg, RH_PS_PRS);
 551
 552                 /* spin until port reset is complete */
 553                 while(!(read32(reg) & RH_PS_PRSC)); // hint: it may stuck here
 554 #ifdef _DU_OHCI_RH
 555                 printf("loop done\n");
 556 #endif
 557
 558                 (void) usb_add_device();
 559         }
 560 }
 561
 562 void hcdi_irq()
 563 {
 564         /* read interrupt status */
 565         u32 flags = read32(OHCI0_HC_INT_STATUS);
 566
 567         /* when all bits are set to 1 some problem occured */
 568         if (flags == 0xffffffff) {
 569                 printf("ohci-- Houston, we have a serious problem! :(\n");
 570                 return;
 571         }
 572
 573         /* only care about interrupts that are enabled */
 574         flags &= read32(OHCI0_HC_INT_ENABLE);
 575
 576         /* nothing to do? */
 577         if (flags == 0) {
 578                 printf("OHCI Interrupt occured: but not for you! WTF?!\n");
 579                 return;
 580         }
 581
 582         printf("OHCI Interrupt occured: ");
 583         /* UnrecoverableError */
 584         if (flags & OHCI_INTR_UE) {
 585                 printf("UnrecoverableError\n");
 586                 /* TODO: well, I don't know... nothing,
 587                  *       because it won't happen anyway? ;-) */
 588         }
 589
 590         /* RootHubStatusChange */
 591         if (flags & OHCI_INTR_RHSC) {
 592                 printf("RootHubStatusChange\n");
 593                 /* TODO: set some next_statechange variable... */
 594                 configure_ports(0);
 595                 write32(OHCI0_HC_INT_STATUS, OHCI_INTR_RD | OHCI_INTR_RHSC);
 596         }
 597         /* ResumeDetected */
 598         else if (flags & OHCI_INTR_RD) {
 599                 printf("ResumeDetected\n");
 600                 write32(OHCI0_HC_INT_STATUS, OHCI_INTR_RD);
 601                 /* TODO: figure out what the linux kernel does here... */
 602         }
 603
 604         /* WritebackDoneHead */
 605         if (flags & OHCI_INTR_WDH) {
 606                 printf("WritebackDoneHead\n");
 607                 /* basically the linux irq handler reverse TDs to their urbs
 608                  * and set done_head to null.
 609                  * since we are polling atm, just should do the latter task.
 610                  * however, this won't work for now (i don't know why...)
 611                  * TODO!
 612                  */
 613 #if 0
 614                 sync_before_read(&hcca_oh0, 256);
 615                 hcca_oh0.done_head = 0;
 616                 sync_after_write(&hcca_oh0, 256);
 617 #endif
 618         }
 619
 620         /* TODO: handle any pending URB/ED unlinks... */
 621
 622 #define HC_IS_RUNNING() 1 /* dirty, i know... just a temporary solution */
 623         if (HC_IS_RUNNING()) {
 624                 write32(OHCI0_HC_INT_STATUS, flags);
 625                 write32(OHCI0_HC_INT_ENABLE, OHCI_INTR_MIE);
 626         }
 627 }
 628
 629 void show_frame_no()
 630 {
 631         sync_before_read(&hcca_oh0, 256);
 632         printf("***** frame_no: %d *****\n", LE(hcca_oh0.frame_no));
 633 }