*/
arg_offsets [0] = 0;
- arg_offsets [1] = SIZEOF_REGISTER;
- arg_offsets [2] = SIZEOF_REGISTER * 2;
- arg_offsets [3] = SIZEOF_REGISTER * 3;
- regs_offset = SIZEOF_REGISTER * 4;
+ arg_offsets [1] = sizeof(mgreg_t);
+ arg_offsets [2] = sizeof(mgreg_t) * 2;
+ arg_offsets [3] = sizeof(mgreg_t) * 3;
+ regs_offset = sizeof(mgreg_t) * 4;
/* Save registers */
for (i = 0; i < AMD64_NREG; ++i)
if (i != AMD64_RSP)
- amd64_mov_membase_reg (code, AMD64_RSP, regs_offset + (i * SIZEOF_REGISTER), i, SIZEOF_REGISTER);
+ amd64_mov_membase_reg (code, AMD64_RSP, regs_offset + (i * sizeof(mgreg_t)), i, sizeof(mgreg_t));
/* Save RSP */
- amd64_lea_membase (code, AMD64_RAX, AMD64_RSP, stack_size + SIZEOF_REGISTER);
- amd64_mov_membase_reg (code, AMD64_RSP, regs_offset + (AMD64_RSP * SIZEOF_REGISTER), X86_EAX, SIZEOF_REGISTER);
+ amd64_lea_membase (code, AMD64_RAX, AMD64_RSP, stack_size + sizeof(mgreg_t));
+ amd64_mov_membase_reg (code, AMD64_RSP, regs_offset + (AMD64_RSP * sizeof(mgreg_t)), X86_EAX, sizeof(mgreg_t));
/* Set arg1 == regs */
amd64_lea_membase (code, AMD64_RAX, AMD64_RSP, regs_offset);
- amd64_mov_membase_reg (code, AMD64_RSP, arg_offsets [0], AMD64_RAX, SIZEOF_REGISTER);
+ amd64_mov_membase_reg (code, AMD64_RSP, arg_offsets [0], AMD64_RAX, sizeof(mgreg_t));
/* Set arg2 == eip */
if (llvm_abs)
amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
else
- amd64_mov_reg_membase (code, AMD64_RAX, AMD64_RSP, stack_size, SIZEOF_REGISTER);
- amd64_mov_membase_reg (code, AMD64_RSP, arg_offsets [1], AMD64_RAX, SIZEOF_REGISTER);
+ amd64_mov_reg_membase (code, AMD64_RAX, AMD64_RSP, stack_size, sizeof(mgreg_t));
+ amd64_mov_membase_reg (code, AMD64_RSP, arg_offsets [1], AMD64_RAX, sizeof(mgreg_t));
/* Set arg3 == exc/ex_token_index */
if (resume_unwind)
- amd64_mov_membase_imm (code, AMD64_RSP, arg_offsets [2], 0, SIZEOF_REGISTER);
+ amd64_mov_membase_imm (code, AMD64_RSP, arg_offsets [2], 0, sizeof(mgreg_t));
else
- amd64_mov_membase_reg (code, AMD64_RSP, arg_offsets [2], AMD64_ARG_REG1, SIZEOF_REGISTER);
+ amd64_mov_membase_reg (code, AMD64_RSP, arg_offsets [2], AMD64_ARG_REG1, sizeof(mgreg_t));
/* Set arg4 == rethrow/pc offset */
if (resume_unwind) {
- amd64_mov_membase_imm (code, AMD64_RSP, arg_offsets [3], 0, SIZEOF_REGISTER);
+ amd64_mov_membase_imm (code, AMD64_RSP, arg_offsets [3], 0, sizeof(mgreg_t));
} else if (corlib) {
- amd64_mov_membase_reg (code, AMD64_RSP, arg_offsets [3], AMD64_ARG_REG2, SIZEOF_REGISTER);
+ amd64_mov_membase_reg (code, AMD64_RSP, arg_offsets [3], AMD64_ARG_REG2, sizeof(mgreg_t));
if (llvm_abs)
/*
* The caller is LLVM code which passes the absolute address not a pc offset,
*/
amd64_neg_membase (code, AMD64_RSP, arg_offsets [3]);
} else {
- amd64_mov_membase_imm (code, AMD64_RSP, arg_offsets [3], rethrow, SIZEOF_REGISTER);
+ amd64_mov_membase_imm (code, AMD64_RSP, arg_offsets [3], rethrow, sizeof(mgreg_t));
}
if (aot) {
* The rsp field is set just before the call which transitioned to native
* code. Obtain the rip from the stack.
*/
- rip = *(guint64*)((*lmf)->rsp - SIZEOF_REGISTER);
+ rip = *(guint64*)((*lmf)->rsp - sizeof(mgreg_t));
}
ji = mini_jit_info_table_find (domain, (gpointer)rip, NULL);
ainfo->storage = ArgOnStack;
/* Since the same stack slot size is used for all arg */
/* types, it needs to be big enough to hold them all */
- (*stack_size) += SIZEOF_REGISTER;
+ (*stack_size) += sizeof(mgreg_t);
}
else {
ainfo->storage = ArgInIReg;
ainfo->storage = ArgOnStack;
/* Since the same stack slot size is used for both float */
/* types, it needs to be big enough to hold them both */
- (*stack_size) += SIZEOF_REGISTER;
+ (*stack_size) += sizeof(mgreg_t);
}
else {
/* A double register */
if (sig->pinvoke)
*stack_size += ALIGN_TO (info->native_size, 8);
else
- *stack_size += nquads * SIZEOF_REGISTER;
+ *stack_size += nquads * sizeof(mgreg_t);
ainfo->storage = ArgOnStack;
}
}
/* Reserve space for caller saved registers */
for (i = 0; i < AMD64_NREG; ++i)
if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
- offset += SIZEOF_REGISTER;
+ offset += sizeof(mgreg_t);
}
}
ins->opcode = OP_REGOFFSET;
ins->inst_basereg = cfg->frame_reg;
/* These arguments are saved to the stack in the prolog */
- offset = ALIGN_TO (offset, SIZEOF_REGISTER);
+ offset = ALIGN_TO (offset, sizeof(mgreg_t));
if (cfg->arch.omit_fp) {
ins->inst_offset = offset;
- offset += (ainfo->storage == ArgValuetypeInReg) ? 2 * SIZEOF_REGISTER : SIZEOF_REGISTER;
+ offset += (ainfo->storage == ArgValuetypeInReg) ? 2 * sizeof(mgreg_t) : sizeof(mgreg_t);
} else {
- offset += (ainfo->storage == ArgValuetypeInReg) ? 2 * SIZEOF_REGISTER : SIZEOF_REGISTER;
+ offset += (ainfo->storage == ArgValuetypeInReg) ? 2 * sizeof(mgreg_t) : sizeof(mgreg_t);
ins->inst_offset = - offset;
}
break;
ins->opcode = OP_REGOFFSET;
ins->inst_basereg = cfg->frame_reg;
/* These arguments are saved to the stack in the prolog */
- offset = ALIGN_TO (offset, SIZEOF_REGISTER);
+ offset = ALIGN_TO (offset, sizeof(mgreg_t));
if (cfg->arch.omit_fp) {
ins->inst_offset = offset;
- offset += (ainfo->storage == ArgValuetypeInReg) ? 2 * SIZEOF_REGISTER : SIZEOF_REGISTER;
+ offset += (ainfo->storage == ArgValuetypeInReg) ? 2 * sizeof(mgreg_t) : sizeof(mgreg_t);
// Arguments are yet supported by the stack map creation code
//cfg->locals_max_stack_offset = MAX (cfg->locals_max_stack_offset, offset);
} else {
- offset += (ainfo->storage == ArgValuetypeInReg) ? 2 * SIZEOF_REGISTER : SIZEOF_REGISTER;
+ offset += (ainfo->storage == ArgValuetypeInReg) ? 2 * sizeof(mgreg_t) : sizeof(mgreg_t);
ins->inst_offset = - offset;
//cfg->locals_min_stack_offset = MIN (cfg->locals_min_stack_offset, offset);
}
MONO_INST_NEW (cfg, load, arg_storage_to_load_membase (ainfo->pair_storage [part]));
load->inst_basereg = src->dreg;
- load->inst_offset = part * SIZEOF_REGISTER;
+ load->inst_offset = part * sizeof(mgreg_t);
switch (ainfo->pair_storage [part]) {
case ArgInIReg:
/* Load the destination address */
g_assert (loc->opcode == OP_REGOFFSET);
- amd64_mov_reg_membase (code, AMD64_RCX, loc->inst_basereg, loc->inst_offset, SIZEOF_VOID_P);
+ amd64_mov_reg_membase (code, AMD64_RCX, loc->inst_basereg, loc->inst_offset, sizeof(gpointer));
for (quad = 0; quad < 2; quad ++) {
switch (cinfo->ret.pair_storage [quad]) {
case ArgInIReg:
- amd64_mov_membase_reg (code, AMD64_RCX, (quad * SIZEOF_REGISTER), cinfo->ret.pair_regs [quad], SIZEOF_REGISTER);
+ amd64_mov_membase_reg (code, AMD64_RCX, (quad * sizeof(mgreg_t)), cinfo->ret.pair_regs [quad], sizeof(mgreg_t));
break;
case ArgInFloatSSEReg:
amd64_movss_membase_reg (code, AMD64_RCX, (quad * 8), cinfo->ret.pair_regs [quad]);
amd64_mov_reg_imm_size (code, ins->dreg, 0, 8);
break;
case OP_MOVE:
- amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, SIZEOF_REGISTER);
+ amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, sizeof(mgreg_t));
break;
case OP_AMD64_SET_XMMREG_R4: {
amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg1);
else {
for (i = 0; i < AMD64_NREG; ++i)
if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i)))
- pos -= SIZEOF_REGISTER;
+ pos -= sizeof(mgreg_t);
/* Restore callee-saved registers */
for (i = AMD64_NREG - 1; i > 0; --i) {
if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
- amd64_mov_reg_membase (code, i, AMD64_RBP, pos, SIZEOF_REGISTER);
- pos += SIZEOF_REGISTER;
+ amd64_mov_reg_membase (code, i, AMD64_RBP, pos, sizeof(mgreg_t));
+ pos += sizeof(mgreg_t);
}
}
/* Copy arguments on the stack to our argument area */
- for (i = 0; i < call->stack_usage; i += SIZEOF_REGISTER) {
- amd64_mov_reg_membase (code, AMD64_RAX, AMD64_RSP, i, SIZEOF_REGISTER);
- amd64_mov_membase_reg (code, AMD64_RBP, 16 + i, AMD64_RAX, SIZEOF_REGISTER);
+ for (i = 0; i < call->stack_usage; i += sizeof(mgreg_t)) {
+ amd64_mov_reg_membase (code, AMD64_RAX, AMD64_RSP, i, sizeof(mgreg_t));
+ amd64_mov_membase_reg (code, AMD64_RBP, 16 + i, AMD64_RAX, sizeof(mgreg_t));
}
if (pos)
/* Set argument registers */
for (i = 0; i < PARAM_REGS; ++i)
- amd64_mov_reg_membase (code, param_regs [i], AMD64_R11, i * SIZEOF_REGISTER, SIZEOF_REGISTER);
+ amd64_mov_reg_membase (code, param_regs [i], AMD64_R11, i * sizeof(mgreg_t), sizeof(mgreg_t));
/* Make the call */
amd64_call_reg (code, AMD64_R10);
mono_arch_unwindinfo_add_push_nonvol (&cfg->arch.unwindinfo, cfg->native_code, code, AMD64_RBP);
#endif
- amd64_mov_reg_reg (code, AMD64_RBP, AMD64_RSP, SIZEOF_REGISTER);
+ amd64_mov_reg_reg (code, AMD64_RBP, AMD64_RSP, sizeof(mgreg_t));
mono_emit_unwind_op_def_cfa_reg (cfg, code, AMD64_RBP);
async_exc_point (code);
#ifdef HOST_WIN32
if (cfg->arch.omit_fp)
// FIXME:
g_assert_not_reached ();
- cfg->stack_offset += ALIGN_TO (cfg->param_area, SIZEOF_REGISTER);
+ cfg->stack_offset += ALIGN_TO (cfg->param_area, sizeof(mgreg_t));
}
if (cfg->arch.omit_fp) {
for (quad = 0; quad < 2; quad ++) {
switch (ainfo->pair_storage [quad]) {
case ArgInIReg:
- amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * SIZEOF_REGISTER), ainfo->pair_regs [quad], SIZEOF_REGISTER);
+ amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof(mgreg_t)), ainfo->pair_regs [quad], sizeof(mgreg_t));
break;
case ArgInFloatSSEReg:
- amd64_movss_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * SIZEOF_REGISTER), ainfo->pair_regs [quad]);
+ amd64_movss_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof(mgreg_t)), ainfo->pair_regs [quad]);
break;
case ArgInDoubleSSEReg:
- amd64_movsd_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * SIZEOF_REGISTER), ainfo->pair_regs [quad]);
+ amd64_movsd_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof(mgreg_t)), ainfo->pair_regs [quad]);
break;
case ArgNone:
break;
for (quad = 0; quad < 2; quad ++) {
switch (ainfo->pair_storage [quad]) {
case ArgInIReg:
- amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * SIZEOF_REGISTER), ainfo->pair_regs [quad], SIZEOF_REGISTER);
+ amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof(mgreg_t)), ainfo->pair_regs [quad], sizeof(mgreg_t));
break;
case ArgInFloatSSEReg:
- amd64_movss_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * SIZEOF_REGISTER), ainfo->pair_regs [quad]);
+ amd64_movss_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof(mgreg_t)), ainfo->pair_regs [quad]);
break;
case ArgInDoubleSSEReg:
- amd64_movsd_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * SIZEOF_REGISTER), ainfo->pair_regs [quad]);
+ amd64_movsd_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof(mgreg_t)), ainfo->pair_regs [quad]);
break;
case ArgNone:
break;
else {
for (i = 0; i < AMD64_NREG; ++i)
if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i)))
- pos -= SIZEOF_REGISTER;
+ pos -= sizeof(mgreg_t);
if (pos) {
- if (pos == - SIZEOF_REGISTER) {
+ if (pos == - sizeof(mgreg_t)) {
/* Only one register, so avoid lea */
for (i = AMD64_NREG - 1; i > 0; --i)
if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
for (quad = 0; quad < 2; quad ++) {
switch (ainfo->pair_storage [quad]) {
case ArgInIReg:
- amd64_mov_reg_membase (code, ainfo->pair_regs [quad], inst->inst_basereg, inst->inst_offset + (quad * SIZEOF_REGISTER), SIZEOF_REGISTER);
+ amd64_mov_reg_membase (code, ainfo->pair_regs [quad], inst->inst_basereg, inst->inst_offset + (quad * sizeof(mgreg_t)), sizeof(mgreg_t));
break;
case ArgInFloatSSEReg:
- amd64_movss_reg_membase (code, ainfo->pair_regs [quad], inst->inst_basereg, inst->inst_offset + (quad * SIZEOF_REGISTER));
+ amd64_movss_reg_membase (code, ainfo->pair_regs [quad], inst->inst_basereg, inst->inst_offset + (quad * sizeof(mgreg_t)));
break;
case ArgInDoubleSSEReg:
- amd64_movsd_reg_membase (code, ainfo->pair_regs [quad], inst->inst_basereg, inst->inst_offset + (quad * SIZEOF_REGISTER));
+ amd64_movsd_reg_membase (code, ainfo->pair_regs [quad], inst->inst_basereg, inst->inst_offset + (quad * sizeof(mgreg_t)));
break;
case ArgNone:
break;
vars = mono_varlist_sort (cfg, vars, 0);
offset = 0;
- *stack_align = SIZEOF_REGISTER;
+ *stack_align = sizeof(mgreg_t);
for (l = vars; l; l = l->next) {
vmv = l->data;
inst = cfg->varinfo [vmv->idx];
/* Pop the return address off the stack */
amd64_pop_reg (code, AMD64_R11);
- orig_rsp_to_rbp_offset += SIZEOF_REGISTER;
+ orig_rsp_to_rbp_offset += sizeof(mgreg_t);
- cfa_offset -= SIZEOF_REGISTER;
+ cfa_offset -= sizeof(mgreg_t);
mono_add_unwind_op_def_cfa_offset (unwind_ops, code, buf, cfa_offset);
/*
* Allocate a new stack frame
*/
amd64_push_reg (code, AMD64_RBP);
- cfa_offset += SIZEOF_REGISTER;
+ cfa_offset += sizeof(mgreg_t);
mono_add_unwind_op_def_cfa_offset (unwind_ops, code, buf, cfa_offset);
mono_add_unwind_op_offset (unwind_ops, code, buf, AMD64_RBP, - cfa_offset);
- orig_rsp_to_rbp_offset -= SIZEOF_REGISTER;
- amd64_mov_reg_reg (code, AMD64_RBP, AMD64_RSP, SIZEOF_REGISTER);
+ orig_rsp_to_rbp_offset -= sizeof(mgreg_t);
+ amd64_mov_reg_reg (code, AMD64_RBP, AMD64_RSP, sizeof(mgreg_t));
mono_add_unwind_op_def_cfa_reg (unwind_ops, code, buf, AMD64_RBP);
amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, framesize);
offset = 0;
rbp_offset = - offset;
- offset += SIZEOF_REGISTER;
+ offset += sizeof(mgreg_t);
rax_offset = - offset;
- offset += SIZEOF_REGISTER;
+ offset += sizeof(mgreg_t);
tramp_offset = - offset;
offset += sizeof(gpointer);
}
amd64_mov_membase_reg (code, AMD64_RBP, tramp_offset, AMD64_R11, sizeof(gpointer));
- offset += SIZEOF_REGISTER;
+ offset += sizeof(mgreg_t);
res_offset = - offset;
/* Save all registers */
- offset += AMD64_NREG * SIZEOF_REGISTER;
+ offset += AMD64_NREG * sizeof(mgreg_t);
saved_regs_offset = - offset;
for (i = 0; i < AMD64_NREG; ++i) {
if (i == AMD64_RBP) {
/* RAX is already saved */
- amd64_mov_reg_membase (code, AMD64_RAX, AMD64_RBP, rbp_offset, SIZEOF_REGISTER);
- amd64_mov_membase_reg (code, AMD64_RBP, saved_regs_offset + (i * SIZEOF_REGISTER), AMD64_RAX, SIZEOF_REGISTER);
+ amd64_mov_reg_membase (code, AMD64_RAX, AMD64_RBP, rbp_offset, sizeof(mgreg_t));
+ amd64_mov_membase_reg (code, AMD64_RBP, saved_regs_offset + (i * sizeof(mgreg_t)), AMD64_RAX, sizeof(mgreg_t));
} else if (i != AMD64_R11) {
- amd64_mov_membase_reg (code, AMD64_RBP, saved_regs_offset + (i * SIZEOF_REGISTER), i, SIZEOF_REGISTER);
+ amd64_mov_membase_reg (code, AMD64_RBP, saved_regs_offset + (i * sizeof(mgreg_t)), i, sizeof(mgreg_t));
} else {
/* We have to save R11 right at the start of
the trampoline code because it's used as a
scratch register */
- amd64_mov_membase_reg (r11_save_code, AMD64_RSP, saved_regs_offset + orig_rsp_to_rbp_offset + (i * SIZEOF_REGISTER), i, SIZEOF_REGISTER);
+ amd64_mov_membase_reg (r11_save_code, AMD64_RSP, saved_regs_offset + orig_rsp_to_rbp_offset + (i * sizeof(mgreg_t)), i, sizeof(mgreg_t));
g_assert (r11_save_code == after_r11_save_code);
}
}
- offset += 8 * SIZEOF_REGISTER;
+ offset += 8 * sizeof(mgreg_t);
saved_fpregs_offset = - offset;
for (i = 0; i < 8; ++i)
- amd64_movsd_membase_reg (code, AMD64_RBP, saved_fpregs_offset + (i * SIZEOF_REGISTER), i);
+ amd64_movsd_membase_reg (code, AMD64_RBP, saved_fpregs_offset + (i * sizeof(mgreg_t)), i);
if (tramp_type != MONO_TRAMPOLINE_GENERIC_CLASS_INIT &&
tramp_type != MONO_TRAMPOLINE_MONITOR_ENTER &&
}
amd64_mov_membase_reg (code, AMD64_RBP, arg_offset, AMD64_R11, sizeof(gpointer));
} else {
- amd64_mov_reg_membase (code, AMD64_R11, AMD64_RBP, saved_regs_offset + (MONO_AMD64_ARG_REG1 * SIZEOF_REGISTER), SIZEOF_REGISTER);
+ amd64_mov_reg_membase (code, AMD64_R11, AMD64_RBP, saved_regs_offset + (MONO_AMD64_ARG_REG1 * sizeof(mgreg_t)), sizeof(mgreg_t));
amd64_mov_membase_reg (code, AMD64_RBP, arg_offset, AMD64_R11, sizeof(gpointer));
}
amd64_mov_reg_membase (code, AMD64_R11, AMD64_RBP, 8, sizeof(gpointer));
else
amd64_mov_reg_imm (code, AMD64_R11, 0);
- amd64_mov_membase_reg (code, AMD64_RBP, lmf_offset + G_STRUCT_OFFSET (MonoLMF, rip), AMD64_R11, SIZEOF_REGISTER);
+ amd64_mov_membase_reg (code, AMD64_RBP, lmf_offset + G_STRUCT_OFFSET (MonoLMF, rip), AMD64_R11, sizeof(mgreg_t));
/* Save fp */
- amd64_mov_reg_membase (code, AMD64_R11, AMD64_RSP, framesize, SIZEOF_REGISTER);
- amd64_mov_membase_reg (code, AMD64_RBP, lmf_offset + G_STRUCT_OFFSET (MonoLMF, rbp), AMD64_R11, SIZEOF_REGISTER);
+ amd64_mov_reg_membase (code, AMD64_R11, AMD64_RSP, framesize, sizeof(mgreg_t));
+ amd64_mov_membase_reg (code, AMD64_RBP, lmf_offset + G_STRUCT_OFFSET (MonoLMF, rbp), AMD64_R11, sizeof(mgreg_t));
/* Save sp */
- amd64_mov_reg_reg (code, AMD64_R11, AMD64_RSP, SIZEOF_REGISTER);
+ amd64_mov_reg_reg (code, AMD64_R11, AMD64_RSP, sizeof(mgreg_t));
amd64_alu_reg_imm (code, X86_ADD, AMD64_R11, framesize + 16);
- amd64_mov_membase_reg (code, AMD64_RBP, lmf_offset + G_STRUCT_OFFSET (MonoLMF, rsp), AMD64_R11, SIZEOF_REGISTER);
+ amd64_mov_membase_reg (code, AMD64_RBP, lmf_offset + G_STRUCT_OFFSET (MonoLMF, rsp), AMD64_R11, sizeof(mgreg_t));
/* Save method */
if (tramp_type == MONO_TRAMPOLINE_JIT || tramp_type == MONO_TRAMPOLINE_JUMP) {
amd64_mov_reg_membase (code, AMD64_R11, AMD64_RBP, arg_offset, sizeof(gpointer));
}
/* Save callee saved regs */
#ifdef TARGET_WIN32
- amd64_mov_membase_reg (code, AMD64_RBP, lmf_offset + G_STRUCT_OFFSET (MonoLMF, rdi), AMD64_RDI, SIZEOF_REGISTER);
- amd64_mov_membase_reg (code, AMD64_RBP, lmf_offset + G_STRUCT_OFFSET (MonoLMF, rsi), AMD64_RSI, SIZEOF_REGISTER);
+ amd64_mov_membase_reg (code, AMD64_RBP, lmf_offset + G_STRUCT_OFFSET (MonoLMF, rdi), AMD64_RDI, sizeof(mgreg_t));
+ amd64_mov_membase_reg (code, AMD64_RBP, lmf_offset + G_STRUCT_OFFSET (MonoLMF, rsi), AMD64_RSI, sizeof(mgreg_t));
#endif
- amd64_mov_membase_reg (code, AMD64_RBP, lmf_offset + G_STRUCT_OFFSET (MonoLMF, rbx), AMD64_RBX, SIZEOF_REGISTER);
- amd64_mov_membase_reg (code, AMD64_RBP, lmf_offset + G_STRUCT_OFFSET (MonoLMF, r12), AMD64_R12, SIZEOF_REGISTER);
- amd64_mov_membase_reg (code, AMD64_RBP, lmf_offset + G_STRUCT_OFFSET (MonoLMF, r13), AMD64_R13, SIZEOF_REGISTER);
- amd64_mov_membase_reg (code, AMD64_RBP, lmf_offset + G_STRUCT_OFFSET (MonoLMF, r14), AMD64_R14, SIZEOF_REGISTER);
- amd64_mov_membase_reg (code, AMD64_RBP, lmf_offset + G_STRUCT_OFFSET (MonoLMF, r15), AMD64_R15, SIZEOF_REGISTER);
+ amd64_mov_membase_reg (code, AMD64_RBP, lmf_offset + G_STRUCT_OFFSET (MonoLMF, rbx), AMD64_RBX, sizeof(mgreg_t));
+ amd64_mov_membase_reg (code, AMD64_RBP, lmf_offset + G_STRUCT_OFFSET (MonoLMF, r12), AMD64_R12, sizeof(mgreg_t));
+ amd64_mov_membase_reg (code, AMD64_RBP, lmf_offset + G_STRUCT_OFFSET (MonoLMF, r13), AMD64_R13, sizeof(mgreg_t));
+ amd64_mov_membase_reg (code, AMD64_RBP, lmf_offset + G_STRUCT_OFFSET (MonoLMF, r14), AMD64_R14, sizeof(mgreg_t));
+ amd64_mov_membase_reg (code, AMD64_RBP, lmf_offset + G_STRUCT_OFFSET (MonoLMF, r15), AMD64_R15, sizeof(mgreg_t));
if (aot) {
code = mono_arch_emit_load_aotconst (buf, code, &ji, MONO_PATCH_INFO_JIT_ICALL_ADDR, "mono_get_lmf_addr");
/*
* Have to call the _force_ variant, since there could be a protected wrapper on the top of the stack.
*/
- amd64_mov_membase_reg (code, AMD64_RBP, res_offset, AMD64_RAX, SIZEOF_REGISTER);
+ amd64_mov_membase_reg (code, AMD64_RBP, res_offset, AMD64_RAX, sizeof(mgreg_t));
if (aot) {
code = mono_arch_emit_load_aotconst (buf, code, &ji, MONO_PATCH_INFO_JIT_ICALL_ADDR, "mono_thread_force_interruption_checkpoint");
} else {
}
amd64_call_reg (code, AMD64_R11);
- amd64_mov_reg_membase (code, AMD64_RAX, AMD64_RBP, res_offset, SIZEOF_REGISTER);
+ amd64_mov_reg_membase (code, AMD64_RAX, AMD64_RBP, res_offset, sizeof(mgreg_t));
/* Restore LMF */
* Save rax to the stack, after the leave instruction, this will become part of
* the red zone.
*/
- amd64_mov_membase_reg (code, AMD64_RBP, rax_offset, AMD64_RAX, SIZEOF_REGISTER);
+ amd64_mov_membase_reg (code, AMD64_RBP, rax_offset, AMD64_RAX, sizeof(mgreg_t));
/* Restore argument registers, r10 (imt method/rgxtx)
and rax (needed for direct calls to C vararg functions). */
for (i = 0; i < AMD64_NREG; ++i)
if (AMD64_IS_ARGUMENT_REG (i) || i == AMD64_R10 || i == AMD64_RAX)
- amd64_mov_reg_membase (code, i, AMD64_RBP, saved_regs_offset + (i * SIZEOF_REGISTER), SIZEOF_REGISTER);
+ amd64_mov_reg_membase (code, i, AMD64_RBP, saved_regs_offset + (i * sizeof(mgreg_t)), sizeof(mgreg_t));
for (i = 0; i < 8; ++i)
- amd64_movsd_reg_membase (code, i, AMD64_RBP, saved_fpregs_offset + (i * SIZEOF_REGISTER));
+ amd64_movsd_reg_membase (code, i, AMD64_RBP, saved_fpregs_offset + (i * sizeof(mgreg_t)));
/* Restore stack */
amd64_leave (code);
if (MONO_TRAMPOLINE_TYPE_MUST_RETURN (tramp_type)) {
/* Load result */
- amd64_mov_reg_membase (code, AMD64_RAX, AMD64_RSP, rax_offset - SIZEOF_REGISTER, SIZEOF_REGISTER);
+ amd64_mov_reg_membase (code, AMD64_RAX, AMD64_RSP, rax_offset - sizeof(mgreg_t), sizeof(mgreg_t));
amd64_ret (code);
} else {
/* call the compiled method using the saved rax */
- amd64_jump_membase (code, AMD64_RSP, rax_offset - SIZEOF_REGISTER);
+ amd64_jump_membase (code, AMD64_RSP, rax_offset - sizeof(mgreg_t));
}
g_assert ((code - buf) <= kMaxCodeSize);