mono/mini/mini-amd64.c

   1 /*
   2  * mini-amd64.c: AMD64 backend for the Mono code generator
   3  *
   4  * Based on mini-x86.c.
   5  *
   6  * Authors:
   7  *   Paolo Molaro (lupus@ximian.com)
   8  *   Dietmar Maurer (dietmar@ximian.com)
   9  *   Patrik Torstensson
  10  *   Zoltan Varga (vargaz@gmail.com)
  11  *
  12  * (C) 2003 Ximian, Inc.
  13  */
  14 #include "mini.h"
  15 #include <string.h>
  16 #include <math.h>
  17 #ifdef HAVE_UNISTD_H
  18 #include <unistd.h>
  19 #endif
  20
  21 #include <mono/metadata/appdomain.h>
  22 #include <mono/metadata/debug-helpers.h>
  23 #include <mono/metadata/threads.h>
  24 #include <mono/metadata/profiler-private.h>
  25 #include <mono/metadata/mono-debug.h>
  26 #include <mono/metadata/gc-internal.h>
  27 #include <mono/utils/mono-math.h>
  28 #include <mono/utils/mono-mmap.h>
  29
  30 #include "trace.h"
  31 #include "ir-emit.h"
  32 #include "mini-amd64.h"
  33 #include "cpu-amd64.h"
  34 #include "debugger-agent.h"
  35
  36 static gint lmf_tls_offset = -1;
  37 static gint lmf_addr_tls_offset = -1;
  38 static gint appdomain_tls_offset = -1;
  39
  40 #ifdef MONO_XEN_OPT
  41 static gboolean optimize_for_xen = TRUE;
  42 #else
  43 #define optimize_for_xen 0
  44 #endif
  45
  46 #define ALIGN_TO(val,align) ((((guint64)val) + ((align) - 1)) & ~((align) - 1))
  47
  48 #define IS_IMM32(val) ((((guint64)val) >> 32) == 0)
  49
  50 #define IS_REX(inst) (((inst) >= 0x40) && ((inst) <= 0x4f))
  51
  52 #ifdef HOST_WIN32
  53 /* Under windows, the calling convention is never stdcall */
  54 #define CALLCONV_IS_STDCALL(call_conv) (FALSE)
  55 #else
  56 #define CALLCONV_IS_STDCALL(call_conv) ((call_conv) == MONO_CALL_STDCALL)
  57 #endif
  58
  59 /* This mutex protects architecture specific caches */
  60 #define mono_mini_arch_lock() EnterCriticalSection (&mini_arch_mutex)
  61 #define mono_mini_arch_unlock() LeaveCriticalSection (&mini_arch_mutex)
  62 static CRITICAL_SECTION mini_arch_mutex;
  63
  64 MonoBreakpointInfo
  65 mono_breakpoint_info [MONO_BREAKPOINT_ARRAY_SIZE];
  66
  67 /*
  68  * The code generated for sequence points reads from this location, which is
  69  * made read-only when single stepping is enabled.
  70  */
  71 static gpointer ss_trigger_page;
  72
  73 /* Enabled breakpoints read from this trigger page */
  74 static gpointer bp_trigger_page;
  75
  76 /* The size of the breakpoint sequence */
  77 static int breakpoint_size;
  78
  79 /* The size of the breakpoint instruction causing the actual fault */
  80 static int breakpoint_fault_size;
  81
  82 /* The size of the single step instruction causing the actual fault */
  83 static int single_step_fault_size;
  84
  85 #ifdef HOST_WIN32
  86 /* On Win64 always reserve first 32 bytes for first four arguments */
  87 #define ARGS_OFFSET 48
  88 #else
  89 #define ARGS_OFFSET 16
  90 #endif
  91 #define GP_SCRATCH_REG AMD64_R11
  92
  93 /*
  94  * AMD64 register usage:
  95  * - callee saved registers are used for global register allocation
  96  * - %r11 is used for materializing 64 bit constants in opcodes
  97  * - the rest is used for local allocation
  98  */
  99
 100 /*
 101  * Floating point comparison results:
 102  *                  ZF PF CF
 103  * A > B            0  0  0
 104  * A < B            0  0  1
 105  * A = B            1  0  0
 106  * A > B            0  0  0
 107  * UNORDERED        1  1  1
 108  */
 109
 110 const char*
 111 mono_arch_regname (int reg)
 112 {
 113         switch (reg) {
 114         case AMD64_RAX: return "%rax";
 115         case AMD64_RBX: return "%rbx";
 116         case AMD64_RCX: return "%rcx";
 117         case AMD64_RDX: return "%rdx";
 118         case AMD64_RSP: return "%rsp";
 119         case AMD64_RBP: return "%rbp";
 120         case AMD64_RDI: return "%rdi";
 121         case AMD64_RSI: return "%rsi";
 122         case AMD64_R8: return "%r8";
 123         case AMD64_R9: return "%r9";
 124         case AMD64_R10: return "%r10";
 125         case AMD64_R11: return "%r11";
 126         case AMD64_R12: return "%r12";
 127         case AMD64_R13: return "%r13";
 128         case AMD64_R14: return "%r14";
 129         case AMD64_R15: return "%r15";
 130         }
 131         return "unknown";
 132 }
 133
 134 static const char * packed_xmmregs [] = {
 135         "p:xmm0", "p:xmm1", "p:xmm2", "p:xmm3", "p:xmm4", "p:xmm5", "p:xmm6", "p:xmm7", "p:xmm8",
 136         "p:xmm9", "p:xmm10", "p:xmm11", "p:xmm12", "p:xmm13", "p:xmm14", "p:xmm15"
 137 };
 138
 139 static const char * single_xmmregs [] = {
 140         "s:xmm0", "s:xmm1", "s:xmm2", "s:xmm3", "s:xmm4", "s:xmm5", "s:xmm6", "s:xmm7", "s:xmm8",
 141         "s:xmm9", "s:xmm10", "s:xmm11", "s:xmm12", "s:xmm13", "s:xmm14", "s:xmm15"
 142 };
 143
 144 const char*
 145 mono_arch_fregname (int reg)
 146 {
 147         if (reg < AMD64_XMM_NREG)
 148                 return single_xmmregs [reg];
 149         else
 150                 return "unknown";
 151 }
 152
 153 const char *
 154 mono_arch_xregname (int reg)
 155 {
 156         if (reg < AMD64_XMM_NREG)
 157                 return packed_xmmregs [reg];
 158         else
 159                 return "unknown";
 160 }
 161
 162 G_GNUC_UNUSED static void
 163 break_count (void)
 164 {
 165 }
 166
 167 G_GNUC_UNUSED static gboolean
 168 debug_count (void)
 169 {
 170         static int count = 0;
 171         count ++;
 172
 173         if (!getenv ("COUNT"))
 174                 return TRUE;
 175
 176         if (count == atoi (getenv ("COUNT"))) {
 177                 break_count ();
 178         }
 179
 180         if (count > atoi (getenv ("COUNT"))) {
 181                 return FALSE;
 182         }
 183
 184         return TRUE;
 185 }
 186
 187 static gboolean
 188 debug_omit_fp (void)
 189 {
 190 #if 0
 191         return debug_count ();
 192 #else
 193         return TRUE;
 194 #endif
 195 }
 196
 197 static inline gboolean
 198 amd64_is_near_call (guint8 *code)
 199 {
 200         /* Skip REX */
 201         if ((code [0] >= 0x40) && (code [0] <= 0x4f))
 202                 code += 1;
 203
 204         return code [0] == 0xe8;
 205 }
 206
 207 #ifdef __native_client_codegen__
 208
 209 /* Keep track of instruction "depth", that is, the level of sub-instruction */
 210 /* for any given instruction.  For instance, amd64_call_reg resolves to     */
 211 /* amd64_call_reg_internal, which uses amd64_alu_* macros, etc.             */
 212 /* We only want to force bundle alignment for the top level instruction,    */
 213 /* so NaCl pseudo-instructions can be implemented with sub instructions.    */
 214 static guint32 nacl_instruction_depth;
 215
 216 static guint32 nacl_rex_tag;
 217 static guint32 nacl_legacy_prefix_tag;
 218
 219 void
 220 amd64_nacl_clear_legacy_prefix_tag ()
 221 {
 222         TlsSetValue (nacl_legacy_prefix_tag, NULL);
 223 }
 224
 225 void
 226 amd64_nacl_tag_legacy_prefix (guint8* code)
 227 {
 228         if (TlsGetValue (nacl_legacy_prefix_tag) == NULL)
 229                 TlsSetValue (nacl_legacy_prefix_tag, code);
 230 }
 231
 232 void
 233 amd64_nacl_tag_rex (guint8* code)
 234 {
 235         TlsSetValue (nacl_rex_tag, code);
 236 }
 237
 238 guint8*
 239 amd64_nacl_get_legacy_prefix_tag ()
 240 {
 241         return (guint8*)TlsGetValue (nacl_legacy_prefix_tag);
 242 }
 243
 244 guint8*
 245 amd64_nacl_get_rex_tag ()
 246 {
 247         return (guint8*)TlsGetValue (nacl_rex_tag);
 248 }
 249
 250 /* Increment the instruction "depth" described above */
 251 void
 252 amd64_nacl_instruction_pre ()
 253 {
 254         intptr_t depth = (intptr_t) TlsGetValue (nacl_instruction_depth);
 255         depth++;
 256         TlsSetValue (nacl_instruction_depth, (gpointer)depth);
 257 }
 258
 259 /* amd64_nacl_instruction_post: Decrement instruction "depth", force bundle */
 260 /* alignment if depth == 0 (top level instruction)                          */
 261 /* IN: start, end    pointers to instruction beginning and end              */
 262 /* OUT: start, end   pointers to beginning and end after possible alignment */
 263 /* GLOBALS: nacl_instruction_depth     defined above                        */
 264 void
 265 amd64_nacl_instruction_post (guint8 **start, guint8 **end)
 266 {
 267         intptr_t depth = (intptr_t) TlsGetValue(nacl_instruction_depth);
 268         depth--;
 269         TlsSetValue (nacl_instruction_depth, (void*)depth);
 270
 271         g_assert ( depth >= 0 );
 272         if (depth == 0) {
 273                 uintptr_t space_in_block;
 274                 uintptr_t instlen;
 275                 guint8 *prefix = amd64_nacl_get_legacy_prefix_tag ();
 276                 /* if legacy prefix is present, and if it was emitted before */
 277                 /* the start of the instruction sequence, adjust the start   */
 278                 if (prefix != NULL && prefix < *start) {
 279                         g_assert (*start - prefix <= 3);/* only 3 are allowed */
 280                         *start = prefix;
 281                 }
 282                 space_in_block = kNaClAlignment - ((uintptr_t)(*start) & kNaClAlignmentMask);
 283                 instlen = (uintptr_t)(*end - *start);
 284                 /* Only check for instructions which are less than        */
 285                 /* kNaClAlignment. The only instructions that should ever */
 286                 /* be that long are call sequences, which are already     */
 287                 /* padded out to align the return to the next bundle.     */
 288                 if (instlen > space_in_block && instlen < kNaClAlignment) {
 289                         const size_t MAX_NACL_INST_LENGTH = kNaClAlignment;
 290                         guint8 copy_of_instruction[MAX_NACL_INST_LENGTH];
 291                         const size_t length = (size_t)((*end)-(*start));
 292                         g_assert (length < MAX_NACL_INST_LENGTH);
 293
 294                         memcpy (copy_of_instruction, *start, length);
 295                         *start = mono_arch_nacl_pad (*start, space_in_block);
 296                         memcpy (*start, copy_of_instruction, length);
 297                         *end = *start + length;
 298                 }
 299                 amd64_nacl_clear_legacy_prefix_tag ();
 300                 amd64_nacl_tag_rex (NULL);
 301         }
 302 }
 303
 304 /* amd64_nacl_membase_handler: ensure all access to memory of the form      */
 305 /*   OFFSET(%rXX) is sandboxed.  For allowable base registers %rip, %rbp,   */
 306 /*   %rsp, and %r15, emit the membase as usual.  For all other registers,   */
 307 /*   make sure the upper 32-bits are cleared, and use that register in the  */
 308 /*   index field of a new address of this form: OFFSET(%r15,%eXX,1)         */
 309 /* IN:      code                                                            */
 310 /*             pointer to current instruction stream (in the                */
 311 /*             middle of an instruction, after opcode is emitted)           */
 312 /*          basereg/offset/dreg                                             */
 313 /*             operands of normal membase address                           */
 314 /* OUT:     code                                                            */
 315 /*             pointer to the end of the membase/memindex emit              */
 316 /* GLOBALS: nacl_rex_tag                                                    */
 317 /*             position in instruction stream that rex prefix was emitted   */
 318 /*          nacl_legacy_prefix_tag                                          */
 319 /*             (possibly NULL) position in instruction of legacy x86 prefix */
 320 void
 321 amd64_nacl_membase_handler (guint8** code, gint8 basereg, gint32 offset, gint8 dreg)
 322 {
 323         gint8 true_basereg = basereg;
 324
 325         /* Cache these values, they might change  */
 326         /* as new instructions are emitted below. */
 327         guint8* rex_tag = amd64_nacl_get_rex_tag ();
 328         guint8* legacy_prefix_tag = amd64_nacl_get_legacy_prefix_tag ();
 329
 330         /* 'basereg' is given masked to 0x7 at this point, so check */
 331         /* the rex prefix to see if this is an extended register.   */
 332         if ((rex_tag != NULL) && IS_REX(*rex_tag) && (*rex_tag & AMD64_REX_B)) {
 333                 true_basereg |= 0x8;
 334         }
 335
 336 #define X86_LEA_OPCODE (0x8D)
 337
 338         if (!amd64_is_valid_nacl_base (true_basereg) && (*(*code-1) != X86_LEA_OPCODE)) {
 339                 guint8* old_instruction_start;
 340
 341                 /* This will hold the 'mov %eXX, %eXX' that clears the upper */
 342                 /* 32-bits of the old base register (new index register)     */
 343                 guint8 buf[32];
 344                 guint8* buf_ptr = buf;
 345                 size_t insert_len;
 346
 347                 g_assert (rex_tag != NULL);
 348
 349                 if (IS_REX(*rex_tag)) {
 350                         /* The old rex.B should be the new rex.X */
 351                         if (*rex_tag & AMD64_REX_B) {
 352                                 *rex_tag |= AMD64_REX_X;
 353                         }
 354                         /* Since our new base is %r15 set rex.B */
 355                         *rex_tag |= AMD64_REX_B;
 356                 } else {
 357                         /* Shift the instruction by one byte  */
 358                         /* so we can insert a rex prefix      */
 359                         memmove (rex_tag + 1, rex_tag, (size_t)(*code - rex_tag));
 360                         *code += 1;
 361                         /* New rex prefix only needs rex.B for %r15 base */
 362                         *rex_tag = AMD64_REX(AMD64_REX_B);
 363                 }
 364
 365                 if (legacy_prefix_tag) {
 366                         old_instruction_start = legacy_prefix_tag;
 367                 } else {
 368                         old_instruction_start = rex_tag;
 369                 }
 370
 371                 /* Clears the upper 32-bits of the previous base register */
 372                 amd64_mov_reg_reg_size (buf_ptr, true_basereg, true_basereg, 4);
 373                 insert_len = buf_ptr - buf;
 374
 375                 /* Move the old instruction forward to make */
 376                 /* room for 'mov' stored in 'buf_ptr'       */
 377                 memmove (old_instruction_start + insert_len, old_instruction_start, (size_t)(*code - old_instruction_start));
 378                 *code += insert_len;
 379                 memcpy (old_instruction_start, buf, insert_len);
 380
 381                 /* Sandboxed replacement for the normal membase_emit */
 382                 x86_memindex_emit (*code, dreg, AMD64_R15, offset, basereg, 0);
 383
 384         } else {
 385                 /* Normal default behavior, emit membase memory location */
 386                 x86_membase_emit_body (*code, dreg, basereg, offset);
 387         }
 388 }
 389
 390
 391 static inline unsigned char*
 392 amd64_skip_nops (unsigned char* code)
 393 {
 394         guint8 in_nop;
 395         do {
 396                 in_nop = 0;
 397                 if (   code[0] == 0x90) {
 398                         in_nop = 1;
 399                         code += 1;
 400                 }
 401                 if (   code[0] == 0x66 && code[1] == 0x90) {
 402                         in_nop = 1;
 403                         code += 2;
 404                 }
 405                 if (code[0] == 0x0f && code[1] == 0x1f
 406                  && code[2] == 0x00) {
 407                         in_nop = 1;
 408                         code += 3;
 409                 }
 410                 if (code[0] == 0x0f && code[1] == 0x1f
 411                  && code[2] == 0x40 && code[3] == 0x00) {
 412                         in_nop = 1;
 413                         code += 4;
 414                 }
 415                 if (code[0] == 0x0f && code[1] == 0x1f
 416                  && code[2] == 0x44 && code[3] == 0x00
 417                  && code[4] == 0x00) {
 418                         in_nop = 1;
 419                         code += 5;
 420                 }
 421                 if (code[0] == 0x66 && code[1] == 0x0f
 422                  && code[2] == 0x1f && code[3] == 0x44
 423                  && code[4] == 0x00 && code[5] == 0x00) {
 424                         in_nop = 1;
 425                         code += 6;
 426                 }
 427                 if (code[0] == 0x0f && code[1] == 0x1f
 428                  && code[2] == 0x80 && code[3] == 0x00
 429                  && code[4] == 0x00 && code[5] == 0x00
 430                  && code[6] == 0x00) {
 431                         in_nop = 1;
 432                         code += 7;
 433                 }
 434                 if (code[0] == 0x0f && code[1] == 0x1f
 435                  && code[2] == 0x84 && code[3] == 0x00
 436                  && code[4] == 0x00 && code[5] == 0x00
 437                  && code[6] == 0x00 && code[7] == 0x00) {
 438                         in_nop = 1;
 439                         code += 8;
 440                 }
 441         } while ( in_nop );
 442         return code;
 443 }
 444
 445 guint8*
 446 mono_arch_nacl_skip_nops (guint8* code)
 447 {
 448   return amd64_skip_nops(code);
 449 }
 450
 451 #endif /*__native_client_codegen__*/
 452
 453 static inline void
 454 amd64_patch (unsigned char* code, gpointer target)
 455 {
 456         guint8 rex = 0;
 457
 458 #ifdef __native_client_codegen__
 459         code = amd64_skip_nops (code);
 460 #endif
 461 #if defined(__native_client_codegen__) && defined(__native_client__)
 462         if (nacl_is_code_address (code)) {
 463                 /* For tail calls, code is patched after being installed */
 464                 /* but not through the normal "patch callsite" method.   */
 465                 unsigned char buf[kNaClAlignment];
 466                 unsigned char *aligned_code = (uintptr_t)code & ~kNaClAlignmentMask;
 467                 int ret;
 468                 memcpy (buf, aligned_code, kNaClAlignment);
 469                 /* Patch a temp buffer of bundle size, */
 470                 /* then install to actual location.    */
 471                 amd64_patch (buf + ((uintptr_t)code - (uintptr_t)aligned_code), target);
 472                 ret = nacl_dyncode_modify (aligned_code, buf, kNaClAlignment);
 473                 g_assert (ret == 0);
 474                 return;
 475         }
 476         target = nacl_modify_patch_target (target);
 477 #endif
 478
 479         /* Skip REX */
 480         if ((code [0] >= 0x40) && (code [0] <= 0x4f)) {
 481                 rex = code [0];
 482                 code += 1;
 483         }
 484
 485         if ((code [0] & 0xf8) == 0xb8) {
 486                 /* amd64_set_reg_template */
 487                 *(guint64*)(code + 1) = (guint64)target;
 488         }
 489         else if ((code [0] == 0x8b) && rex && x86_modrm_mod (code [1]) == 0 && x86_modrm_rm (code [1]) == 5) {
 490                 /* mov 0(%rip), %dreg */
 491                 *(guint32*)(code + 2) = (guint32)(guint64)target - 7;
 492         }
 493         else if ((code [0] == 0xff) && (code [1] == 0x15)) {
 494                 /* call *<OFFSET>(%rip) */
 495                 *(guint32*)(code + 2) = ((guint32)(guint64)target) - 7;
 496         }
 497         else if ((code [0] == 0xe8)) {
 498                 /* call <DISP> */
 499                 gint64 disp = (guint8*)target - (guint8*)code;
 500                 g_assert (amd64_is_imm32 (disp));
 501                 x86_patch (code, (unsigned char*)target);
 502         }
 503         else
 504                 x86_patch (code, (unsigned char*)target);
 505 }
 506
 507 void
 508 mono_amd64_patch (unsigned char* code, gpointer target)
 509 {
 510         amd64_patch (code, target);
 511 }
 512
 513 typedef enum {
 514         ArgInIReg,
 515         ArgInFloatSSEReg,
 516         ArgInDoubleSSEReg,
 517         ArgOnStack,
 518         ArgValuetypeInReg,
 519         ArgValuetypeAddrInIReg,
 520         ArgNone /* only in pair_storage */
 521 } ArgStorage;
 522
 523 typedef struct {
 524         gint16 offset;
 525         gint8  reg;
 526         ArgStorage storage;
 527
 528         /* Only if storage == ArgValuetypeInReg */
 529         ArgStorage pair_storage [2];
 530         gint8 pair_regs [2];
 531 } ArgInfo;
 532
 533 typedef struct {
 534         int nargs;
 535         guint32 stack_usage;
 536         guint32 reg_usage;
 537         guint32 freg_usage;
 538         gboolean need_stack_align;
 539         gboolean vtype_retaddr;
 540         /* The index of the vret arg in the argument list */
 541         int vret_arg_index;
 542         ArgInfo ret;
 543         ArgInfo sig_cookie;
 544         ArgInfo args [1];
 545 } CallInfo;
 546
 547 #define DEBUG(a) if (cfg->verbose_level > 1) a
 548
 549 #ifdef HOST_WIN32
 550 #define PARAM_REGS 4
 551
 552 static AMD64_Reg_No param_regs [] = { AMD64_RCX, AMD64_RDX, AMD64_R8, AMD64_R9 };
 553
 554 static AMD64_Reg_No return_regs [] = { AMD64_RAX, AMD64_RDX };
 555 #else
 556 #define PARAM_REGS 6
 557
 558 static AMD64_Reg_No param_regs [] = { AMD64_RDI, AMD64_RSI, AMD64_RDX, AMD64_RCX, AMD64_R8, AMD64_R9 };
 559
 560  static AMD64_Reg_No return_regs [] = { AMD64_RAX, AMD64_RDX };
 561 #endif
 562
 563 static void inline
 564 add_general (guint32 *gr, guint32 *stack_size, ArgInfo *ainfo)
 565 {
 566     ainfo->offset = *stack_size;
 567
 568     if (*gr >= PARAM_REGS) {
 569                 ainfo->storage = ArgOnStack;
 570                 /* Since the same stack slot size is used for all arg */
 571                 /*  types, it needs to be big enough to hold them all */
 572                 (*stack_size) += sizeof(mgreg_t);
 573     }
 574     else {
 575                 ainfo->storage = ArgInIReg;
 576                 ainfo->reg = param_regs [*gr];
 577                 (*gr) ++;
 578     }
 579 }
 580
 581 #ifdef HOST_WIN32
 582 #define FLOAT_PARAM_REGS 4
 583 #else
 584 #define FLOAT_PARAM_REGS 8
 585 #endif
 586
 587 static void inline
 588 add_float (guint32 *gr, guint32 *stack_size, ArgInfo *ainfo, gboolean is_double)
 589 {
 590     ainfo->offset = *stack_size;
 591
 592     if (*gr >= FLOAT_PARAM_REGS) {
 593                 ainfo->storage = ArgOnStack;
 594                 /* Since the same stack slot size is used for both float */
 595                 /*  types, it needs to be big enough to hold them both */
 596                 (*stack_size) += sizeof(mgreg_t);
 597     }
 598     else {
 599                 /* A double register */
 600                 if (is_double)
 601                         ainfo->storage = ArgInDoubleSSEReg;
 602                 else
 603                         ainfo->storage = ArgInFloatSSEReg;
 604                 ainfo->reg = *gr;
 605                 (*gr) += 1;
 606     }
 607 }
 608
 609 typedef enum ArgumentClass {
 610         ARG_CLASS_NO_CLASS,
 611         ARG_CLASS_MEMORY,
 612         ARG_CLASS_INTEGER,
 613         ARG_CLASS_SSE
 614 } ArgumentClass;
 615
 616 static ArgumentClass
 617 merge_argument_class_from_type (MonoType *type, ArgumentClass class1)
 618 {
 619         ArgumentClass class2 = ARG_CLASS_NO_CLASS;
 620         MonoType *ptype;
 621
 622         ptype = mini_type_get_underlying_type (NULL, type);
 623         switch (ptype->type) {
 624         case MONO_TYPE_BOOLEAN:
 625         case MONO_TYPE_CHAR:
 626         case MONO_TYPE_I1:
 627         case MONO_TYPE_U1:
 628         case MONO_TYPE_I2:
 629         case MONO_TYPE_U2:
 630         case MONO_TYPE_I4:
 631         case MONO_TYPE_U4:
 632         case MONO_TYPE_I:
 633         case MONO_TYPE_U:
 634         case MONO_TYPE_STRING:
 635         case MONO_TYPE_OBJECT:
 636         case MONO_TYPE_CLASS:
 637         case MONO_TYPE_SZARRAY:
 638         case MONO_TYPE_PTR:
 639         case MONO_TYPE_FNPTR:
 640         case MONO_TYPE_ARRAY:
 641         case MONO_TYPE_I8:
 642         case MONO_TYPE_U8:
 643                 class2 = ARG_CLASS_INTEGER;
 644                 break;
 645         case MONO_TYPE_R4:
 646         case MONO_TYPE_R8:
 647 #ifdef HOST_WIN32
 648                 class2 = ARG_CLASS_INTEGER;
 649 #else
 650                 class2 = ARG_CLASS_SSE;
 651 #endif
 652                 break;
 653
 654         case MONO_TYPE_TYPEDBYREF:
 655                 g_assert_not_reached ();
 656
 657         case MONO_TYPE_GENERICINST:
 658                 if (!mono_type_generic_inst_is_valuetype (ptype)) {
 659                         class2 = ARG_CLASS_INTEGER;
 660                         break;
 661                 }
 662                 /* fall through */
 663         case MONO_TYPE_VALUETYPE: {
 664                 MonoMarshalType *info = mono_marshal_load_type_info (ptype->data.klass);
 665                 int i;
 666
 667                 for (i = 0; i < info->num_fields; ++i) {
 668                         class2 = class1;
 669                         class2 = merge_argument_class_from_type (info->fields [i].field->type, class2);
 670                 }
 671                 break;
 672         }
 673         default:
 674                 g_assert_not_reached ();
 675         }
 676
 677         /* Merge */
 678         if (class1 == class2)
 679                 ;
 680         else if (class1 == ARG_CLASS_NO_CLASS)
 681                 class1 = class2;
 682         else if ((class1 == ARG_CLASS_MEMORY) || (class2 == ARG_CLASS_MEMORY))
 683                 class1 = ARG_CLASS_MEMORY;
 684         else if ((class1 == ARG_CLASS_INTEGER) || (class2 == ARG_CLASS_INTEGER))
 685                 class1 = ARG_CLASS_INTEGER;
 686         else
 687                 class1 = ARG_CLASS_SSE;
 688
 689         return class1;
 690 }
 691 #ifdef __native_client_codegen__
 692 const guint kNaClAlignment = kNaClAlignmentAMD64;
 693 const guint kNaClAlignmentMask = kNaClAlignmentMaskAMD64;
 694
 695 /* Default alignment for Native Client is 32-byte. */
 696 gint8 nacl_align_byte = -32; /* signed version of 0xe0 */
 697
 698 /* mono_arch_nacl_pad: Add pad bytes of alignment instructions at code,  */
 699 /* Check that alignment doesn't cross an alignment boundary.             */
 700 guint8*
 701 mono_arch_nacl_pad(guint8 *code, int pad)
 702 {
 703         const int kMaxPadding = 8; /* see amd64-codegen.h:amd64_padding_size() */
 704
 705         if (pad == 0) return code;
 706         /* assertion: alignment cannot cross a block boundary */
 707         g_assert (((uintptr_t)code & (~kNaClAlignmentMask)) ==
 708                  (((uintptr_t)code + pad - 1) & (~kNaClAlignmentMask)));
 709         while (pad >= kMaxPadding) {
 710                 amd64_padding (code, kMaxPadding);
 711                 pad -= kMaxPadding;
 712         }
 713         if (pad != 0) amd64_padding (code, pad);
 714         return code;
 715 }
 716 #endif
 717
 718 static void
 719 add_valuetype (MonoGenericSharingContext *gsctx, MonoMethodSignature *sig, ArgInfo *ainfo, MonoType *type,
 720                            gboolean is_return,
 721                            guint32 *gr, guint32 *fr, guint32 *stack_size)
 722 {
 723         guint32 size, quad, nquads, i;
 724         /* Keep track of the size used in each quad so we can */
 725         /* use the right size when copying args/return vars.  */
 726         guint32 quadsize [2] = {8, 8};
 727         ArgumentClass args [2];
 728         MonoMarshalType *info = NULL;
 729         MonoClass *klass;
 730         MonoGenericSharingContext tmp_gsctx;
 731         gboolean pass_on_stack = FALSE;
 732
 733         /*
 734          * The gsctx currently contains no data, it is only used for checking whenever
 735          * open types are allowed, some callers like mono_arch_get_argument_info ()
 736          * don't pass it to us, so work around that.
 737          */
 738         if (!gsctx)
 739                 gsctx = &tmp_gsctx;
 740
 741         klass = mono_class_from_mono_type (type);
 742         size = mini_type_stack_size_full (gsctx, &klass->byval_arg, NULL, sig->pinvoke);
 743 #ifndef HOST_WIN32
 744         if (!sig->pinvoke && !disable_vtypes_in_regs && ((is_return && (size == 8)) || (!is_return && (size <= 16)))) {
 745                 /* We pass and return vtypes of size 8 in a register */
 746         } else if (!sig->pinvoke || (size == 0) || (size > 16)) {
 747                 pass_on_stack = TRUE;
 748         }
 749 #else
 750         if (!sig->pinvoke) {
 751                 pass_on_stack = TRUE;
 752         }
 753 #endif
 754
 755         /* If this struct can't be split up naturally into 8-byte */
 756         /* chunks (registers), pass it on the stack.              */
 757         if (sig->pinvoke && !pass_on_stack) {
 758                 info = mono_marshal_load_type_info (klass);
 759                 g_assert(info);
 760                 guint32 align;
 761                 guint32 field_size;
 762                 for (i = 0; i < info->num_fields; ++i) {
 763                         field_size = mono_marshal_type_size (info->fields [i].field->type,
 764                                                            info->fields [i].mspec,
 765                                                            &align, TRUE, klass->unicode);
 766                         if ((info->fields [i].offset < 8) && (info->fields [i].offset + field_size) > 8) {
 767                                 pass_on_stack = TRUE;
 768                                 break;
 769                         }
 770                 }
 771         }
 772
 773         if (pass_on_stack) {
 774                 /* Allways pass in memory */
 775                 ainfo->offset = *stack_size;
 776                 *stack_size += ALIGN_TO (size, 8);
 777                 ainfo->storage = ArgOnStack;
 778
 779                 return;
 780         }
 781
 782         /* FIXME: Handle structs smaller than 8 bytes */
 783         //if ((size % 8) != 0)
 784         //      NOT_IMPLEMENTED;
 785
 786         if (size > 8)
 787                 nquads = 2;
 788         else
 789                 nquads = 1;
 790
 791         if (!sig->pinvoke) {
 792                 /* Always pass in 1 or 2 integer registers */
 793                 args [0] = ARG_CLASS_INTEGER;
 794                 args [1] = ARG_CLASS_INTEGER;
 795                 /* Only the simplest cases are supported */
 796                 if (is_return && nquads != 1) {
 797                         args [0] = ARG_CLASS_MEMORY;
 798                         args [1] = ARG_CLASS_MEMORY;
 799                 }
 800         } else {
 801                 /*
 802                  * Implement the algorithm from section 3.2.3 of the X86_64 ABI.
 803                  * The X87 and SSEUP stuff is left out since there are no such types in
 804                  * the CLR.
 805                  */
 806                 info = mono_marshal_load_type_info (klass);
 807                 g_assert (info);
 808
 809 #ifndef HOST_WIN32
 810                 if (info->native_size > 16) {
 811                         ainfo->offset = *stack_size;
 812                         *stack_size += ALIGN_TO (info->native_size, 8);
 813                         ainfo->storage = ArgOnStack;
 814
 815                         return;
 816                 }
 817 #else
 818                 switch (info->native_size) {
 819                 case 1: case 2: case 4: case 8:
 820                         break;
 821                 default:
 822                         if (is_return) {
 823                                 ainfo->storage = ArgOnStack;
 824                                 ainfo->offset = *stack_size;
 825                                 *stack_size += ALIGN_TO (info->native_size, 8);
 826                         }
 827                         else {
 828                                 ainfo->storage = ArgValuetypeAddrInIReg;
 829
 830                                 if (*gr < PARAM_REGS) {
 831                                         ainfo->pair_storage [0] = ArgInIReg;
 832                                         ainfo->pair_regs [0] = param_regs [*gr];
 833                                         (*gr) ++;
 834                                 }
 835                                 else {
 836                                         ainfo->pair_storage [0] = ArgOnStack;
 837                                         ainfo->offset = *stack_size;
 838                                         *stack_size += 8;
 839                                 }
 840                         }
 841
 842                         return;
 843                 }
 844 #endif
 845
 846                 args [0] = ARG_CLASS_NO_CLASS;
 847                 args [1] = ARG_CLASS_NO_CLASS;
 848                 for (quad = 0; quad < nquads; ++quad) {
 849                         int size;
 850                         guint32 align;
 851                         ArgumentClass class1;
 852
 853                         if (info->num_fields == 0)
 854                                 class1 = ARG_CLASS_MEMORY;
 855                         else
 856                                 class1 = ARG_CLASS_NO_CLASS;
 857                         for (i = 0; i < info->num_fields; ++i) {
 858                                 size = mono_marshal_type_size (info->fields [i].field->type,
 859                                                                                            info->fields [i].mspec,
 860                                                                                            &align, TRUE, klass->unicode);
 861                                 if ((info->fields [i].offset < 8) && (info->fields [i].offset + size) > 8) {
 862                                         /* Unaligned field */
 863                                         NOT_IMPLEMENTED;
 864                                 }
 865
 866                                 /* Skip fields in other quad */
 867                                 if ((quad == 0) && (info->fields [i].offset >= 8))
 868                                         continue;
 869                                 if ((quad == 1) && (info->fields [i].offset < 8))
 870                                         continue;
 871
 872                                 /* How far into this quad this data extends.*/
 873                                 /* (8 is size of quad) */
 874                                 quadsize [quad] = info->fields [i].offset + size - (quad * 8);
 875
 876                                 class1 = merge_argument_class_from_type (info->fields [i].field->type, class1);
 877                         }
 878                         g_assert (class1 != ARG_CLASS_NO_CLASS);
 879                         args [quad] = class1;
 880                 }
 881         }
 882
 883         /* Post merger cleanup */
 884         if ((args [0] == ARG_CLASS_MEMORY) || (args [1] == ARG_CLASS_MEMORY))
 885                 args [0] = args [1] = ARG_CLASS_MEMORY;
 886
 887         /* Allocate registers */
 888         {
 889                 int orig_gr = *gr;
 890                 int orig_fr = *fr;
 891
 892                 ainfo->storage = ArgValuetypeInReg;
 893                 ainfo->pair_storage [0] = ainfo->pair_storage [1] = ArgNone;
 894                 for (quad = 0; quad < nquads; ++quad) {
 895                         switch (args [quad]) {
 896                         case ARG_CLASS_INTEGER:
 897                                 if (*gr >= PARAM_REGS)
 898                                         args [quad] = ARG_CLASS_MEMORY;
 899                                 else {
 900                                         ainfo->pair_storage [quad] = ArgInIReg;
 901                                         if (is_return)
 902                                                 ainfo->pair_regs [quad] = return_regs [*gr];
 903                                         else
 904                                                 ainfo->pair_regs [quad] = param_regs [*gr];
 905                                         (*gr) ++;
 906                                 }
 907                                 break;
 908                         case ARG_CLASS_SSE:
 909                                 if (*fr >= FLOAT_PARAM_REGS)
 910                                         args [quad] = ARG_CLASS_MEMORY;
 911                                 else {
 912                                         if (quadsize[quad] <= 4)
 913                                                 ainfo->pair_storage [quad] = ArgInFloatSSEReg;
 914                                         else ainfo->pair_storage [quad] = ArgInDoubleSSEReg;
 915                                         ainfo->pair_regs [quad] = *fr;
 916                                         (*fr) ++;
 917                                 }
 918                                 break;
 919                         case ARG_CLASS_MEMORY:
 920                                 break;
 921                         default:
 922                                 g_assert_not_reached ();
 923                         }
 924                 }
 925
 926                 if ((args [0] == ARG_CLASS_MEMORY) || (args [1] == ARG_CLASS_MEMORY)) {
 927                         /* Revert possible register assignments */
 928                         *gr = orig_gr;
 929                         *fr = orig_fr;
 930
 931                         ainfo->offset = *stack_size;
 932                         if (sig->pinvoke)
 933                                 *stack_size += ALIGN_TO (info->native_size, 8);
 934                         else
 935                                 *stack_size += nquads * sizeof(mgreg_t);
 936                         ainfo->storage = ArgOnStack;
 937                 }
 938         }
 939 }
 940
 941 /*
 942  * get_call_info:
 943  *
 944  *  Obtain information about a call according to the calling convention.
 945  * For AMD64, see the "System V ABI, x86-64 Architecture Processor Supplement
 946  * Draft Version 0.23" document for more information.
 947  */
 948 static CallInfo*
 949 get_call_info (MonoGenericSharingContext *gsctx, MonoMemPool *mp, MonoMethodSignature *sig)
 950 {
 951         guint32 i, gr, fr, pstart;
 952         MonoType *ret_type;
 953         int n = sig->hasthis + sig->param_count;
 954         guint32 stack_size = 0;
 955         CallInfo *cinfo;
 956         gboolean is_pinvoke = sig->pinvoke;
 957
 958         if (mp)
 959                 cinfo = mono_mempool_alloc0 (mp, sizeof (CallInfo) + (sizeof (ArgInfo) * n));
 960         else
 961                 cinfo = g_malloc0 (sizeof (CallInfo) + (sizeof (ArgInfo) * n));
 962
 963         cinfo->nargs = n;
 964
 965         gr = 0;
 966         fr = 0;
 967
 968         /* return value */
 969         {
 970                 ret_type = mini_type_get_underlying_type (gsctx, sig->ret);
 971                 switch (ret_type->type) {
 972                 case MONO_TYPE_BOOLEAN:
 973                 case MONO_TYPE_I1:
 974                 case MONO_TYPE_U1:
 975                 case MONO_TYPE_I2:
 976                 case MONO_TYPE_U2:
 977                 case MONO_TYPE_CHAR:
 978                 case MONO_TYPE_I4:
 979                 case MONO_TYPE_U4:
 980                 case MONO_TYPE_I:
 981                 case MONO_TYPE_U:
 982                 case MONO_TYPE_PTR:
 983                 case MONO_TYPE_FNPTR:
 984                 case MONO_TYPE_CLASS:
 985                 case MONO_TYPE_OBJECT:
 986                 case MONO_TYPE_SZARRAY:
 987                 case MONO_TYPE_ARRAY:
 988                 case MONO_TYPE_STRING:
 989                         cinfo->ret.storage = ArgInIReg;
 990                         cinfo->ret.reg = AMD64_RAX;
 991                         break;
 992                 case MONO_TYPE_U8:
 993                 case MONO_TYPE_I8:
 994                         cinfo->ret.storage = ArgInIReg;
 995                         cinfo->ret.reg = AMD64_RAX;
 996                         break;
 997                 case MONO_TYPE_R4:
 998                         cinfo->ret.storage = ArgInFloatSSEReg;
 999                         cinfo->ret.reg = AMD64_XMM0;
1000                         break;
1001                 case MONO_TYPE_R8:
1002                         cinfo->ret.storage = ArgInDoubleSSEReg;
1003                         cinfo->ret.reg = AMD64_XMM0;
1004                         break;
1005                 case MONO_TYPE_GENERICINST:
1006                         if (!mono_type_generic_inst_is_valuetype (ret_type)) {
1007                                 cinfo->ret.storage = ArgInIReg;
1008                                 cinfo->ret.reg = AMD64_RAX;
1009                                 break;
1010                         }
1011                         /* fall through */
1012                 case MONO_TYPE_VALUETYPE: {
1013                         guint32 tmp_gr = 0, tmp_fr = 0, tmp_stacksize = 0;
1014
1015                         add_valuetype (gsctx, sig, &cinfo->ret, sig->ret, TRUE, &tmp_gr, &tmp_fr, &tmp_stacksize);
1016                         if (cinfo->ret.storage == ArgOnStack) {
1017                                 cinfo->vtype_retaddr = TRUE;
1018                                 /* The caller passes the address where the value is stored */
1019                         }
1020                         break;
1021                 }
1022                 case MONO_TYPE_TYPEDBYREF:
1023                         /* Same as a valuetype with size 24 */
1024                         cinfo->vtype_retaddr = TRUE;
1025                         break;
1026                 case MONO_TYPE_VOID:
1027                         break;
1028                 default:
1029                         g_error ("Can't handle as return value 0x%x", sig->ret->type);
1030                 }
1031         }
1032
1033         pstart = 0;
1034         /*
1035          * To simplify get_this_arg_reg () and LLVM integration, emit the vret arg after
1036          * the first argument, allowing 'this' to be always passed in the first arg reg.
1037          * Also do this if the first argument is a reference type, since virtual calls
1038          * are sometimes made using calli without sig->hasthis set, like in the delegate
1039          * invoke wrappers.
1040          */
1041         if (cinfo->vtype_retaddr && !is_pinvoke && (sig->hasthis || (sig->param_count > 0 && MONO_TYPE_IS_REFERENCE (mini_type_get_underlying_type (gsctx, sig->params [0]))))) {
1042                 if (sig->hasthis) {
1043                         add_general (&gr, &stack_size, cinfo->args + 0);
1044                 } else {
1045                         add_general (&gr, &stack_size, &cinfo->args [sig->hasthis + 0]);
1046                         pstart = 1;
1047                 }
1048                 add_general (&gr, &stack_size, &cinfo->ret);
1049                 cinfo->vret_arg_index = 1;
1050         } else {
1051                 /* this */
1052                 if (sig->hasthis)
1053                         add_general (&gr, &stack_size, cinfo->args + 0);
1054
1055                 if (cinfo->vtype_retaddr)
1056                         add_general (&gr, &stack_size, &cinfo->ret);
1057         }
1058
1059         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n == 0)) {
1060                 gr = PARAM_REGS;
1061                 fr = FLOAT_PARAM_REGS;
1062
1063                 /* Emit the signature cookie just before the implicit arguments */
1064                 add_general (&gr, &stack_size, &cinfo->sig_cookie);
1065         }
1066
1067         for (i = pstart; i < sig->param_count; ++i) {
1068                 ArgInfo *ainfo = &cinfo->args [sig->hasthis + i];
1069                 MonoType *ptype;
1070
1071 #ifdef HOST_WIN32
1072                 /* The float param registers and other param registers must be the same index on Windows x64.*/
1073                 if (gr > fr)
1074                         fr = gr;
1075                 else if (fr > gr)
1076                         gr = fr;
1077 #endif
1078
1079                 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos)) {
1080                         /* We allways pass the sig cookie on the stack for simplicity */
1081                         /*
1082                          * Prevent implicit arguments + the sig cookie from being passed
1083                          * in registers.
1084                          */
1085                         gr = PARAM_REGS;
1086                         fr = FLOAT_PARAM_REGS;
1087
1088                         /* Emit the signature cookie just before the implicit arguments */
1089                         add_general (&gr, &stack_size, &cinfo->sig_cookie);
1090                 }
1091
1092                 ptype = mini_type_get_underlying_type (gsctx, sig->params [i]);
1093                 switch (ptype->type) {
1094                 case MONO_TYPE_BOOLEAN:
1095                 case MONO_TYPE_I1:
1096                 case MONO_TYPE_U1:
1097                         add_general (&gr, &stack_size, ainfo);
1098                         break;
1099                 case MONO_TYPE_I2:
1100                 case MONO_TYPE_U2:
1101                 case MONO_TYPE_CHAR:
1102                         add_general (&gr, &stack_size, ainfo);
1103                         break;
1104                 case MONO_TYPE_I4:
1105                 case MONO_TYPE_U4:
1106                         add_general (&gr, &stack_size, ainfo);
1107                         break;
1108                 case MONO_TYPE_I:
1109                 case MONO_TYPE_U:
1110                 case MONO_TYPE_PTR:
1111                 case MONO_TYPE_FNPTR:
1112                 case MONO_TYPE_CLASS:
1113                 case MONO_TYPE_OBJECT:
1114                 case MONO_TYPE_STRING:
1115                 case MONO_TYPE_SZARRAY:
1116                 case MONO_TYPE_ARRAY:
1117                         add_general (&gr, &stack_size, ainfo);
1118                         break;
1119                 case MONO_TYPE_GENERICINST:
1120                         if (!mono_type_generic_inst_is_valuetype (ptype)) {
1121                                 add_general (&gr, &stack_size, ainfo);
1122                                 break;
1123                         }
1124                         /* fall through */
1125                 case MONO_TYPE_VALUETYPE:
1126                         add_valuetype (gsctx, sig, ainfo, sig->params [i], FALSE, &gr, &fr, &stack_size);
1127                         break;
1128                 case MONO_TYPE_TYPEDBYREF:
1129 #ifdef HOST_WIN32
1130                         add_valuetype (gsctx, sig, ainfo, sig->params [i], FALSE, &gr, &fr, &stack_size);
1131 #else
1132                         stack_size += sizeof (MonoTypedRef);
1133                         ainfo->storage = ArgOnStack;
1134 #endif
1135                         break;
1136                 case MONO_TYPE_U8:
1137                 case MONO_TYPE_I8:
1138                         add_general (&gr, &stack_size, ainfo);
1139                         break;
1140                 case MONO_TYPE_R4:
1141                         add_float (&fr, &stack_size, ainfo, FALSE);
1142                         break;
1143                 case MONO_TYPE_R8:
1144                         add_float (&fr, &stack_size, ainfo, TRUE);
1145                         break;
1146                 default:
1147                         g_assert_not_reached ();
1148                 }
1149         }
1150
1151         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n > 0) && (sig->sentinelpos == sig->param_count)) {
1152                 gr = PARAM_REGS;
1153                 fr = FLOAT_PARAM_REGS;
1154
1155                 /* Emit the signature cookie just before the implicit arguments */
1156                 add_general (&gr, &stack_size, &cinfo->sig_cookie);
1157         }
1158
1159 #ifdef HOST_WIN32
1160         // There always is 32 bytes reserved on the stack when calling on Winx64
1161         stack_size += 0x20;
1162 #endif
1163
1164         if (stack_size & 0x8) {
1165                 /* The AMD64 ABI requires each stack frame to be 16 byte aligned */
1166                 cinfo->need_stack_align = TRUE;
1167                 stack_size += 8;
1168         }
1169
1170         cinfo->stack_usage = stack_size;
1171         cinfo->reg_usage = gr;
1172         cinfo->freg_usage = fr;
1173         return cinfo;
1174 }
1175
1176 /*
1177  * mono_arch_get_argument_info:
1178  * @csig:  a method signature
1179  * @param_count: the number of parameters to consider
1180  * @arg_info: an array to store the result infos
1181  *
1182  * Gathers information on parameters such as size, alignment and
1183  * padding. arg_info should be large enought to hold param_count + 1 entries.
1184  *
1185  * Returns the size of the argument area on the stack.
1186  */
1187 int
1188 mono_arch_get_argument_info (MonoMethodSignature *csig, int param_count, MonoJitArgumentInfo *arg_info)
1189 {
1190         int k;
1191         CallInfo *cinfo = get_call_info (NULL, NULL, csig);
1192         guint32 args_size = cinfo->stack_usage;
1193
1194         /* The arguments are saved to a stack area in mono_arch_instrument_prolog */
1195         if (csig->hasthis) {
1196                 arg_info [0].offset = 0;
1197         }
1198
1199         for (k = 0; k < param_count; k++) {
1200                 arg_info [k + 1].offset = ((k + csig->hasthis) * 8);
1201                 /* FIXME: */
1202                 arg_info [k + 1].size = 0;
1203         }
1204
1205         g_free (cinfo);
1206
1207         return args_size;
1208 }
1209
1210 gboolean
1211 mono_amd64_tail_call_supported (MonoMethodSignature *caller_sig, MonoMethodSignature *callee_sig)
1212 {
1213         CallInfo *c1, *c2;
1214         gboolean res;
1215
1216         c1 = get_call_info (NULL, NULL, caller_sig);
1217         c2 = get_call_info (NULL, NULL, callee_sig);
1218         res = c1->stack_usage >= c2->stack_usage;
1219         if (callee_sig->ret && MONO_TYPE_ISSTRUCT (callee_sig->ret) && c2->ret.storage != ArgValuetypeInReg)
1220                 /* An address on the callee's stack is passed as the first argument */
1221                 res = FALSE;
1222
1223         g_free (c1);
1224         g_free (c2);
1225
1226         return res;
1227 }
1228
1229 static int
1230 cpuid (int id, int* p_eax, int* p_ebx, int* p_ecx, int* p_edx)
1231 {
1232 #if defined(MONO_CROSS_COMPILE)
1233         return 0;
1234 #else
1235 #ifndef _MSC_VER
1236         __asm__ __volatile__ ("cpuid"
1237                 : "=a" (*p_eax), "=b" (*p_ebx), "=c" (*p_ecx), "=d" (*p_edx)
1238                 : "a" (id));
1239 #else
1240         int info[4];
1241         __cpuid(info, id);
1242         *p_eax = info[0];
1243         *p_ebx = info[1];
1244         *p_ecx = info[2];
1245         *p_edx = info[3];
1246 #endif
1247         return 1;
1248 #endif
1249 }
1250
1251 /*
1252  * Initialize the cpu to execute managed code.
1253  */
1254 void
1255 mono_arch_cpu_init (void)
1256 {
1257 #ifndef _MSC_VER
1258         guint16 fpcw;
1259
1260         /* spec compliance requires running with double precision */
1261         __asm__  __volatile__ ("fnstcw %0\n": "=m" (fpcw));
1262         fpcw &= ~X86_FPCW_PRECC_MASK;
1263         fpcw |= X86_FPCW_PREC_DOUBLE;
1264         __asm__  __volatile__ ("fldcw %0\n": : "m" (fpcw));
1265         __asm__  __volatile__ ("fnstcw %0\n": "=m" (fpcw));
1266 #else
1267         /* TODO: This is crashing on Win64 right now.
1268         * _control87 (_PC_53, MCW_PC);
1269         */
1270 #endif
1271 }
1272
1273 /*
1274  * Initialize architecture specific code.
1275  */
1276 void
1277 mono_arch_init (void)
1278 {
1279         int flags;
1280
1281         InitializeCriticalSection (&mini_arch_mutex);
1282 #if defined(__native_client_codegen__)
1283         nacl_instruction_depth = TlsAlloc ();
1284         TlsSetValue (nacl_instruction_depth, (gpointer)0);
1285         nacl_rex_tag = TlsAlloc ();
1286         nacl_legacy_prefix_tag = TlsAlloc ();
1287 #endif
1288
1289 #ifdef MONO_ARCH_NOMAP32BIT
1290         flags = MONO_MMAP_READ;
1291         /* amd64_mov_reg_imm () + amd64_mov_reg_membase () */
1292         breakpoint_size = 13;
1293         breakpoint_fault_size = 3;
1294         /* amd64_alu_membase_imm_size (code, X86_CMP, AMD64_R11, 0, 0, 4); */
1295         single_step_fault_size = 5;
1296 #else
1297         flags = MONO_MMAP_READ|MONO_MMAP_32BIT;
1298         /* amd64_mov_reg_mem () */
1299         breakpoint_size = 8;
1300         breakpoint_fault_size = 8;
1301         single_step_fault_size = 8;
1302 #endif
1303
1304         ss_trigger_page = mono_valloc (NULL, mono_pagesize (), flags);
1305         bp_trigger_page = mono_valloc (NULL, mono_pagesize (), flags);
1306         mono_mprotect (bp_trigger_page, mono_pagesize (), 0);
1307
1308         mono_aot_register_jit_icall ("mono_amd64_throw_exception", mono_amd64_throw_exception);
1309         mono_aot_register_jit_icall ("mono_amd64_throw_corlib_exception", mono_amd64_throw_corlib_exception);
1310         mono_aot_register_jit_icall ("mono_amd64_get_original_ip", mono_amd64_get_original_ip);
1311 }
1312
1313 /*
1314  * Cleanup architecture specific code.
1315  */
1316 void
1317 mono_arch_cleanup (void)
1318 {
1319         DeleteCriticalSection (&mini_arch_mutex);
1320 #if defined(__native_client_codegen__)
1321         TlsFree (nacl_instruction_depth);
1322         TlsFree (nacl_rex_tag);
1323         TlsFree (nacl_legacy_prefix_tag);
1324 #endif
1325 }
1326
1327 /*
1328  * This function returns the optimizations supported on this cpu.
1329  */
1330 guint32
1331 mono_arch_cpu_optimizazions (guint32 *exclude_mask)
1332 {
1333         int eax, ebx, ecx, edx;
1334         guint32 opts = 0;
1335
1336         *exclude_mask = 0;
1337         /* Feature Flags function, flags returned in EDX. */
1338         if (cpuid (1, &eax, &ebx, &ecx, &edx)) {
1339                 if (edx & (1 << 15)) {
1340                         opts |= MONO_OPT_CMOV;
1341                         if (edx & 1)
1342                                 opts |= MONO_OPT_FCMOV;
1343                         else
1344                                 *exclude_mask |= MONO_OPT_FCMOV;
1345                 } else
1346                         *exclude_mask |= MONO_OPT_CMOV;
1347         }
1348
1349         return opts;
1350 }
1351
1352 /*
1353  * This function test for all SSE functions supported.
1354  *
1355  * Returns a bitmask corresponding to all supported versions.
1356  *
1357  */
1358 guint32
1359 mono_arch_cpu_enumerate_simd_versions (void)
1360 {
1361         int eax, ebx, ecx, edx;
1362         guint32 sse_opts = 0;
1363
1364         if (cpuid (1, &eax, &ebx, &ecx, &edx)) {
1365                 if (edx & (1 << 25))
1366                         sse_opts |= SIMD_VERSION_SSE1;
1367                 if (edx & (1 << 26))
1368                         sse_opts |= SIMD_VERSION_SSE2;
1369                 if (ecx & (1 << 0))
1370                         sse_opts |= SIMD_VERSION_SSE3;
1371                 if (ecx & (1 << 9))
1372                         sse_opts |= SIMD_VERSION_SSSE3;
1373                 if (ecx & (1 << 19))
1374                         sse_opts |= SIMD_VERSION_SSE41;
1375                 if (ecx & (1 << 20))
1376                         sse_opts |= SIMD_VERSION_SSE42;
1377         }
1378
1379         /* Yes, all this needs to be done to check for sse4a.
1380            See: "Amd: CPUID Specification"
1381          */
1382         if (cpuid (0x80000000, &eax, &ebx, &ecx, &edx)) {
1383                 /* eax greater or equal than 0x80000001, ebx = 'htuA', ecx = DMAc', edx = 'itne'*/
1384                 if ((((unsigned int) eax) >= 0x80000001) && (ebx == 0x68747541) && (ecx == 0x444D4163) && (edx == 0x69746E65)) {
1385                         cpuid (0x80000001, &eax, &ebx, &ecx, &edx);
1386                         if (ecx & (1 << 6))
1387                                 sse_opts |= SIMD_VERSION_SSE4a;
1388                 }
1389         }
1390
1391         return sse_opts;
1392 }
1393
1394 #ifndef DISABLE_JIT
1395
1396 GList *
1397 mono_arch_get_allocatable_int_vars (MonoCompile *cfg)
1398 {
1399         GList *vars = NULL;
1400         int i;
1401
1402         for (i = 0; i < cfg->num_varinfo; i++) {
1403                 MonoInst *ins = cfg->varinfo [i];
1404                 MonoMethodVar *vmv = MONO_VARINFO (cfg, i);
1405
1406                 /* unused vars */
1407                 if (vmv->range.first_use.abs_pos >= vmv->range.last_use.abs_pos)
1408                         continue;
1409
1410                 if ((ins->flags & (MONO_INST_IS_DEAD|MONO_INST_VOLATILE|MONO_INST_INDIRECT)) ||
1411                     (ins->opcode != OP_LOCAL && ins->opcode != OP_ARG))
1412                         continue;
1413
1414                 if (mono_is_regsize_var (ins->inst_vtype)) {
1415                         g_assert (MONO_VARINFO (cfg, i)->reg == -1);
1416                         g_assert (i == vmv->idx);
1417                         vars = g_list_prepend (vars, vmv);
1418                 }
1419         }
1420
1421         vars = mono_varlist_sort (cfg, vars, 0);
1422
1423         return vars;
1424 }
1425
1426 /**
1427  * mono_arch_compute_omit_fp:
1428  *
1429  *   Determine whenever the frame pointer can be eliminated.
1430  */
1431 static void
1432 mono_arch_compute_omit_fp (MonoCompile *cfg)
1433 {
1434         MonoMethodSignature *sig;
1435         MonoMethodHeader *header;
1436         int i, locals_size;
1437         CallInfo *cinfo;
1438
1439         if (cfg->arch.omit_fp_computed)
1440                 return;
1441
1442         header = cfg->header;
1443
1444         sig = mono_method_signature (cfg->method);
1445
1446         if (!cfg->arch.cinfo)
1447                 cfg->arch.cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig);
1448         cinfo = cfg->arch.cinfo;
1449
1450         /*
1451          * FIXME: Remove some of the restrictions.
1452          */
1453         cfg->arch.omit_fp = TRUE;
1454         cfg->arch.omit_fp_computed = TRUE;
1455
1456 #ifdef __native_client_codegen__
1457         /* NaCl modules may not change the value of RBP, so it cannot be */
1458         /* used as a normal register, but it can be used as a frame pointer*/
1459         cfg->disable_omit_fp = TRUE;
1460         cfg->arch.omit_fp = FALSE;
1461 #endif
1462
1463         if (cfg->disable_omit_fp)
1464                 cfg->arch.omit_fp = FALSE;
1465
1466         if (!debug_omit_fp ())
1467                 cfg->arch.omit_fp = FALSE;
1468         /*
1469         if (cfg->method->save_lmf)
1470                 cfg->arch.omit_fp = FALSE;
1471         */
1472         if (cfg->flags & MONO_CFG_HAS_ALLOCA)
1473                 cfg->arch.omit_fp = FALSE;
1474         if (header->num_clauses)
1475                 cfg->arch.omit_fp = FALSE;
1476         if (cfg->param_area)
1477                 cfg->arch.omit_fp = FALSE;
1478         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG))
1479                 cfg->arch.omit_fp = FALSE;
1480         if ((mono_jit_trace_calls != NULL && mono_trace_eval (cfg->method)) ||
1481                 (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE))
1482                 cfg->arch.omit_fp = FALSE;
1483         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1484                 ArgInfo *ainfo = &cinfo->args [i];
1485
1486                 if (ainfo->storage == ArgOnStack) {
1487                         /*
1488                          * The stack offset can only be determined when the frame
1489                          * size is known.
1490                          */
1491                         cfg->arch.omit_fp = FALSE;
1492                 }
1493         }
1494
1495         locals_size = 0;
1496         for (i = cfg->locals_start; i < cfg->num_varinfo; i++) {
1497                 MonoInst *ins = cfg->varinfo [i];
1498                 int ialign;
1499
1500                 locals_size += mono_type_size (ins->inst_vtype, &ialign);
1501         }
1502 }
1503
1504 GList *
1505 mono_arch_get_global_int_regs (MonoCompile *cfg)
1506 {
1507         GList *regs = NULL;
1508
1509         mono_arch_compute_omit_fp (cfg);
1510
1511         if (cfg->globalra) {
1512                 if (cfg->arch.omit_fp)
1513                         regs = g_list_prepend (regs, (gpointer)AMD64_RBP);
1514
1515                 regs = g_list_prepend (regs, (gpointer)AMD64_RBX);
1516                 regs = g_list_prepend (regs, (gpointer)AMD64_R12);
1517                 regs = g_list_prepend (regs, (gpointer)AMD64_R13);
1518                 regs = g_list_prepend (regs, (gpointer)AMD64_R14);
1519 #ifndef __native_client_codegen__
1520                 regs = g_list_prepend (regs, (gpointer)AMD64_R15);
1521 #endif
1522
1523                 regs = g_list_prepend (regs, (gpointer)AMD64_R10);
1524                 regs = g_list_prepend (regs, (gpointer)AMD64_R9);
1525                 regs = g_list_prepend (regs, (gpointer)AMD64_R8);
1526                 regs = g_list_prepend (regs, (gpointer)AMD64_RDI);
1527                 regs = g_list_prepend (regs, (gpointer)AMD64_RSI);
1528                 regs = g_list_prepend (regs, (gpointer)AMD64_RDX);
1529                 regs = g_list_prepend (regs, (gpointer)AMD64_RCX);
1530                 regs = g_list_prepend (regs, (gpointer)AMD64_RAX);
1531         } else {
1532                 if (cfg->arch.omit_fp)
1533                         regs = g_list_prepend (regs, (gpointer)AMD64_RBP);
1534
1535                 /* We use the callee saved registers for global allocation */
1536                 regs = g_list_prepend (regs, (gpointer)AMD64_RBX);
1537                 regs = g_list_prepend (regs, (gpointer)AMD64_R12);
1538                 regs = g_list_prepend (regs, (gpointer)AMD64_R13);
1539                 regs = g_list_prepend (regs, (gpointer)AMD64_R14);
1540 #ifndef __native_client_codegen__
1541                 regs = g_list_prepend (regs, (gpointer)AMD64_R15);
1542 #endif
1543 #ifdef HOST_WIN32
1544                 regs = g_list_prepend (regs, (gpointer)AMD64_RDI);
1545                 regs = g_list_prepend (regs, (gpointer)AMD64_RSI);
1546 #endif
1547         }
1548
1549         return regs;
1550 }
1551
1552 GList*
1553 mono_arch_get_global_fp_regs (MonoCompile *cfg)
1554 {
1555         GList *regs = NULL;
1556         int i;
1557
1558         /* All XMM registers */
1559         for (i = 0; i < 16; ++i)
1560                 regs = g_list_prepend (regs, GINT_TO_POINTER (i));
1561
1562         return regs;
1563 }
1564
1565 GList*
1566 mono_arch_get_iregs_clobbered_by_call (MonoCallInst *call)
1567 {
1568         static GList *r = NULL;
1569
1570         if (r == NULL) {
1571                 GList *regs = NULL;
1572
1573                 regs = g_list_prepend (regs, (gpointer)AMD64_RBP);
1574                 regs = g_list_prepend (regs, (gpointer)AMD64_RBX);
1575                 regs = g_list_prepend (regs, (gpointer)AMD64_R12);
1576                 regs = g_list_prepend (regs, (gpointer)AMD64_R13);
1577                 regs = g_list_prepend (regs, (gpointer)AMD64_R14);
1578 #ifndef __native_client_codegen__
1579                 regs = g_list_prepend (regs, (gpointer)AMD64_R15);
1580 #endif
1581
1582                 regs = g_list_prepend (regs, (gpointer)AMD64_R10);
1583                 regs = g_list_prepend (regs, (gpointer)AMD64_R9);
1584                 regs = g_list_prepend (regs, (gpointer)AMD64_R8);
1585                 regs = g_list_prepend (regs, (gpointer)AMD64_RDI);
1586                 regs = g_list_prepend (regs, (gpointer)AMD64_RSI);
1587                 regs = g_list_prepend (regs, (gpointer)AMD64_RDX);
1588                 regs = g_list_prepend (regs, (gpointer)AMD64_RCX);
1589                 regs = g_list_prepend (regs, (gpointer)AMD64_RAX);
1590
1591                 InterlockedCompareExchangePointer ((gpointer*)&r, regs, NULL);
1592         }
1593
1594         return r;
1595 }
1596
1597 GList*
1598 mono_arch_get_fregs_clobbered_by_call (MonoCallInst *call)
1599 {
1600         int i;
1601         static GList *r = NULL;
1602
1603         if (r == NULL) {
1604                 GList *regs = NULL;
1605
1606                 for (i = 0; i < AMD64_XMM_NREG; ++i)
1607                         regs = g_list_prepend (regs, GINT_TO_POINTER (MONO_MAX_IREGS + i));
1608
1609                 InterlockedCompareExchangePointer ((gpointer*)&r, regs, NULL);
1610         }
1611
1612         return r;
1613 }
1614
1615 /*
1616  * mono_arch_regalloc_cost:
1617  *
1618  *  Return the cost, in number of memory references, of the action of
1619  * allocating the variable VMV into a register during global register
1620  * allocation.
1621  */
1622 guint32
1623 mono_arch_regalloc_cost (MonoCompile *cfg, MonoMethodVar *vmv)
1624 {
1625         MonoInst *ins = cfg->varinfo [vmv->idx];
1626
1627         if (cfg->method->save_lmf)
1628                 /* The register is already saved */
1629                 /* substract 1 for the invisible store in the prolog */
1630                 return (ins->opcode == OP_ARG) ? 0 : 1;
1631         else
1632                 /* push+pop */
1633                 return (ins->opcode == OP_ARG) ? 1 : 2;
1634 }
1635
1636 /*
1637  * mono_arch_fill_argument_info:
1638  *
1639  *   Populate cfg->args, cfg->ret and cfg->vret_addr with information about the arguments
1640  * of the method.
1641  */
1642 void
1643 mono_arch_fill_argument_info (MonoCompile *cfg)
1644 {
1645         MonoMethodSignature *sig;
1646         MonoMethodHeader *header;
1647         MonoInst *ins;
1648         int i;
1649         CallInfo *cinfo;
1650
1651         header = cfg->header;
1652
1653         sig = mono_method_signature (cfg->method);
1654
1655         cinfo = cfg->arch.cinfo;
1656
1657         /*
1658          * Contrary to mono_arch_allocate_vars (), the information should describe
1659          * where the arguments are at the beginning of the method, not where they can be
1660          * accessed during the execution of the method. The later makes no sense for the
1661          * global register allocator, since a variable can be in more than one location.
1662          */
1663         if (sig->ret->type != MONO_TYPE_VOID) {
1664                 switch (cinfo->ret.storage) {
1665                 case ArgInIReg:
1666                 case ArgInFloatSSEReg:
1667                 case ArgInDoubleSSEReg:
1668                         if ((MONO_TYPE_ISSTRUCT (sig->ret) && !mono_class_from_mono_type (sig->ret)->enumtype) || (sig->ret->type == MONO_TYPE_TYPEDBYREF)) {
1669                                 cfg->vret_addr->opcode = OP_REGVAR;
1670                                 cfg->vret_addr->inst_c0 = cinfo->ret.reg;
1671                         }
1672                         else {
1673                                 cfg->ret->opcode = OP_REGVAR;
1674                                 cfg->ret->inst_c0 = cinfo->ret.reg;
1675                         }
1676                         break;
1677                 case ArgValuetypeInReg:
1678                         cfg->ret->opcode = OP_REGOFFSET;
1679                         cfg->ret->inst_basereg = -1;
1680                         cfg->ret->inst_offset = -1;
1681                         break;
1682                 default:
1683                         g_assert_not_reached ();
1684                 }
1685         }
1686
1687         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1688                 ArgInfo *ainfo = &cinfo->args [i];
1689                 MonoType *arg_type;
1690
1691                 ins = cfg->args [i];
1692
1693                 if (sig->hasthis && (i == 0))
1694                         arg_type = &mono_defaults.object_class->byval_arg;
1695                 else
1696                         arg_type = sig->params [i - sig->hasthis];
1697
1698                 switch (ainfo->storage) {
1699                 case ArgInIReg:
1700                 case ArgInFloatSSEReg:
1701                 case ArgInDoubleSSEReg:
1702                         ins->opcode = OP_REGVAR;
1703                         ins->inst_c0 = ainfo->reg;
1704                         break;
1705                 case ArgOnStack:
1706                         ins->opcode = OP_REGOFFSET;
1707                         ins->inst_basereg = -1;
1708                         ins->inst_offset = -1;
1709                         break;
1710                 case ArgValuetypeInReg:
1711                         /* Dummy */
1712                         ins->opcode = OP_NOP;
1713                         break;
1714                 default:
1715                         g_assert_not_reached ();
1716                 }
1717         }
1718 }
1719
1720 void
1721 mono_arch_allocate_vars (MonoCompile *cfg)
1722 {
1723         MonoMethodSignature *sig;
1724         MonoMethodHeader *header;
1725         MonoInst *ins;
1726         int i, offset;
1727         guint32 locals_stack_size, locals_stack_align;
1728         gint32 *offsets;
1729         CallInfo *cinfo;
1730
1731         header = cfg->header;
1732
1733         sig = mono_method_signature (cfg->method);
1734
1735         cinfo = cfg->arch.cinfo;
1736
1737         mono_arch_compute_omit_fp (cfg);
1738
1739         /*
1740          * We use the ABI calling conventions for managed code as well.
1741          * Exception: valuetypes are only sometimes passed or returned in registers.
1742          */
1743
1744         /*
1745          * The stack looks like this:
1746          * <incoming arguments passed on the stack>
1747          * <return value>
1748          * <lmf/caller saved registers>
1749          * <locals>
1750          * <spill area>
1751          * <localloc area>  -> grows dynamically
1752          * <params area>
1753          */
1754
1755         if (cfg->arch.omit_fp) {
1756                 cfg->flags |= MONO_CFG_HAS_SPILLUP;
1757                 cfg->frame_reg = AMD64_RSP;
1758                 offset = 0;
1759         } else {
1760                 /* Locals are allocated backwards from %fp */
1761                 cfg->frame_reg = AMD64_RBP;
1762                 offset = 0;
1763         }
1764
1765         if (cfg->method->save_lmf) {
1766                 /* Reserve stack space for saving LMF */
1767                 if (cfg->arch.omit_fp) {
1768                         cfg->arch.lmf_offset = offset;
1769                         offset += sizeof (MonoLMF);
1770                 }
1771                 else {
1772                         offset += sizeof (MonoLMF);
1773                         cfg->arch.lmf_offset = -offset;
1774                 }
1775         } else {
1776                 if (cfg->arch.omit_fp)
1777                         cfg->arch.reg_save_area_offset = offset;
1778                 /* Reserve space for caller saved registers */
1779                 for (i = 0; i < AMD64_NREG; ++i)
1780                         if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
1781                                 offset += sizeof(mgreg_t);
1782                         }
1783         }
1784
1785         if (sig->ret->type != MONO_TYPE_VOID) {
1786                 switch (cinfo->ret.storage) {
1787                 case ArgInIReg:
1788                 case ArgInFloatSSEReg:
1789                 case ArgInDoubleSSEReg:
1790                         if ((MONO_TYPE_ISSTRUCT (sig->ret) && !mono_class_from_mono_type (sig->ret)->enumtype) || (sig->ret->type == MONO_TYPE_TYPEDBYREF)) {
1791                                 if (cfg->globalra) {
1792                                         cfg->vret_addr->opcode = OP_REGVAR;
1793                                         cfg->vret_addr->inst_c0 = cinfo->ret.reg;
1794                                 } else {
1795                                         /* The register is volatile */
1796                                         cfg->vret_addr->opcode = OP_REGOFFSET;
1797                                         cfg->vret_addr->inst_basereg = cfg->frame_reg;
1798                                         if (cfg->arch.omit_fp) {
1799                                                 cfg->vret_addr->inst_offset = offset;
1800                                                 offset += 8;
1801                                         } else {
1802                                                 offset += 8;
1803                                                 cfg->vret_addr->inst_offset = -offset;
1804                                         }
1805                                         if (G_UNLIKELY (cfg->verbose_level > 1)) {
1806                                                 printf ("vret_addr =");
1807                                                 mono_print_ins (cfg->vret_addr);
1808                                         }
1809                                 }
1810                         }
1811                         else {
1812                                 cfg->ret->opcode = OP_REGVAR;
1813                                 cfg->ret->inst_c0 = cinfo->ret.reg;
1814                         }
1815                         break;
1816                 case ArgValuetypeInReg:
1817                         /* Allocate a local to hold the result, the epilog will copy it to the correct place */
1818                         cfg->ret->opcode = OP_REGOFFSET;
1819                         cfg->ret->inst_basereg = cfg->frame_reg;
1820                         if (cfg->arch.omit_fp) {
1821                                 cfg->ret->inst_offset = offset;
1822                                 offset += 16;
1823                         } else {
1824                                 offset += 16;
1825                                 cfg->ret->inst_offset = - offset;
1826                         }
1827                         break;
1828                 default:
1829                         g_assert_not_reached ();
1830                 }
1831                 if (!cfg->globalra)
1832                         cfg->ret->dreg = cfg->ret->inst_c0;
1833         }
1834
1835         /* Allocate locals */
1836         if (!cfg->globalra) {
1837                 offsets = mono_allocate_stack_slots_full (cfg, cfg->arch.omit_fp ? FALSE: TRUE, &locals_stack_size, &locals_stack_align);
1838                 if (locals_stack_size > MONO_ARCH_MAX_FRAME_SIZE) {
1839                         char *mname = mono_method_full_name (cfg->method, TRUE);
1840                         cfg->exception_type = MONO_EXCEPTION_INVALID_PROGRAM;
1841                         cfg->exception_message = g_strdup_printf ("Method %s stack is too big.", mname);
1842                         g_free (mname);
1843                         return;
1844                 }
1845
1846                 if (locals_stack_align) {
1847                         offset += (locals_stack_align - 1);
1848                         offset &= ~(locals_stack_align - 1);
1849                 }
1850                 if (cfg->arch.omit_fp) {
1851                         cfg->locals_min_stack_offset = offset;
1852                         cfg->locals_max_stack_offset = offset + locals_stack_size;
1853                 } else {
1854                         cfg->locals_min_stack_offset = - (offset + locals_stack_size);
1855                         cfg->locals_max_stack_offset = - offset;
1856                 }
1857
1858                 for (i = cfg->locals_start; i < cfg->num_varinfo; i++) {
1859                         if (offsets [i] != -1) {
1860                                 MonoInst *ins = cfg->varinfo [i];
1861                                 ins->opcode = OP_REGOFFSET;
1862                                 ins->inst_basereg = cfg->frame_reg;
1863                                 if (cfg->arch.omit_fp)
1864                                         ins->inst_offset = (offset + offsets [i]);
1865                                 else
1866                                         ins->inst_offset = - (offset + offsets [i]);
1867                                 //printf ("allocated local %d to ", i); mono_print_tree_nl (ins);
1868                         }
1869                 }
1870                 offset += locals_stack_size;
1871         }
1872
1873         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG)) {
1874                 g_assert (!cfg->arch.omit_fp);
1875                 g_assert (cinfo->sig_cookie.storage == ArgOnStack);
1876                 cfg->sig_cookie = cinfo->sig_cookie.offset + ARGS_OFFSET;
1877         }
1878
1879         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1880                 ins = cfg->args [i];
1881                 if (ins->opcode != OP_REGVAR) {
1882                         ArgInfo *ainfo = &cinfo->args [i];
1883                         gboolean inreg = TRUE;
1884                         MonoType *arg_type;
1885
1886                         if (sig->hasthis && (i == 0))
1887                                 arg_type = &mono_defaults.object_class->byval_arg;
1888                         else
1889                                 arg_type = sig->params [i - sig->hasthis];
1890
1891                         if (cfg->globalra) {
1892                                 /* The new allocator needs info about the original locations of the arguments */
1893                                 switch (ainfo->storage) {
1894                                 case ArgInIReg:
1895                                 case ArgInFloatSSEReg:
1896                                 case ArgInDoubleSSEReg:
1897                                         ins->opcode = OP_REGVAR;
1898                                         ins->inst_c0 = ainfo->reg;
1899                                         break;
1900                                 case ArgOnStack:
1901                                         g_assert (!cfg->arch.omit_fp);
1902                                         ins->opcode = OP_REGOFFSET;
1903                                         ins->inst_basereg = cfg->frame_reg;
1904                                         ins->inst_offset = ainfo->offset + ARGS_OFFSET;
1905                                         break;
1906                                 case ArgValuetypeInReg:
1907                                         ins->opcode = OP_REGOFFSET;
1908                                         ins->inst_basereg = cfg->frame_reg;
1909                                         /* These arguments are saved to the stack in the prolog */
1910                                         offset = ALIGN_TO (offset, sizeof(mgreg_t));
1911                                         if (cfg->arch.omit_fp) {
1912                                                 ins->inst_offset = offset;
1913                                                 offset += (ainfo->storage == ArgValuetypeInReg) ? 2 * sizeof(mgreg_t) : sizeof(mgreg_t);
1914                                         } else {
1915                                                 offset += (ainfo->storage == ArgValuetypeInReg) ? 2 * sizeof(mgreg_t) : sizeof(mgreg_t);
1916                                                 ins->inst_offset = - offset;
1917                                         }
1918                                         break;
1919                                 default:
1920                                         g_assert_not_reached ();
1921                                 }
1922
1923                                 continue;
1924                         }
1925
1926                         /* FIXME: Allocate volatile arguments to registers */
1927                         if (ins->flags & (MONO_INST_VOLATILE|MONO_INST_INDIRECT))
1928                                 inreg = FALSE;
1929
1930                         /*
1931                          * Under AMD64, all registers used to pass arguments to functions
1932                          * are volatile across calls.
1933                          * FIXME: Optimize this.
1934                          */
1935                         if ((ainfo->storage == ArgInIReg) || (ainfo->storage == ArgInFloatSSEReg) || (ainfo->storage == ArgInDoubleSSEReg) || (ainfo->storage == ArgValuetypeInReg))
1936                                 inreg = FALSE;
1937
1938                         ins->opcode = OP_REGOFFSET;
1939
1940                         switch (ainfo->storage) {
1941                         case ArgInIReg:
1942                         case ArgInFloatSSEReg:
1943                         case ArgInDoubleSSEReg:
1944                                 if (inreg) {
1945                                         ins->opcode = OP_REGVAR;
1946                                         ins->dreg = ainfo->reg;
1947                                 }
1948                                 break;
1949                         case ArgOnStack:
1950                                 g_assert (!cfg->arch.omit_fp);
1951                                 ins->opcode = OP_REGOFFSET;
1952                                 ins->inst_basereg = cfg->frame_reg;
1953                                 ins->inst_offset = ainfo->offset + ARGS_OFFSET;
1954                                 break;
1955                         case ArgValuetypeInReg:
1956                                 break;
1957                         case ArgValuetypeAddrInIReg: {
1958                                 MonoInst *indir;
1959                                 g_assert (!cfg->arch.omit_fp);
1960
1961                                 MONO_INST_NEW (cfg, indir, 0);
1962                                 indir->opcode = OP_REGOFFSET;
1963                                 if (ainfo->pair_storage [0] == ArgInIReg) {
1964                                         indir->inst_basereg = cfg->frame_reg;
1965                                         offset = ALIGN_TO (offset, sizeof (gpointer));
1966                                         offset += (sizeof (gpointer));
1967                                         indir->inst_offset = - offset;
1968                                 }
1969                                 else {
1970                                         indir->inst_basereg = cfg->frame_reg;
1971                                         indir->inst_offset = ainfo->offset + ARGS_OFFSET;
1972                                 }
1973
1974                                 ins->opcode = OP_VTARG_ADDR;
1975                                 ins->inst_left = indir;
1976
1977                                 break;
1978                         }
1979                         default:
1980                                 NOT_IMPLEMENTED;
1981                         }
1982
1983                         if (!inreg && (ainfo->storage != ArgOnStack) && (ainfo->storage != ArgValuetypeAddrInIReg)) {
1984                                 ins->opcode = OP_REGOFFSET;
1985                                 ins->inst_basereg = cfg->frame_reg;
1986                                 /* These arguments are saved to the stack in the prolog */
1987                                 offset = ALIGN_TO (offset, sizeof(mgreg_t));
1988                                 if (cfg->arch.omit_fp) {
1989                                         ins->inst_offset = offset;
1990                                         offset += (ainfo->storage == ArgValuetypeInReg) ? 2 * sizeof(mgreg_t) : sizeof(mgreg_t);
1991                                         // Arguments are yet supported by the stack map creation code
1992                                         //cfg->locals_max_stack_offset = MAX (cfg->locals_max_stack_offset, offset);
1993                                 } else {
1994                                         offset += (ainfo->storage == ArgValuetypeInReg) ? 2 * sizeof(mgreg_t) : sizeof(mgreg_t);
1995                                         ins->inst_offset = - offset;
1996                                         //cfg->locals_min_stack_offset = MIN (cfg->locals_min_stack_offset, offset);
1997                                 }
1998                         }
1999                 }
2000         }
2001
2002         cfg->stack_offset = offset;
2003 }
2004
2005 void
2006 mono_arch_create_vars (MonoCompile *cfg)
2007 {
2008         MonoMethodSignature *sig;
2009         CallInfo *cinfo;
2010
2011         sig = mono_method_signature (cfg->method);
2012
2013         if (!cfg->arch.cinfo)
2014                 cfg->arch.cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig);
2015         cinfo = cfg->arch.cinfo;
2016
2017         if (cinfo->ret.storage == ArgValuetypeInReg)
2018                 cfg->ret_var_is_local = TRUE;
2019
2020         if ((cinfo->ret.storage != ArgValuetypeInReg) && MONO_TYPE_ISSTRUCT (sig->ret)) {
2021                 cfg->vret_addr = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_ARG);
2022                 if (G_UNLIKELY (cfg->verbose_level > 1)) {
2023                         printf ("vret_addr = ");
2024                         mono_print_ins (cfg->vret_addr);
2025                 }
2026         }
2027
2028         if (cfg->gen_seq_points) {
2029                 MonoInst *ins;
2030
2031             ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
2032                 ins->flags |= MONO_INST_VOLATILE;
2033                 cfg->arch.ss_trigger_page_var = ins;
2034         }
2035
2036 #ifdef MONO_AMD64_NO_PUSHES
2037         /*
2038          * When this is set, we pass arguments on the stack by moves, and by allocating
2039          * a bigger stack frame, instead of pushes.
2040          * Pushes complicate exception handling because the arguments on the stack have
2041          * to be popped each time a frame is unwound. They also make fp elimination
2042          * impossible.
2043          * FIXME: This doesn't work inside filter/finally clauses, since those execute
2044          * on a new frame which doesn't include a param area.
2045          */
2046         cfg->arch.no_pushes = TRUE;
2047 #endif
2048 }
2049
2050 static void
2051 add_outarg_reg (MonoCompile *cfg, MonoCallInst *call, ArgStorage storage, int reg, MonoInst *tree)
2052 {
2053         MonoInst *ins;
2054
2055         switch (storage) {
2056         case ArgInIReg:
2057                 MONO_INST_NEW (cfg, ins, OP_MOVE);
2058                 ins->dreg = mono_alloc_ireg (cfg);
2059                 ins->sreg1 = tree->dreg;
2060                 MONO_ADD_INS (cfg->cbb, ins);
2061                 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, reg, FALSE);
2062                 break;
2063         case ArgInFloatSSEReg:
2064                 MONO_INST_NEW (cfg, ins, OP_AMD64_SET_XMMREG_R4);
2065                 ins->dreg = mono_alloc_freg (cfg);
2066                 ins->sreg1 = tree->dreg;
2067                 MONO_ADD_INS (cfg->cbb, ins);
2068
2069                 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, reg, TRUE);
2070                 break;
2071         case ArgInDoubleSSEReg:
2072                 MONO_INST_NEW (cfg, ins, OP_FMOVE);
2073                 ins->dreg = mono_alloc_freg (cfg);
2074                 ins->sreg1 = tree->dreg;
2075                 MONO_ADD_INS (cfg->cbb, ins);
2076
2077                 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, reg, TRUE);
2078
2079                 break;
2080         default:
2081                 g_assert_not_reached ();
2082         }
2083 }
2084
2085 static int
2086 arg_storage_to_load_membase (ArgStorage storage)
2087 {
2088         switch (storage) {
2089         case ArgInIReg:
2090 #if defined(__mono_ilp32__)
2091                 return OP_LOADI8_MEMBASE;
2092 #else
2093                 return OP_LOAD_MEMBASE;
2094 #endif
2095         case ArgInDoubleSSEReg:
2096                 return OP_LOADR8_MEMBASE;
2097         case ArgInFloatSSEReg:
2098                 return OP_LOADR4_MEMBASE;
2099         default:
2100                 g_assert_not_reached ();
2101         }
2102
2103         return -1;
2104 }
2105
2106 static void
2107 emit_sig_cookie (MonoCompile *cfg, MonoCallInst *call, CallInfo *cinfo)
2108 {
2109         MonoInst *arg;
2110         MonoMethodSignature *tmp_sig;
2111         MonoInst *sig_arg;
2112
2113         if (call->tail_call)
2114                 NOT_IMPLEMENTED;
2115
2116         /* FIXME: Add support for signature tokens to AOT */
2117         cfg->disable_aot = TRUE;
2118
2119         g_assert (cinfo->sig_cookie.storage == ArgOnStack);
2120
2121         /*
2122          * mono_ArgIterator_Setup assumes the signature cookie is
2123          * passed first and all the arguments which were before it are
2124          * passed on the stack after the signature. So compensate by
2125          * passing a different signature.
2126          */
2127         tmp_sig = mono_metadata_signature_dup_full (cfg->method->klass->image, call->signature);
2128         tmp_sig->param_count -= call->signature->sentinelpos;
2129         tmp_sig->sentinelpos = 0;
2130         memcpy (tmp_sig->params, call->signature->params + call->signature->sentinelpos, tmp_sig->param_count * sizeof (MonoType*));
2131
2132         MONO_INST_NEW (cfg, sig_arg, OP_ICONST);
2133         sig_arg->dreg = mono_alloc_ireg (cfg);
2134         sig_arg->inst_p0 = tmp_sig;
2135         MONO_ADD_INS (cfg->cbb, sig_arg);
2136
2137         if (cfg->arch.no_pushes) {
2138                 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, cinfo->sig_cookie.offset, sig_arg->dreg);
2139         } else {
2140                 MONO_INST_NEW (cfg, arg, OP_X86_PUSH);
2141                 arg->sreg1 = sig_arg->dreg;
2142                 MONO_ADD_INS (cfg->cbb, arg);
2143         }
2144 }
2145
2146 static inline LLVMArgStorage
2147 arg_storage_to_llvm_arg_storage (MonoCompile *cfg, ArgStorage storage)
2148 {
2149         switch (storage) {
2150         case ArgInIReg:
2151                 return LLVMArgInIReg;
2152         case ArgNone:
2153                 return LLVMArgNone;
2154         default:
2155                 g_assert_not_reached ();
2156                 return LLVMArgNone;
2157         }
2158 }
2159
2160 #ifdef ENABLE_LLVM
2161 LLVMCallInfo*
2162 mono_arch_get_llvm_call_info (MonoCompile *cfg, MonoMethodSignature *sig)
2163 {
2164         int i, n;
2165         CallInfo *cinfo;
2166         ArgInfo *ainfo;
2167         int j;
2168         LLVMCallInfo *linfo;
2169         MonoType *t;
2170
2171         n = sig->param_count + sig->hasthis;
2172
2173         cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig);
2174
2175         linfo = mono_mempool_alloc0 (cfg->mempool, sizeof (LLVMCallInfo) + (sizeof (LLVMArgInfo) * n));
2176
2177         /*
2178          * LLVM always uses the native ABI while we use our own ABI, the
2179          * only difference is the handling of vtypes:
2180          * - we only pass/receive them in registers in some cases, and only
2181          *   in 1 or 2 integer registers.
2182          */
2183         if (cinfo->ret.storage == ArgValuetypeInReg) {
2184                 if (sig->pinvoke) {
2185                         cfg->exception_message = g_strdup ("pinvoke + vtypes");
2186                         cfg->disable_llvm = TRUE;
2187                         return linfo;
2188                 }
2189
2190                 linfo->ret.storage = LLVMArgVtypeInReg;
2191                 for (j = 0; j < 2; ++j)
2192                         linfo->ret.pair_storage [j] = arg_storage_to_llvm_arg_storage (cfg, cinfo->ret.pair_storage [j]);
2193         }
2194
2195         if (MONO_TYPE_ISSTRUCT (sig->ret) && cinfo->ret.storage == ArgInIReg) {
2196                 /* Vtype returned using a hidden argument */
2197                 linfo->ret.storage = LLVMArgVtypeRetAddr;
2198                 linfo->vret_arg_index = cinfo->vret_arg_index;
2199         }
2200
2201         for (i = 0; i < n; ++i) {
2202                 ainfo = cinfo->args + i;
2203
2204                 if (i >= sig->hasthis)
2205                         t = sig->params [i - sig->hasthis];
2206                 else
2207                         t = &mono_defaults.int_class->byval_arg;
2208
2209                 linfo->args [i].storage = LLVMArgNone;
2210
2211                 switch (ainfo->storage) {
2212                 case ArgInIReg:
2213                         linfo->args [i].storage = LLVMArgInIReg;
2214                         break;
2215                 case ArgInDoubleSSEReg:
2216                 case ArgInFloatSSEReg:
2217                         linfo->args [i].storage = LLVMArgInFPReg;
2218                         break;
2219                 case ArgOnStack:
2220                         if (MONO_TYPE_ISSTRUCT (t)) {
2221                                 linfo->args [i].storage = LLVMArgVtypeByVal;
2222                         } else {
2223                                 linfo->args [i].storage = LLVMArgInIReg;
2224                                 if (!t->byref) {
2225                                         if (t->type == MONO_TYPE_R4)
2226                                                 linfo->args [i].storage = LLVMArgInFPReg;
2227                                         else if (t->type == MONO_TYPE_R8)
2228                                                 linfo->args [i].storage = LLVMArgInFPReg;
2229                                 }
2230                         }
2231                         break;
2232                 case ArgValuetypeInReg:
2233                         if (sig->pinvoke) {
2234                                 cfg->exception_message = g_strdup ("pinvoke + vtypes");
2235                                 cfg->disable_llvm = TRUE;
2236                                 return linfo;
2237                         }
2238
2239                         linfo->args [i].storage = LLVMArgVtypeInReg;
2240                         for (j = 0; j < 2; ++j)
2241                                 linfo->args [i].pair_storage [j] = arg_storage_to_llvm_arg_storage (cfg, ainfo->pair_storage [j]);
2242                         break;
2243                 default:
2244                         cfg->exception_message = g_strdup ("ainfo->storage");
2245                         cfg->disable_llvm = TRUE;
2246                         break;
2247                 }
2248         }
2249
2250         return linfo;
2251 }
2252 #endif
2253
2254 void
2255 mono_arch_emit_call (MonoCompile *cfg, MonoCallInst *call)
2256 {
2257         MonoInst *arg, *in;
2258         MonoMethodSignature *sig;
2259         int i, n, stack_size;
2260         CallInfo *cinfo;
2261         ArgInfo *ainfo;
2262
2263         stack_size = 0;
2264
2265         sig = call->signature;
2266         n = sig->param_count + sig->hasthis;
2267
2268         cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig);
2269
2270         if (COMPILE_LLVM (cfg)) {
2271                 /* We shouldn't be called in the llvm case */
2272                 cfg->disable_llvm = TRUE;
2273                 return;
2274         }
2275
2276         if (cinfo->need_stack_align) {
2277                 if (!cfg->arch.no_pushes)
2278                         MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SUB_IMM, X86_ESP, X86_ESP, 8);
2279         }
2280
2281         /*
2282          * Emit all arguments which are passed on the stack to prevent register
2283          * allocation problems.
2284          */
2285         if (cfg->arch.no_pushes) {
2286                 for (i = 0; i < n; ++i) {
2287                         MonoType *t;
2288                         ainfo = cinfo->args + i;
2289
2290                         in = call->args [i];
2291
2292                         if (sig->hasthis && i == 0)
2293                                 t = &mono_defaults.object_class->byval_arg;
2294                         else
2295                                 t = sig->params [i - sig->hasthis];
2296
2297                         if (ainfo->storage == ArgOnStack && !MONO_TYPE_ISSTRUCT (t) && !call->tail_call) {
2298                                 if (!t->byref) {
2299                                         if (t->type == MONO_TYPE_R4)
2300                                                 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER4_MEMBASE_REG, AMD64_RSP, ainfo->offset, in->dreg);
2301                                         else if (t->type == MONO_TYPE_R8)
2302                                                 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER8_MEMBASE_REG, AMD64_RSP, ainfo->offset, in->dreg);
2303                                         else
2304                                                 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, ainfo->offset, in->dreg);
2305                                 } else {
2306                                         MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, ainfo->offset, in->dreg);
2307                                 }
2308                         }
2309                 }
2310         }
2311
2312         /*
2313          * Emit all parameters passed in registers in non-reverse order for better readability
2314          * and to help the optimization in emit_prolog ().
2315          */
2316         for (i = 0; i < n; ++i) {
2317                 ainfo = cinfo->args + i;
2318
2319                 in = call->args [i];
2320
2321                 if (ainfo->storage == ArgInIReg)
2322                         add_outarg_reg (cfg, call, ainfo->storage, ainfo->reg, in);
2323         }
2324
2325         for (i = n - 1; i >= 0; --i) {
2326                 ainfo = cinfo->args + i;
2327
2328                 in = call->args [i];
2329
2330                 switch (ainfo->storage) {
2331                 case ArgInIReg:
2332                         /* Already done */
2333                         break;
2334                 case ArgInFloatSSEReg:
2335                 case ArgInDoubleSSEReg:
2336                         add_outarg_reg (cfg, call, ainfo->storage, ainfo->reg, in);
2337                         break;
2338                 case ArgOnStack:
2339                 case ArgValuetypeInReg:
2340                 case ArgValuetypeAddrInIReg:
2341                         if (ainfo->storage == ArgOnStack && call->tail_call) {
2342                                 MonoInst *call_inst = (MonoInst*)call;
2343                                 cfg->args [i]->flags |= MONO_INST_VOLATILE;
2344                                 EMIT_NEW_ARGSTORE (cfg, call_inst, i, in);
2345                         } else if ((i >= sig->hasthis) && (MONO_TYPE_ISSTRUCT(sig->params [i - sig->hasthis]))) {
2346                                 guint32 align;
2347                                 guint32 size;
2348
2349                                 if (sig->params [i - sig->hasthis]->type == MONO_TYPE_TYPEDBYREF) {
2350                                         size = sizeof (MonoTypedRef);
2351                                         align = sizeof (gpointer);
2352                                 }
2353                                 else {
2354                                         if (sig->pinvoke)
2355                                                 size = mono_type_native_stack_size (&in->klass->byval_arg, &align);
2356                                         else {
2357                                                 /*
2358                                                  * Other backends use mono_type_stack_size (), but that
2359                                                  * aligns the size to 8, which is larger than the size of
2360                                                  * the source, leading to reads of invalid memory if the
2361                                                  * source is at the end of address space.
2362                                                  */
2363                                                 size = mono_class_value_size (in->klass, &align);
2364                                         }
2365                                 }
2366                                 g_assert (in->klass);
2367
2368                                 if (ainfo->storage == ArgOnStack && size >= 10000) {
2369                                         /* Avoid asserts in emit_memcpy () */
2370                                         cfg->exception_type = MONO_EXCEPTION_INVALID_PROGRAM;
2371                                         cfg->exception_message = g_strdup_printf ("Passing an argument of size '%d'.", size);
2372                                         /* Continue normally */
2373                                 }
2374
2375                                 if (size > 0) {
2376                                         MONO_INST_NEW (cfg, arg, OP_OUTARG_VT);
2377                                         arg->sreg1 = in->dreg;
2378                                         arg->klass = in->klass;
2379                                         arg->backend.size = size;
2380                                         arg->inst_p0 = call;
2381                                         arg->inst_p1 = mono_mempool_alloc (cfg->mempool, sizeof (ArgInfo));
2382                                         memcpy (arg->inst_p1, ainfo, sizeof (ArgInfo));
2383
2384                                         MONO_ADD_INS (cfg->cbb, arg);
2385                                 }
2386                         } else {
2387                                 if (cfg->arch.no_pushes) {
2388                                         /* Already done */
2389                                 } else {
2390                                         MONO_INST_NEW (cfg, arg, OP_X86_PUSH);
2391                                         arg->sreg1 = in->dreg;
2392                                         if (!sig->params [i - sig->hasthis]->byref) {
2393                                                 if (sig->params [i - sig->hasthis]->type == MONO_TYPE_R4) {
2394                                                         MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SUB_IMM, X86_ESP, X86_ESP, 8);
2395                                                         arg->opcode = OP_STORER4_MEMBASE_REG;
2396                                                         arg->inst_destbasereg = X86_ESP;
2397                                                         arg->inst_offset = 0;
2398                                                 } else if (sig->params [i - sig->hasthis]->type == MONO_TYPE_R8) {
2399                                                         MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SUB_IMM, X86_ESP, X86_ESP, 8);
2400                                                         arg->opcode = OP_STORER8_MEMBASE_REG;
2401                                                         arg->inst_destbasereg = X86_ESP;
2402                                                         arg->inst_offset = 0;
2403                                                 }
2404                                         }
2405                                         MONO_ADD_INS (cfg->cbb, arg);
2406                                 }
2407                         }
2408                         break;
2409                 default:
2410                         g_assert_not_reached ();
2411                 }
2412
2413                 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos))
2414                         /* Emit the signature cookie just before the implicit arguments */
2415                         emit_sig_cookie (cfg, call, cinfo);
2416         }
2417
2418         /* Handle the case where there are no implicit arguments */
2419         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n == sig->sentinelpos))
2420                 emit_sig_cookie (cfg, call, cinfo);
2421
2422         if (sig->ret && MONO_TYPE_ISSTRUCT (sig->ret)) {
2423                 MonoInst *vtarg;
2424
2425                 if (cinfo->ret.storage == ArgValuetypeInReg) {
2426                         if (cinfo->ret.pair_storage [0] == ArgInIReg && cinfo->ret.pair_storage [1] == ArgNone) {
2427                                 /*
2428                                  * Tell the JIT to use a more efficient calling convention: call using
2429                                  * OP_CALL, compute the result location after the call, and save the
2430                                  * result there.
2431                                  */
2432                                 call->vret_in_reg = TRUE;
2433                                 /*
2434                                  * Nullify the instruction computing the vret addr to enable
2435                                  * future optimizations.
2436                                  */
2437                                 if (call->vret_var)
2438                                         NULLIFY_INS (call->vret_var);
2439                         } else {
2440                                 if (call->tail_call)
2441                                         NOT_IMPLEMENTED;
2442                                 /*
2443                                  * The valuetype is in RAX:RDX after the call, need to be copied to
2444                                  * the stack. Push the address here, so the call instruction can
2445                                  * access it.
2446                                  */
2447                                 if (!cfg->arch.vret_addr_loc) {
2448                                         cfg->arch.vret_addr_loc = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
2449                                         /* Prevent it from being register allocated or optimized away */
2450                                         ((MonoInst*)cfg->arch.vret_addr_loc)->flags |= MONO_INST_VOLATILE;
2451                                 }
2452
2453                                 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, ((MonoInst*)cfg->arch.vret_addr_loc)->dreg, call->vret_var->dreg);
2454                         }
2455                 }
2456                 else {
2457                         MONO_INST_NEW (cfg, vtarg, OP_MOVE);
2458                         vtarg->sreg1 = call->vret_var->dreg;
2459                         vtarg->dreg = mono_alloc_preg (cfg);
2460                         MONO_ADD_INS (cfg->cbb, vtarg);
2461
2462                         mono_call_inst_add_outarg_reg (cfg, call, vtarg->dreg, cinfo->ret.reg, FALSE);
2463                 }
2464         }
2465
2466 #ifdef HOST_WIN32
2467         if (call->inst.opcode != OP_JMP && OP_TAILCALL != call->inst.opcode) {
2468                 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SUB_IMM, X86_ESP, X86_ESP, 0x20);
2469         }
2470 #endif
2471
2472         if (cfg->method->save_lmf) {
2473                 MONO_INST_NEW (cfg, arg, OP_AMD64_SAVE_SP_TO_LMF);
2474                 MONO_ADD_INS (cfg->cbb, arg);
2475         }
2476
2477         call->stack_usage = cinfo->stack_usage;
2478 }
2479
2480 void
2481 mono_arch_emit_outarg_vt (MonoCompile *cfg, MonoInst *ins, MonoInst *src)
2482 {
2483         MonoInst *arg;
2484         MonoCallInst *call = (MonoCallInst*)ins->inst_p0;
2485         ArgInfo *ainfo = (ArgInfo*)ins->inst_p1;
2486         int size = ins->backend.size;
2487
2488         if (ainfo->storage == ArgValuetypeInReg) {
2489                 MonoInst *load;
2490                 int part;
2491
2492                 for (part = 0; part < 2; ++part) {
2493                         if (ainfo->pair_storage [part] == ArgNone)
2494                                 continue;
2495
2496                         MONO_INST_NEW (cfg, load, arg_storage_to_load_membase (ainfo->pair_storage [part]));
2497                         load->inst_basereg = src->dreg;
2498                         load->inst_offset = part * sizeof(mgreg_t);
2499
2500                         switch (ainfo->pair_storage [part]) {
2501                         case ArgInIReg:
2502                                 load->dreg = mono_alloc_ireg (cfg);
2503                                 break;
2504                         case ArgInDoubleSSEReg:
2505                         case ArgInFloatSSEReg:
2506                                 load->dreg = mono_alloc_freg (cfg);
2507                                 break;
2508                         default:
2509                                 g_assert_not_reached ();
2510                         }
2511                         MONO_ADD_INS (cfg->cbb, load);
2512
2513                         add_outarg_reg (cfg, call, ainfo->pair_storage [part], ainfo->pair_regs [part], load);
2514                 }
2515         } else if (ainfo->storage == ArgValuetypeAddrInIReg) {
2516                 MonoInst *vtaddr, *load;
2517                 vtaddr = mono_compile_create_var (cfg, &ins->klass->byval_arg, OP_LOCAL);
2518
2519                 g_assert (!cfg->arch.no_pushes);
2520
2521                 MONO_INST_NEW (cfg, load, OP_LDADDR);
2522                 load->inst_p0 = vtaddr;
2523                 vtaddr->flags |= MONO_INST_INDIRECT;
2524                 load->type = STACK_MP;
2525                 load->klass = vtaddr->klass;
2526                 load->dreg = mono_alloc_ireg (cfg);
2527                 MONO_ADD_INS (cfg->cbb, load);
2528                 mini_emit_memcpy (cfg, load->dreg, 0, src->dreg, 0, size, 4);
2529
2530                 if (ainfo->pair_storage [0] == ArgInIReg) {
2531                         MONO_INST_NEW (cfg, arg, OP_X86_LEA_MEMBASE);
2532                         arg->dreg = mono_alloc_ireg (cfg);
2533                         arg->sreg1 = load->dreg;
2534                         arg->inst_imm = 0;
2535                         MONO_ADD_INS (cfg->cbb, arg);
2536                         mono_call_inst_add_outarg_reg (cfg, call, arg->dreg, ainfo->pair_regs [0], FALSE);
2537                 } else {
2538                         MONO_INST_NEW (cfg, arg, OP_X86_PUSH);
2539                         arg->sreg1 = load->dreg;
2540                         MONO_ADD_INS (cfg->cbb, arg);
2541                 }
2542         } else {
2543                 if (size == 8) {
2544                         if (cfg->arch.no_pushes) {
2545                                 int dreg = mono_alloc_ireg (cfg);
2546
2547                                 MONO_EMIT_NEW_LOAD_MEMBASE (cfg, dreg, src->dreg, 0);
2548                                 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, ainfo->offset, dreg);
2549                         } else {
2550                                 /* Can't use this for < 8 since it does an 8 byte memory load */
2551                                 MONO_INST_NEW (cfg, arg, OP_X86_PUSH_MEMBASE);
2552                                 arg->inst_basereg = src->dreg;
2553                                 arg->inst_offset = 0;
2554                                 MONO_ADD_INS (cfg->cbb, arg);
2555                         }
2556                 } else if (size <= 40) {
2557                         if (cfg->arch.no_pushes) {
2558                                 mini_emit_memcpy (cfg, AMD64_RSP, ainfo->offset, src->dreg, 0, size, 4);
2559                         } else {
2560                                 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SUB_IMM, X86_ESP, X86_ESP, ALIGN_TO (size, 8));
2561                                 mini_emit_memcpy (cfg, X86_ESP, 0, src->dreg, 0, size, 4);
2562                         }
2563                 } else {
2564                         if (cfg->arch.no_pushes) {
2565                                 // FIXME: Code growth
2566                                 mini_emit_memcpy (cfg, AMD64_RSP, ainfo->offset, src->dreg, 0, size, 4);
2567                         } else {
2568                                 MONO_INST_NEW (cfg, arg, OP_X86_PUSH_OBJ);
2569                                 arg->inst_basereg = src->dreg;
2570                                 arg->inst_offset = 0;
2571                                 arg->inst_imm = size;
2572                                 MONO_ADD_INS (cfg->cbb, arg);
2573                         }
2574                 }
2575         }
2576 }
2577
2578 void
2579 mono_arch_emit_setret (MonoCompile *cfg, MonoMethod *method, MonoInst *val)
2580 {
2581         MonoType *ret = mini_type_get_underlying_type (NULL, mono_method_signature (method)->ret);
2582
2583         if (ret->type == MONO_TYPE_R4) {
2584                 if (COMPILE_LLVM (cfg))
2585                         MONO_EMIT_NEW_UNALU (cfg, OP_FMOVE, cfg->ret->dreg, val->dreg);
2586                 else
2587                         MONO_EMIT_NEW_UNALU (cfg, OP_AMD64_SET_XMMREG_R4, cfg->ret->dreg, val->dreg);
2588                 return;
2589         } else if (ret->type == MONO_TYPE_R8) {
2590                 MONO_EMIT_NEW_UNALU (cfg, OP_FMOVE, cfg->ret->dreg, val->dreg);
2591                 return;
2592         }
2593
2594         MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, cfg->ret->dreg, val->dreg);
2595 }
2596
2597 #endif /* DISABLE_JIT */
2598
2599 #define EMIT_COND_BRANCH(ins,cond,sign) \
2600         if (ins->inst_true_bb->native_offset) { \
2601                 x86_branch (code, cond, cfg->native_code + ins->inst_true_bb->native_offset, sign); \
2602         } else { \
2603                 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_true_bb); \
2604                 if ((cfg->opt & MONO_OPT_BRANCH) && \
2605             x86_is_imm8 (ins->inst_true_bb->max_offset - offset)) \
2606                         x86_branch8 (code, cond, 0, sign); \
2607                 else \
2608                         x86_branch32 (code, cond, 0, sign); \
2609 }
2610
2611 typedef struct {
2612         MonoMethodSignature *sig;
2613         CallInfo *cinfo;
2614 } ArchDynCallInfo;
2615
2616 typedef struct {
2617         mgreg_t regs [PARAM_REGS];
2618         mgreg_t res;
2619         guint8 *ret;
2620 } DynCallArgs;
2621
2622 static gboolean
2623 dyn_call_supported (MonoMethodSignature *sig, CallInfo *cinfo)
2624 {
2625         int i;
2626
2627 #ifdef HOST_WIN32
2628         return FALSE;
2629 #endif
2630
2631         switch (cinfo->ret.storage) {
2632         case ArgNone:
2633         case ArgInIReg:
2634                 break;
2635         case ArgValuetypeInReg: {
2636                 ArgInfo *ainfo = &cinfo->ret;
2637
2638                 if (ainfo->pair_storage [0] != ArgNone && ainfo->pair_storage [0] != ArgInIReg)
2639                         return FALSE;
2640                 if (ainfo->pair_storage [1] != ArgNone && ainfo->pair_storage [1] != ArgInIReg)
2641                         return FALSE;
2642                 break;
2643         }
2644         default:
2645                 return FALSE;
2646         }
2647
2648         for (i = 0; i < cinfo->nargs; ++i) {
2649                 ArgInfo *ainfo = &cinfo->args [i];
2650                 switch (ainfo->storage) {
2651                 case ArgInIReg:
2652                         break;
2653                 case ArgValuetypeInReg:
2654                         if (ainfo->pair_storage [0] != ArgNone && ainfo->pair_storage [0] != ArgInIReg)
2655                                 return FALSE;
2656                         if (ainfo->pair_storage [1] != ArgNone && ainfo->pair_storage [1] != ArgInIReg)
2657                                 return FALSE;
2658                         break;
2659                 default:
2660                         return FALSE;
2661                 }
2662         }
2663
2664         return TRUE;
2665 }
2666
2667 /*
2668  * mono_arch_dyn_call_prepare:
2669  *
2670  *   Return a pointer to an arch-specific structure which contains information
2671  * needed by mono_arch_get_dyn_call_args (). Return NULL if OP_DYN_CALL is not
2672  * supported for SIG.
2673  * This function is equivalent to ffi_prep_cif in libffi.
2674  */
2675 MonoDynCallInfo*
2676 mono_arch_dyn_call_prepare (MonoMethodSignature *sig)
2677 {
2678         ArchDynCallInfo *info;
2679         CallInfo *cinfo;
2680
2681         cinfo = get_call_info (NULL, NULL, sig);
2682
2683         if (!dyn_call_supported (sig, cinfo)) {
2684                 g_free (cinfo);
2685                 return NULL;
2686         }
2687
2688         info = g_new0 (ArchDynCallInfo, 1);
2689         // FIXME: Preprocess the info to speed up get_dyn_call_args ().
2690         info->sig = sig;
2691         info->cinfo = cinfo;
2692
2693         return (MonoDynCallInfo*)info;
2694 }
2695
2696 /*
2697  * mono_arch_dyn_call_free:
2698  *
2699  *   Free a MonoDynCallInfo structure.
2700  */
2701 void
2702 mono_arch_dyn_call_free (MonoDynCallInfo *info)
2703 {
2704         ArchDynCallInfo *ainfo = (ArchDynCallInfo*)info;
2705
2706         g_free (ainfo->cinfo);
2707         g_free (ainfo);
2708 }
2709
2710 #if !defined(__native_client__)
2711 #define PTR_TO_GREG(ptr) (mgreg_t)(ptr)
2712 #define GREG_TO_PTR(greg) (gpointer)(greg)
2713 #else
2714 /* Correctly handle casts to/from 32-bit pointers without compiler warnings */
2715 #define PTR_TO_GREG(ptr) (mgreg_t)(uintptr_t)(ptr)
2716 #define GREG_TO_PTR(greg) (gpointer)(guint32)(greg)
2717 #endif
2718
2719 /*
2720  * mono_arch_get_start_dyn_call:
2721  *
2722  *   Convert the arguments ARGS to a format which can be passed to OP_DYN_CALL, and
2723  * store the result into BUF.
2724  * ARGS should be an array of pointers pointing to the arguments.
2725  * RET should point to a memory buffer large enought to hold the result of the
2726  * call.
2727  * This function should be as fast as possible, any work which does not depend
2728  * on the actual values of the arguments should be done in
2729  * mono_arch_dyn_call_prepare ().
2730  * start_dyn_call + OP_DYN_CALL + finish_dyn_call is equivalent to ffi_call in
2731  * libffi.
2732  */
2733 void
2734 mono_arch_start_dyn_call (MonoDynCallInfo *info, gpointer **args, guint8 *ret, guint8 *buf, int buf_len)
2735 {
2736         ArchDynCallInfo *dinfo = (ArchDynCallInfo*)info;
2737         DynCallArgs *p = (DynCallArgs*)buf;
2738         int arg_index, greg, i, pindex;
2739         MonoMethodSignature *sig = dinfo->sig;
2740
2741         g_assert (buf_len >= sizeof (DynCallArgs));
2742
2743         p->res = 0;
2744         p->ret = ret;
2745
2746         arg_index = 0;
2747         greg = 0;
2748         pindex = 0;
2749
2750         if (sig->hasthis || dinfo->cinfo->vret_arg_index == 1) {
2751                 p->regs [greg ++] = PTR_TO_GREG(*(args [arg_index ++]));
2752                 if (!sig->hasthis)
2753                         pindex = 1;
2754         }
2755
2756         if (dinfo->cinfo->vtype_retaddr)
2757                 p->regs [greg ++] = PTR_TO_GREG(ret);
2758
2759         for (i = pindex; i < sig->param_count; i++) {
2760                 MonoType *t = mono_type_get_underlying_type (sig->params [i]);
2761                 gpointer *arg = args [arg_index ++];
2762
2763                 if (t->byref) {
2764                         p->regs [greg ++] = PTR_TO_GREG(*(arg));
2765                         continue;
2766                 }
2767
2768                 switch (t->type) {
2769                 case MONO_TYPE_STRING:
2770                 case MONO_TYPE_CLASS:
2771                 case MONO_TYPE_ARRAY:
2772                 case MONO_TYPE_SZARRAY:
2773                 case MONO_TYPE_OBJECT:
2774                 case MONO_TYPE_PTR:
2775                 case MONO_TYPE_I:
2776                 case MONO_TYPE_U:
2777 #if !defined(__mono_ilp32__)
2778                 case MONO_TYPE_I8:
2779                 case MONO_TYPE_U8:
2780 #endif
2781                         g_assert (dinfo->cinfo->args [i + sig->hasthis].reg == param_regs [greg]);
2782                         p->regs [greg ++] = PTR_TO_GREG(*(arg));
2783                         break;
2784 #if defined(__mono_ilp32__)
2785                 case MONO_TYPE_I8:
2786                 case MONO_TYPE_U8:
2787                         g_assert (dinfo->cinfo->args [i + sig->hasthis].reg == param_regs [greg]);
2788                         p->regs [greg ++] = *(guint64*)(arg);
2789                         break;
2790 #endif
2791                 case MONO_TYPE_BOOLEAN:
2792                 case MONO_TYPE_U1:
2793                         p->regs [greg ++] = *(guint8*)(arg);
2794                         break;
2795                 case MONO_TYPE_I1:
2796                         p->regs [greg ++] = *(gint8*)(arg);
2797                         break;
2798                 case MONO_TYPE_I2:
2799                         p->regs [greg ++] = *(gint16*)(arg);
2800                         break;
2801                 case MONO_TYPE_U2:
2802                 case MONO_TYPE_CHAR:
2803                         p->regs [greg ++] = *(guint16*)(arg);
2804                         break;
2805                 case MONO_TYPE_I4:
2806                         p->regs [greg ++] = *(gint32*)(arg);
2807                         break;
2808                 case MONO_TYPE_U4:
2809                         p->regs [greg ++] = *(guint32*)(arg);
2810                         break;
2811                 case MONO_TYPE_GENERICINST:
2812                     if (MONO_TYPE_IS_REFERENCE (t)) {
2813                                 p->regs [greg ++] = PTR_TO_GREG(*(arg));
2814                                 break;
2815                         } else {
2816                                 /* Fall through */
2817                         }
2818                 case MONO_TYPE_VALUETYPE: {
2819                         ArgInfo *ainfo = &dinfo->cinfo->args [i + sig->hasthis];
2820
2821                         g_assert (ainfo->storage == ArgValuetypeInReg);
2822                         if (ainfo->pair_storage [0] != ArgNone) {
2823                                 g_assert (ainfo->pair_storage [0] == ArgInIReg);
2824                                 p->regs [greg ++] = ((mgreg_t*)(arg))[0];
2825                         }
2826                         if (ainfo->pair_storage [1] != ArgNone) {
2827                                 g_assert (ainfo->pair_storage [1] == ArgInIReg);
2828                                 p->regs [greg ++] = ((mgreg_t*)(arg))[1];
2829                         }
2830                         break;
2831                 }
2832                 default:
2833                         g_assert_not_reached ();
2834                 }
2835         }
2836
2837         g_assert (greg <= PARAM_REGS);
2838 }
2839
2840 /*
2841  * mono_arch_finish_dyn_call:
2842  *
2843  *   Store the result of a dyn call into the return value buffer passed to
2844  * start_dyn_call ().
2845  * This function should be as fast as possible, any work which does not depend
2846  * on the actual values of the arguments should be done in
2847  * mono_arch_dyn_call_prepare ().
2848  */
2849 void
2850 mono_arch_finish_dyn_call (MonoDynCallInfo *info, guint8 *buf)
2851 {
2852         ArchDynCallInfo *dinfo = (ArchDynCallInfo*)info;
2853         MonoMethodSignature *sig = dinfo->sig;
2854         guint8 *ret = ((DynCallArgs*)buf)->ret;
2855         mgreg_t res = ((DynCallArgs*)buf)->res;
2856
2857         switch (mono_type_get_underlying_type (sig->ret)->type) {
2858         case MONO_TYPE_VOID:
2859                 *(gpointer*)ret = NULL;
2860                 break;
2861         case MONO_TYPE_STRING:
2862         case MONO_TYPE_CLASS:
2863         case MONO_TYPE_ARRAY:
2864         case MONO_TYPE_SZARRAY:
2865         case MONO_TYPE_OBJECT:
2866         case MONO_TYPE_I:
2867         case MONO_TYPE_U:
2868         case MONO_TYPE_PTR:
2869                 *(gpointer*)ret = GREG_TO_PTR(res);
2870                 break;
2871         case MONO_TYPE_I1:
2872                 *(gint8*)ret = res;
2873                 break;
2874         case MONO_TYPE_U1:
2875         case MONO_TYPE_BOOLEAN:
2876                 *(guint8*)ret = res;
2877                 break;
2878         case MONO_TYPE_I2:
2879                 *(gint16*)ret = res;
2880                 break;
2881         case MONO_TYPE_U2:
2882         case MONO_TYPE_CHAR:
2883                 *(guint16*)ret = res;
2884                 break;
2885         case MONO_TYPE_I4:
2886                 *(gint32*)ret = res;
2887                 break;
2888         case MONO_TYPE_U4:
2889                 *(guint32*)ret = res;
2890                 break;
2891         case MONO_TYPE_I8:
2892                 *(gint64*)ret = res;
2893                 break;
2894         case MONO_TYPE_U8:
2895                 *(guint64*)ret = res;
2896                 break;
2897         case MONO_TYPE_GENERICINST:
2898                 if (MONO_TYPE_IS_REFERENCE (sig->ret)) {
2899                         *(gpointer*)ret = GREG_TO_PTR(res);
2900                         break;
2901                 } else {
2902                         /* Fall through */
2903                 }
2904         case MONO_TYPE_VALUETYPE:
2905                 if (dinfo->cinfo->vtype_retaddr) {
2906                         /* Nothing to do */
2907                 } else {
2908                         ArgInfo *ainfo = &dinfo->cinfo->ret;
2909
2910                         g_assert (ainfo->storage == ArgValuetypeInReg);
2911
2912                         if (ainfo->pair_storage [0] != ArgNone) {
2913                                 g_assert (ainfo->pair_storage [0] == ArgInIReg);
2914                                 ((mgreg_t*)ret)[0] = res;
2915                         }
2916
2917                         g_assert (ainfo->pair_storage [1] == ArgNone);
2918                 }
2919                 break;
2920         default:
2921                 g_assert_not_reached ();
2922         }
2923 }
2924
2925 /* emit an exception if condition is fail */
2926 #define EMIT_COND_SYSTEM_EXCEPTION(cond,signed,exc_name)            \
2927         do {                                                        \
2928                 MonoInst *tins = mono_branch_optimize_exception_target (cfg, bb, exc_name); \
2929                 if (tins == NULL) {                                                                             \
2930                         mono_add_patch_info (cfg, code - cfg->native_code,   \
2931                                         MONO_PATCH_INFO_EXC, exc_name);  \
2932                         x86_branch32 (code, cond, 0, signed);               \
2933                 } else {        \
2934                         EMIT_COND_BRANCH (tins, cond, signed);  \
2935                 }                       \
2936         } while (0);
2937
2938 #define EMIT_FPCOMPARE(code) do { \
2939         amd64_fcompp (code); \
2940         amd64_fnstsw (code); \
2941 } while (0);
2942
2943 #define EMIT_SSE2_FPFUNC(code, op, dreg, sreg1) do { \
2944     amd64_movsd_membase_reg (code, AMD64_RSP, -8, (sreg1)); \
2945         amd64_fld_membase (code, AMD64_RSP, -8, TRUE); \
2946         amd64_ ##op (code); \
2947         amd64_fst_membase (code, AMD64_RSP, -8, TRUE, TRUE); \
2948         amd64_movsd_reg_membase (code, (dreg), AMD64_RSP, -8); \
2949 } while (0);
2950
2951 static guint8*
2952 emit_call_body (MonoCompile *cfg, guint8 *code, guint32 patch_type, gconstpointer data)
2953 {
2954         gboolean no_patch = FALSE;
2955
2956         /*
2957          * FIXME: Add support for thunks
2958          */
2959         {
2960                 gboolean near_call = FALSE;
2961
2962                 /*
2963                  * Indirect calls are expensive so try to make a near call if possible.
2964                  * The caller memory is allocated by the code manager so it is
2965                  * guaranteed to be at a 32 bit offset.
2966                  */
2967
2968                 if (patch_type != MONO_PATCH_INFO_ABS) {
2969                         /* The target is in memory allocated using the code manager */
2970                         near_call = TRUE;
2971
2972                         if ((patch_type == MONO_PATCH_INFO_METHOD) || (patch_type == MONO_PATCH_INFO_METHOD_JUMP)) {
2973                                 if (((MonoMethod*)data)->klass->image->aot_module)
2974                                         /* The callee might be an AOT method */
2975                                         near_call = FALSE;
2976                                 if (((MonoMethod*)data)->dynamic)
2977                                         /* The target is in malloc-ed memory */
2978                                         near_call = FALSE;
2979                         }
2980
2981                         if (patch_type == MONO_PATCH_INFO_INTERNAL_METHOD) {
2982                                 /*
2983                                  * The call might go directly to a native function without
2984                                  * the wrapper.
2985                                  */
2986                                 MonoJitICallInfo *mi = mono_find_jit_icall_by_name (data);
2987                                 if (mi) {
2988                                         gconstpointer target = mono_icall_get_wrapper (mi);
2989                                         if ((((guint64)target) >> 32) != 0)
2990                                                 near_call = FALSE;
2991                                 }
2992                         }
2993                 }
2994                 else {
2995                         if (cfg->abs_patches && g_hash_table_lookup (cfg->abs_patches, data)) {
2996                                 /*
2997                                  * This is not really an optimization, but required because the
2998                                  * generic class init trampolines use R11 to pass the vtable.
2999                                  */
3000                                 near_call = TRUE;
3001                         } else {
3002                                 MonoJitICallInfo *info = mono_find_jit_icall_by_addr (data);
3003                                 if (info) {
3004                                         if ((cfg->method->wrapper_type == MONO_WRAPPER_MANAGED_TO_NATIVE) &&
3005                                                 strstr (cfg->method->name, info->name)) {
3006                                                 /* A call to the wrapped function */
3007                                                 if ((((guint64)data) >> 32) == 0)
3008                                                         near_call = TRUE;
3009                                                 no_patch = TRUE;
3010                                         }
3011                                         else if (info->func == info->wrapper) {
3012                                                 /* No wrapper */
3013                                                 if ((((guint64)info->func) >> 32) == 0)
3014                                                         near_call = TRUE;
3015                                         }
3016                                         else {
3017                                                 /* See the comment in mono_codegen () */
3018                                                 if ((info->name [0] != 'v') || (strstr (info->name, "ves_array_new_va_") == NULL && strstr (info->name, "ves_array_element_address_") == NULL))
3019                                                         near_call = TRUE;
3020                                         }
3021                                 }
3022                                 else if ((((guint64)data) >> 32) == 0) {
3023                                         near_call = TRUE;
3024                                         no_patch = TRUE;
3025                                 }
3026                         }
3027                 }
3028
3029                 if (cfg->method->dynamic)
3030                         /* These methods are allocated using malloc */
3031                         near_call = FALSE;
3032
3033 #ifdef MONO_ARCH_NOMAP32BIT
3034                 near_call = FALSE;
3035 #endif
3036
3037                 /* The 64bit XEN kernel does not honour the MAP_32BIT flag. (#522894) */
3038                 if (optimize_for_xen)
3039                         near_call = FALSE;
3040
3041                 if (cfg->compile_aot) {
3042                         near_call = TRUE;
3043                         no_patch = TRUE;
3044                 }
3045
3046                 if (near_call) {
3047                         /*
3048                          * Align the call displacement to an address divisible by 4 so it does
3049                          * not span cache lines. This is required for code patching to work on SMP
3050                          * systems.
3051                          */
3052                         if (!no_patch && ((guint32)(code + 1 - cfg->native_code) % 4) != 0) {
3053                                 guint32 pad_size = 4 - ((guint32)(code + 1 - cfg->native_code) % 4);
3054                                 amd64_padding (code, pad_size);
3055                         }
3056                         mono_add_patch_info (cfg, code - cfg->native_code, patch_type, data);
3057                         amd64_call_code (code, 0);
3058                 }
3059                 else {
3060                         mono_add_patch_info (cfg, code - cfg->native_code, patch_type, data);
3061                         amd64_set_reg_template (code, GP_SCRATCH_REG);
3062                         amd64_call_reg (code, GP_SCRATCH_REG);
3063                 }
3064         }
3065
3066         return code;
3067 }
3068
3069 static inline guint8*
3070 emit_call (MonoCompile *cfg, guint8 *code, guint32 patch_type, gconstpointer data, gboolean win64_adjust_stack)
3071 {
3072 #ifdef HOST_WIN32
3073         if (win64_adjust_stack)
3074                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 32);
3075 #endif
3076         code = emit_call_body (cfg, code, patch_type, data);
3077 #ifdef HOST_WIN32
3078         if (win64_adjust_stack)
3079                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 32);
3080 #endif
3081
3082         return code;
3083 }
3084
3085 static inline int
3086 store_membase_imm_to_store_membase_reg (int opcode)
3087 {
3088         switch (opcode) {
3089         case OP_STORE_MEMBASE_IMM:
3090                 return OP_STORE_MEMBASE_REG;
3091         case OP_STOREI4_MEMBASE_IMM:
3092                 return OP_STOREI4_MEMBASE_REG;
3093         case OP_STOREI8_MEMBASE_IMM:
3094                 return OP_STOREI8_MEMBASE_REG;
3095         }
3096
3097         return -1;
3098 }
3099
3100 #ifndef DISABLE_JIT
3101
3102 #define INST_IGNORES_CFLAGS(opcode) (!(((opcode) == OP_ADC) || ((opcode) == OP_ADC_IMM) || ((opcode) == OP_IADC) || ((opcode) == OP_IADC_IMM) || ((opcode) == OP_SBB) || ((opcode) == OP_SBB_IMM) || ((opcode) == OP_ISBB) || ((opcode) == OP_ISBB_IMM)))
3103
3104 /*
3105  * mono_arch_peephole_pass_1:
3106  *
3107  *   Perform peephole opts which should/can be performed before local regalloc
3108  */
3109 void
3110 mono_arch_peephole_pass_1 (MonoCompile *cfg, MonoBasicBlock *bb)
3111 {
3112         MonoInst *ins, *n;
3113
3114         MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
3115                 MonoInst *last_ins = ins->prev;
3116
3117                 switch (ins->opcode) {
3118                 case OP_ADD_IMM:
3119                 case OP_IADD_IMM:
3120                 case OP_LADD_IMM:
3121                         if ((ins->sreg1 < MONO_MAX_IREGS) && (ins->dreg >= MONO_MAX_IREGS) && (ins->inst_imm > 0)) {
3122                                 /*
3123                                  * X86_LEA is like ADD, but doesn't have the
3124                                  * sreg1==dreg restriction. inst_imm > 0 is needed since LEA sign-extends
3125                                  * its operand to 64 bit.
3126                                  */
3127                                 ins->opcode = OP_X86_LEA_MEMBASE;
3128                                 ins->inst_basereg = ins->sreg1;
3129                         }
3130                         break;
3131                 case OP_LXOR:
3132                 case OP_IXOR:
3133                         if ((ins->sreg1 == ins->sreg2) && (ins->sreg1 == ins->dreg)) {
3134                                 MonoInst *ins2;
3135
3136                                 /*
3137                                  * Replace STORE_MEMBASE_IMM 0 with STORE_MEMBASE_REG since
3138                                  * the latter has length 2-3 instead of 6 (reverse constant
3139                                  * propagation). These instruction sequences are very common
3140                                  * in the initlocals bblock.
3141                                  */
3142                                 for (ins2 = ins->next; ins2; ins2 = ins2->next) {
3143                                         if (((ins2->opcode == OP_STORE_MEMBASE_IMM) || (ins2->opcode == OP_STOREI4_MEMBASE_IMM) || (ins2->opcode == OP_STOREI8_MEMBASE_IMM) || (ins2->opcode == OP_STORE_MEMBASE_IMM)) && (ins2->inst_imm == 0)) {
3144                                                 ins2->opcode = store_membase_imm_to_store_membase_reg (ins2->opcode);
3145                                                 ins2->sreg1 = ins->dreg;
3146                                         } else if ((ins2->opcode == OP_STOREI1_MEMBASE_IMM) || (ins2->opcode == OP_STOREI2_MEMBASE_IMM) || (ins2->opcode == OP_STOREI8_MEMBASE_REG) || (ins2->opcode == OP_STORE_MEMBASE_REG)) {
3147                                                 /* Continue */
3148                                         } else if (((ins2->opcode == OP_ICONST) || (ins2->opcode == OP_I8CONST)) && (ins2->dreg == ins->dreg) && (ins2->inst_c0 == 0)) {
3149                                                 NULLIFY_INS (ins2);
3150                                                 /* Continue */
3151                                         } else {
3152                                                 break;
3153                                         }
3154                                 }
3155                         }
3156                         break;
3157                 case OP_COMPARE_IMM:
3158                 case OP_LCOMPARE_IMM:
3159                         /* OP_COMPARE_IMM (reg, 0)
3160                          * -->
3161                          * OP_AMD64_TEST_NULL (reg)
3162                          */
3163                         if (!ins->inst_imm)
3164                                 ins->opcode = OP_AMD64_TEST_NULL;
3165                         break;
3166                 case OP_ICOMPARE_IMM:
3167                         if (!ins->inst_imm)
3168                                 ins->opcode = OP_X86_TEST_NULL;
3169                         break;
3170                 case OP_AMD64_ICOMPARE_MEMBASE_IMM:
3171                         /*
3172                          * OP_STORE_MEMBASE_REG reg, offset(basereg)
3173                          * OP_X86_COMPARE_MEMBASE_IMM offset(basereg), imm
3174                          * -->
3175                          * OP_STORE_MEMBASE_REG reg, offset(basereg)
3176                          * OP_COMPARE_IMM reg, imm
3177                          *
3178                          * Note: if imm = 0 then OP_COMPARE_IMM replaced with OP_X86_TEST_NULL
3179                          */
3180                         if (last_ins && (last_ins->opcode == OP_STOREI4_MEMBASE_REG) &&
3181                             ins->inst_basereg == last_ins->inst_destbasereg &&
3182                             ins->inst_offset == last_ins->inst_offset) {
3183                                         ins->opcode = OP_ICOMPARE_IMM;
3184                                         ins->sreg1 = last_ins->sreg1;
3185
3186                                         /* check if we can remove cmp reg,0 with test null */
3187                                         if (!ins->inst_imm)
3188                                                 ins->opcode = OP_X86_TEST_NULL;
3189                                 }
3190
3191                         break;
3192                 }
3193
3194                 mono_peephole_ins (bb, ins);
3195         }
3196 }
3197
3198 void
3199 mono_arch_peephole_pass_2 (MonoCompile *cfg, MonoBasicBlock *bb)
3200 {
3201         MonoInst *ins, *n;
3202
3203         MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
3204                 switch (ins->opcode) {
3205                 case OP_ICONST:
3206                 case OP_I8CONST: {
3207                         /* reg = 0 -> XOR (reg, reg) */
3208                         /* XOR sets cflags on x86, so we cant do it always */
3209                         if (ins->inst_c0 == 0 && (!ins->next || (ins->next && INST_IGNORES_CFLAGS (ins->next->opcode)))) {
3210                                 ins->opcode = OP_LXOR;
3211                                 ins->sreg1 = ins->dreg;
3212                                 ins->sreg2 = ins->dreg;
3213                                 /* Fall through */
3214                         } else {
3215                                 break;
3216                         }
3217                 }
3218                 case OP_LXOR:
3219                         /*
3220                          * Use IXOR to avoid a rex prefix if possible. The cpu will sign extend the
3221                          * 0 result into 64 bits.
3222                          */
3223                         if ((ins->sreg1 == ins->sreg2) && (ins->sreg1 == ins->dreg)) {
3224                                 ins->opcode = OP_IXOR;
3225                         }
3226                         /* Fall through */
3227                 case OP_IXOR:
3228                         if ((ins->sreg1 == ins->sreg2) && (ins->sreg1 == ins->dreg)) {
3229                                 MonoInst *ins2;
3230
3231                                 /*
3232                                  * Replace STORE_MEMBASE_IMM 0 with STORE_MEMBASE_REG since
3233                                  * the latter has length 2-3 instead of 6 (reverse constant
3234                                  * propagation). These instruction sequences are very common
3235                                  * in the initlocals bblock.
3236                                  */
3237                                 for (ins2 = ins->next; ins2; ins2 = ins2->next) {
3238                                         if (((ins2->opcode == OP_STORE_MEMBASE_IMM) || (ins2->opcode == OP_STOREI4_MEMBASE_IMM) || (ins2->opcode == OP_STOREI8_MEMBASE_IMM) || (ins2->opcode == OP_STORE_MEMBASE_IMM)) && (ins2->inst_imm == 0)) {
3239                                                 ins2->opcode = store_membase_imm_to_store_membase_reg (ins2->opcode);
3240                                                 ins2->sreg1 = ins->dreg;
3241                                         } else if ((ins2->opcode == OP_STOREI1_MEMBASE_IMM) || (ins2->opcode == OP_STOREI2_MEMBASE_IMM) || (ins2->opcode == OP_STOREI4_MEMBASE_REG) || (ins2->opcode == OP_STOREI8_MEMBASE_REG) || (ins2->opcode == OP_STORE_MEMBASE_REG) || (ins2->opcode == OP_LIVERANGE_START)) {
3242                                                 /* Continue */
3243                                         } else if (((ins2->opcode == OP_ICONST) || (ins2->opcode == OP_I8CONST)) && (ins2->dreg == ins->dreg) && (ins2->inst_c0 == 0)) {
3244                                                 NULLIFY_INS (ins2);
3245                                                 /* Continue */
3246                                         } else {
3247                                                 break;
3248                                         }
3249                                 }
3250                         }
3251                         break;
3252                 case OP_IADD_IMM:
3253                         if ((ins->inst_imm == 1) && (ins->dreg == ins->sreg1))
3254                                 ins->opcode = OP_X86_INC_REG;
3255                         break;
3256                 case OP_ISUB_IMM:
3257                         if ((ins->inst_imm == 1) && (ins->dreg == ins->sreg1))
3258                                 ins->opcode = OP_X86_DEC_REG;
3259                         break;
3260                 }
3261
3262                 mono_peephole_ins (bb, ins);
3263         }
3264 }
3265
3266 #define NEW_INS(cfg,ins,dest,op) do {   \
3267                 MONO_INST_NEW ((cfg), (dest), (op)); \
3268         (dest)->cil_code = (ins)->cil_code; \
3269         mono_bblock_insert_before_ins (bb, ins, (dest)); \
3270         } while (0)
3271
3272 /*
3273  * mono_arch_lowering_pass:
3274  *
3275  *  Converts complex opcodes into simpler ones so that each IR instruction
3276  * corresponds to one machine instruction.
3277  */
3278 void
3279 mono_arch_lowering_pass (MonoCompile *cfg, MonoBasicBlock *bb)
3280 {
3281         MonoInst *ins, *n, *temp;
3282
3283         /*
3284          * FIXME: Need to add more instructions, but the current machine
3285          * description can't model some parts of the composite instructions like
3286          * cdq.
3287          */
3288         MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
3289                 switch (ins->opcode) {
3290                 case OP_DIV_IMM:
3291                 case OP_REM_IMM:
3292                 case OP_IDIV_IMM:
3293                 case OP_IDIV_UN_IMM:
3294                 case OP_IREM_UN_IMM:
3295                         mono_decompose_op_imm (cfg, bb, ins);
3296                         break;
3297                 case OP_IREM_IMM:
3298                         /* Keep the opcode if we can implement it efficiently */
3299                         if (!((ins->inst_imm > 0) && (mono_is_power_of_two (ins->inst_imm) != -1)))
3300                                 mono_decompose_op_imm (cfg, bb, ins);
3301                         break;
3302                 case OP_COMPARE_IMM:
3303                 case OP_LCOMPARE_IMM:
3304                         if (!amd64_is_imm32 (ins->inst_imm)) {
3305                                 NEW_INS (cfg, ins, temp, OP_I8CONST);
3306                                 temp->inst_c0 = ins->inst_imm;
3307                                 temp->dreg = mono_alloc_ireg (cfg);
3308                                 ins->opcode = OP_COMPARE;
3309                                 ins->sreg2 = temp->dreg;
3310                         }
3311                         break;
3312 #ifndef __mono_ilp32__
3313                 case OP_LOAD_MEMBASE:
3314 #endif
3315                 case OP_LOADI8_MEMBASE:
3316 #ifndef __native_client_codegen__
3317                 /*  Don't generate memindex opcodes (to simplify */
3318                 /*  read sandboxing) */
3319                         if (!amd64_is_imm32 (ins->inst_offset)) {
3320                                 NEW_INS (cfg, ins, temp, OP_I8CONST);
3321                                 temp->inst_c0 = ins->inst_offset;
3322                                 temp->dreg = mono_alloc_ireg (cfg);
3323                                 ins->opcode = OP_AMD64_LOADI8_MEMINDEX;
3324                                 ins->inst_indexreg = temp->dreg;
3325                         }
3326 #endif
3327                         break;
3328 #ifndef __mono_ilp32__
3329                 case OP_STORE_MEMBASE_IMM:
3330 #endif
3331                 case OP_STOREI8_MEMBASE_IMM:
3332                         if (!amd64_is_imm32 (ins->inst_imm)) {
3333                                 NEW_INS (cfg, ins, temp, OP_I8CONST);
3334                                 temp->inst_c0 = ins->inst_imm;
3335                                 temp->dreg = mono_alloc_ireg (cfg);
3336                                 ins->opcode = OP_STOREI8_MEMBASE_REG;
3337                                 ins->sreg1 = temp->dreg;
3338                         }
3339                         break;
3340 #ifdef MONO_ARCH_SIMD_INTRINSICS
3341                 case OP_EXPAND_I1: {
3342                                 int temp_reg1 = mono_alloc_ireg (cfg);
3343                                 int temp_reg2 = mono_alloc_ireg (cfg);
3344                                 int original_reg = ins->sreg1;
3345
3346                                 NEW_INS (cfg, ins, temp, OP_ICONV_TO_U1);
3347                                 temp->sreg1 = original_reg;
3348                                 temp->dreg = temp_reg1;
3349
3350                                 NEW_INS (cfg, ins, temp, OP_SHL_IMM);
3351                                 temp->sreg1 = temp_reg1;
3352                                 temp->dreg = temp_reg2;
3353                                 temp->inst_imm = 8;
3354
3355                                 NEW_INS (cfg, ins, temp, OP_LOR);
3356                                 temp->sreg1 = temp->dreg = temp_reg2;
3357                                 temp->sreg2 = temp_reg1;
3358
3359                                 ins->opcode = OP_EXPAND_I2;
3360                                 ins->sreg1 = temp_reg2;
3361                         }
3362                         break;
3363 #endif
3364                 default:
3365                         break;
3366                 }
3367         }
3368
3369         bb->max_vreg = cfg->next_vreg;
3370 }
3371
3372 static const int
3373 branch_cc_table [] = {
3374         X86_CC_EQ, X86_CC_GE, X86_CC_GT, X86_CC_LE, X86_CC_LT,
3375         X86_CC_NE, X86_CC_GE, X86_CC_GT, X86_CC_LE, X86_CC_LT,
3376         X86_CC_O, X86_CC_NO, X86_CC_C, X86_CC_NC
3377 };
3378
3379 /* Maps CMP_... constants to X86_CC_... constants */
3380 static const int
3381 cc_table [] = {
3382         X86_CC_EQ, X86_CC_NE, X86_CC_LE, X86_CC_GE, X86_CC_LT, X86_CC_GT,
3383         X86_CC_LE, X86_CC_GE, X86_CC_LT, X86_CC_GT
3384 };
3385
3386 static const int
3387 cc_signed_table [] = {
3388         TRUE, TRUE, TRUE, TRUE, TRUE, TRUE,
3389         FALSE, FALSE, FALSE, FALSE
3390 };
3391
3392 /*#include "cprop.c"*/
3393
3394 static unsigned char*
3395 emit_float_to_int (MonoCompile *cfg, guchar *code, int dreg, int sreg, int size, gboolean is_signed)
3396 {
3397         amd64_sse_cvttsd2si_reg_reg (code, dreg, sreg);
3398
3399         if (size == 1)
3400                 amd64_widen_reg (code, dreg, dreg, is_signed, FALSE);
3401         else if (size == 2)
3402                 amd64_widen_reg (code, dreg, dreg, is_signed, TRUE);
3403         return code;
3404 }
3405
3406 static unsigned char*
3407 mono_emit_stack_alloc (MonoCompile *cfg, guchar *code, MonoInst* tree)
3408 {
3409         int sreg = tree->sreg1;
3410         int need_touch = FALSE;
3411
3412 #if defined(HOST_WIN32) || defined(MONO_ARCH_SIGSEGV_ON_ALTSTACK)
3413         if (!tree->flags & MONO_INST_INIT)
3414                 need_touch = TRUE;
3415 #endif
3416
3417         if (need_touch) {
3418                 guint8* br[5];
3419
3420                 /*
3421                  * Under Windows:
3422                  * If requested stack size is larger than one page,
3423                  * perform stack-touch operation
3424                  */
3425                 /*
3426                  * Generate stack probe code.
3427                  * Under Windows, it is necessary to allocate one page at a time,
3428                  * "touching" stack after each successful sub-allocation. This is
3429                  * because of the way stack growth is implemented - there is a
3430                  * guard page before the lowest stack page that is currently commited.
3431                  * Stack normally grows sequentially so OS traps access to the
3432                  * guard page and commits more pages when needed.
3433                  */
3434                 amd64_test_reg_imm (code, sreg, ~0xFFF);
3435                 br[0] = code; x86_branch8 (code, X86_CC_Z, 0, FALSE);
3436
3437                 br[2] = code; /* loop */
3438                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 0x1000);
3439                 amd64_test_membase_reg (code, AMD64_RSP, 0, AMD64_RSP);
3440                 amd64_alu_reg_imm (code, X86_SUB, sreg, 0x1000);
3441                 amd64_alu_reg_imm (code, X86_CMP, sreg, 0x1000);
3442                 br[3] = code; x86_branch8 (code, X86_CC_AE, 0, FALSE);
3443                 amd64_patch (br[3], br[2]);
3444                 amd64_test_reg_reg (code, sreg, sreg);
3445                 br[4] = code; x86_branch8 (code, X86_CC_Z, 0, FALSE);
3446                 amd64_alu_reg_reg (code, X86_SUB, AMD64_RSP, sreg);
3447
3448                 br[1] = code; x86_jump8 (code, 0);
3449
3450                 amd64_patch (br[0], code);
3451                 amd64_alu_reg_reg (code, X86_SUB, AMD64_RSP, sreg);
3452                 amd64_patch (br[1], code);
3453                 amd64_patch (br[4], code);
3454         }
3455         else
3456                 amd64_alu_reg_reg (code, X86_SUB, AMD64_RSP, tree->sreg1);
3457
3458         if (tree->flags & MONO_INST_INIT) {
3459                 int offset = 0;
3460                 if (tree->dreg != AMD64_RAX && sreg != AMD64_RAX) {
3461                         amd64_push_reg (code, AMD64_RAX);
3462                         offset += 8;
3463                 }
3464                 if (tree->dreg != AMD64_RCX && sreg != AMD64_RCX) {
3465                         amd64_push_reg (code, AMD64_RCX);
3466                         offset += 8;
3467                 }
3468                 if (tree->dreg != AMD64_RDI && sreg != AMD64_RDI) {
3469                         amd64_push_reg (code, AMD64_RDI);
3470                         offset += 8;
3471                 }
3472
3473                 amd64_shift_reg_imm (code, X86_SHR, sreg, 3);
3474                 if (sreg != AMD64_RCX)
3475                         amd64_mov_reg_reg (code, AMD64_RCX, sreg, 8);
3476                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
3477
3478                 amd64_lea_membase (code, AMD64_RDI, AMD64_RSP, offset);
3479                 if (cfg->param_area && cfg->arch.no_pushes)
3480                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RDI, cfg->param_area);
3481                 amd64_cld (code);
3482 #if defined(__default_codegen__)
3483                 amd64_prefix (code, X86_REP_PREFIX);
3484                 amd64_stosl (code);
3485 #elif defined(__native_client_codegen__)
3486                 /* NaCl stos pseudo-instruction */
3487                 amd64_codegen_pre(code);
3488                 /* First, clear the upper 32 bits of RDI (mov %edi, %edi)  */
3489                 amd64_mov_reg_reg (code, AMD64_RDI, AMD64_RDI, 4);
3490                 /* Add %r15 to %rdi using lea, condition flags unaffected. */
3491                 amd64_lea_memindex_size (code, AMD64_RDI, AMD64_R15, 0, AMD64_RDI, 0, 8);
3492                 amd64_prefix (code, X86_REP_PREFIX);
3493                 amd64_stosl (code);
3494                 amd64_codegen_post(code);
3495 #endif /* __native_client_codegen__ */
3496
3497                 if (tree->dreg != AMD64_RDI && sreg != AMD64_RDI)
3498                         amd64_pop_reg (code, AMD64_RDI);
3499                 if (tree->dreg != AMD64_RCX && sreg != AMD64_RCX)
3500                         amd64_pop_reg (code, AMD64_RCX);
3501                 if (tree->dreg != AMD64_RAX && sreg != AMD64_RAX)
3502                         amd64_pop_reg (code, AMD64_RAX);
3503         }
3504         return code;
3505 }
3506
3507 static guint8*
3508 emit_move_return_value (MonoCompile *cfg, MonoInst *ins, guint8 *code)
3509 {
3510         CallInfo *cinfo;
3511         guint32 quad;
3512
3513         /* Move return value to the target register */
3514         /* FIXME: do this in the local reg allocator */
3515         switch (ins->opcode) {
3516         case OP_CALL:
3517         case OP_CALL_REG:
3518         case OP_CALL_MEMBASE:
3519         case OP_LCALL:
3520         case OP_LCALL_REG:
3521         case OP_LCALL_MEMBASE:
3522                 g_assert (ins->dreg == AMD64_RAX);
3523                 break;
3524         case OP_FCALL:
3525         case OP_FCALL_REG:
3526         case OP_FCALL_MEMBASE:
3527                 if (((MonoCallInst*)ins)->signature->ret->type == MONO_TYPE_R4) {
3528                         amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, AMD64_XMM0);
3529                 }
3530                 else {
3531                         if (ins->dreg != AMD64_XMM0)
3532                                 amd64_sse_movsd_reg_reg (code, ins->dreg, AMD64_XMM0);
3533                 }
3534                 break;
3535         case OP_VCALL:
3536         case OP_VCALL_REG:
3537         case OP_VCALL_MEMBASE:
3538         case OP_VCALL2:
3539         case OP_VCALL2_REG:
3540         case OP_VCALL2_MEMBASE:
3541                 cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, ((MonoCallInst*)ins)->signature);
3542                 if (cinfo->ret.storage == ArgValuetypeInReg) {
3543                         MonoInst *loc = cfg->arch.vret_addr_loc;
3544
3545                         /* Load the destination address */
3546                         g_assert (loc->opcode == OP_REGOFFSET);
3547                         amd64_mov_reg_membase (code, AMD64_RCX, loc->inst_basereg, loc->inst_offset, sizeof(gpointer));
3548
3549                         for (quad = 0; quad < 2; quad ++) {
3550                                 switch (cinfo->ret.pair_storage [quad]) {
3551                                 case ArgInIReg:
3552                                         amd64_mov_membase_reg (code, AMD64_RCX, (quad * sizeof(mgreg_t)), cinfo->ret.pair_regs [quad], sizeof(mgreg_t));
3553                                         break;
3554                                 case ArgInFloatSSEReg:
3555                                         amd64_movss_membase_reg (code, AMD64_RCX, (quad * 8), cinfo->ret.pair_regs [quad]);
3556                                         break;
3557                                 case ArgInDoubleSSEReg:
3558                                         amd64_movsd_membase_reg (code, AMD64_RCX, (quad * 8), cinfo->ret.pair_regs [quad]);
3559                                         break;
3560                                 case ArgNone:
3561                                         break;
3562                                 default:
3563                                         NOT_IMPLEMENTED;
3564                                 }
3565                         }
3566                 }
3567                 break;
3568         }
3569
3570         return code;
3571 }
3572
3573 #endif /* DISABLE_JIT */
3574
3575 /*
3576  * mono_amd64_emit_tls_get:
3577  * @code: buffer to store code to
3578  * @dreg: hard register where to place the result
3579  * @tls_offset: offset info
3580  *
3581  * mono_amd64_emit_tls_get emits in @code the native code that puts in
3582  * the dreg register the item in the thread local storage identified
3583  * by tls_offset.
3584  *
3585  * Returns: a pointer to the end of the stored code
3586  */
3587 guint8*
3588 mono_amd64_emit_tls_get (guint8* code, int dreg, int tls_offset)
3589 {
3590 #ifdef HOST_WIN32
3591         g_assert (tls_offset < 64);
3592         x86_prefix (code, X86_GS_PREFIX);
3593         amd64_mov_reg_mem (code, dreg, (tls_offset * 8) + 0x1480, 8);
3594 #else
3595         if (optimize_for_xen) {
3596                 x86_prefix (code, X86_FS_PREFIX);
3597                 amd64_mov_reg_mem (code, dreg, 0, 8);
3598                 amd64_mov_reg_membase (code, dreg, dreg, tls_offset, 8);
3599         } else {
3600                 x86_prefix (code, X86_FS_PREFIX);
3601                 amd64_mov_reg_mem (code, dreg, tls_offset, 8);
3602         }
3603 #endif
3604         return code;
3605 }
3606
3607 #define REAL_PRINT_REG(text,reg) \
3608 mono_assert (reg >= 0); \
3609 amd64_push_reg (code, AMD64_RAX); \
3610 amd64_push_reg (code, AMD64_RDX); \
3611 amd64_push_reg (code, AMD64_RCX); \
3612 amd64_push_reg (code, reg); \
3613 amd64_push_imm (code, reg); \
3614 amd64_push_imm (code, text " %d %p\n"); \
3615 amd64_mov_reg_imm (code, AMD64_RAX, printf); \
3616 amd64_call_reg (code, AMD64_RAX); \
3617 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 3*4); \
3618 amd64_pop_reg (code, AMD64_RCX); \
3619 amd64_pop_reg (code, AMD64_RDX); \
3620 amd64_pop_reg (code, AMD64_RAX);
3621
3622 /* benchmark and set based on cpu */
3623 #define LOOP_ALIGNMENT 8
3624 #define bb_is_loop_start(bb) ((bb)->loop_body_start && (bb)->nesting)
3625
3626 #ifndef DISABLE_JIT
3627
3628 #if defined(__native_client__) || defined(__native_client_codegen__)
3629 void mono_nacl_gc()
3630 {
3631 #ifdef __native_client_gc__
3632         __nacl_suspend_thread_if_needed();
3633 #endif
3634 }
3635 #endif
3636
3637 void
3638 mono_arch_output_basic_block (MonoCompile *cfg, MonoBasicBlock *bb)
3639 {
3640         MonoInst *ins;
3641         MonoCallInst *call;
3642         guint offset;
3643         guint8 *code = cfg->native_code + cfg->code_len;
3644         MonoInst *last_ins = NULL;
3645         guint last_offset = 0;
3646         int max_len;
3647
3648         /* Fix max_offset estimate for each successor bb */
3649         if (cfg->opt & MONO_OPT_BRANCH) {
3650                 int current_offset = cfg->code_len;
3651                 MonoBasicBlock *current_bb;
3652                 for (current_bb = bb; current_bb != NULL; current_bb = current_bb->next_bb) {
3653                         current_bb->max_offset = current_offset;
3654                         current_offset += current_bb->max_length;
3655                 }
3656         }
3657
3658         if (cfg->opt & MONO_OPT_LOOP) {
3659                 int pad, align = LOOP_ALIGNMENT;
3660                 /* set alignment depending on cpu */
3661                 if (bb_is_loop_start (bb) && (pad = (cfg->code_len & (align - 1)))) {
3662                         pad = align - pad;
3663                         /*g_print ("adding %d pad at %x to loop in %s\n", pad, cfg->code_len, cfg->method->name);*/
3664                         amd64_padding (code, pad);
3665                         cfg->code_len += pad;
3666                         bb->native_offset = cfg->code_len;
3667                 }
3668         }
3669
3670 #if defined(__native_client_codegen__)
3671         /* For Native Client, all indirect call/jump targets must be */
3672         /* 32-byte aligned.  Exception handler blocks are jumped to  */
3673         /* indirectly as well.                                       */
3674         gboolean bb_needs_alignment = (bb->flags & BB_INDIRECT_JUMP_TARGET) ||
3675                                       (bb->flags & BB_EXCEPTION_HANDLER);
3676
3677         if ( bb_needs_alignment && ((cfg->code_len & kNaClAlignmentMask) != 0)) {
3678                 int pad = kNaClAlignment - (cfg->code_len & kNaClAlignmentMask);
3679                 if (pad != kNaClAlignment) code = mono_arch_nacl_pad(code, pad);
3680                 cfg->code_len += pad;
3681                 bb->native_offset = cfg->code_len;
3682         }
3683 #endif  /*__native_client_codegen__*/
3684
3685         if (cfg->verbose_level > 2)
3686                 g_print ("Basic block %d starting at offset 0x%x\n", bb->block_num, bb->native_offset);
3687
3688         if (cfg->prof_options & MONO_PROFILE_COVERAGE) {
3689                 MonoProfileCoverageInfo *cov = cfg->coverage_info;
3690                 g_assert (!cfg->compile_aot);
3691
3692                 cov->data [bb->dfn].cil_code = bb->cil_code;
3693                 amd64_mov_reg_imm (code, AMD64_R11, (guint64)&cov->data [bb->dfn].count);
3694                 /* this is not thread save, but good enough */
3695                 amd64_inc_membase (code, AMD64_R11, 0);
3696         }
3697
3698         offset = code - cfg->native_code;
3699
3700         mono_debug_open_block (cfg, bb, offset);
3701
3702     if (mono_break_at_bb_method && mono_method_desc_full_match (mono_break_at_bb_method, cfg->method) && bb->block_num == mono_break_at_bb_bb_num)
3703                 x86_breakpoint (code);
3704
3705         MONO_BB_FOR_EACH_INS (bb, ins) {
3706                 offset = code - cfg->native_code;
3707
3708                 max_len = ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
3709
3710 #define EXTRA_CODE_SPACE (NACL_SIZE (16, 16 + kNaClAlignment))
3711
3712                 if (G_UNLIKELY (offset > (cfg->code_size - max_len - EXTRA_CODE_SPACE))) {
3713                         cfg->code_size *= 2;
3714                         cfg->native_code = mono_realloc_native_code(cfg);
3715                         code = cfg->native_code + offset;
3716                         mono_jit_stats.code_reallocs++;
3717                 }
3718
3719                 if (cfg->debug_info)
3720                         mono_debug_record_line_number (cfg, ins, offset);
3721
3722                 switch (ins->opcode) {
3723                 case OP_BIGMUL:
3724                         amd64_mul_reg (code, ins->sreg2, TRUE);
3725                         break;
3726                 case OP_BIGMUL_UN:
3727                         amd64_mul_reg (code, ins->sreg2, FALSE);
3728                         break;
3729                 case OP_X86_SETEQ_MEMBASE:
3730                         amd64_set_membase (code, X86_CC_EQ, ins->inst_basereg, ins->inst_offset, TRUE);
3731                         break;
3732                 case OP_STOREI1_MEMBASE_IMM:
3733                         amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 1);
3734                         break;
3735                 case OP_STOREI2_MEMBASE_IMM:
3736                         amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 2);
3737                         break;
3738                 case OP_STOREI4_MEMBASE_IMM:
3739                         amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 4);
3740                         break;
3741                 case OP_STOREI1_MEMBASE_REG:
3742                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 1);
3743                         break;
3744                 case OP_STOREI2_MEMBASE_REG:
3745                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 2);
3746                         break;
3747                 /* In AMD64 NaCl, pointers are 4 bytes, */
3748                 /*  so STORE_* != STOREI8_*. Likewise below. */
3749                 case OP_STORE_MEMBASE_REG:
3750                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, sizeof(gpointer));
3751                         break;
3752                 case OP_STOREI8_MEMBASE_REG:
3753                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 8);
3754                         break;
3755                 case OP_STOREI4_MEMBASE_REG:
3756                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 4);
3757                         break;
3758                 case OP_STORE_MEMBASE_IMM:
3759 #ifndef __native_client_codegen__
3760                         /* In NaCl, this could be a PCONST type, which could */
3761                         /* mean a pointer type was copied directly into the  */
3762                         /* lower 32-bits of inst_imm, so for InvalidPtr==-1  */
3763                         /* the value would be 0x00000000FFFFFFFF which is    */
3764                         /* not proper for an imm32 unless you cast it.       */
3765                         g_assert (amd64_is_imm32 (ins->inst_imm));
3766 #endif
3767                         amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, (gint32)ins->inst_imm, sizeof(gpointer));
3768                         break;
3769                 case OP_STOREI8_MEMBASE_IMM:
3770                         g_assert (amd64_is_imm32 (ins->inst_imm));
3771                         amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 8);
3772                         break;
3773                 case OP_LOAD_MEM:
3774 #ifdef __mono_ilp32__
3775                         /* In ILP32, pointers are 4 bytes, so separate these */
3776                         /* cases, use literal 8 below where we really want 8 */
3777                         amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
3778                         amd64_mov_reg_membase (code, ins->dreg, ins->dreg, 0, sizeof(gpointer));
3779                         break;
3780 #endif
3781                 case OP_LOADI8_MEM:
3782                         // FIXME: Decompose this earlier
3783                         if (amd64_is_imm32 (ins->inst_imm))
3784                                 amd64_mov_reg_mem (code, ins->dreg, ins->inst_imm, 8);
3785                         else {
3786                                 amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
3787                                 amd64_mov_reg_membase (code, ins->dreg, ins->dreg, 0, 8);
3788                         }
3789                         break;
3790                 case OP_LOADI4_MEM:
3791                         amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
3792                         amd64_movsxd_reg_membase (code, ins->dreg, ins->dreg, 0);
3793                         break;
3794                 case OP_LOADU4_MEM:
3795                         // FIXME: Decompose this earlier
3796                         if (amd64_is_imm32 (ins->inst_imm))
3797                                 amd64_mov_reg_mem (code, ins->dreg, ins->inst_imm, 4);
3798                         else {
3799                                 amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
3800                                 amd64_mov_reg_membase (code, ins->dreg, ins->dreg, 0, 4);
3801                         }
3802                         break;
3803                 case OP_LOADU1_MEM:
3804                         amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
3805                         amd64_widen_membase (code, ins->dreg, ins->dreg, 0, FALSE, FALSE);
3806                         break;
3807                 case OP_LOADU2_MEM:
3808                         /* For NaCl, pointers are 4 bytes, so separate these */
3809                         /* cases, use literal 8 below where we really want 8 */
3810                         amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
3811                         amd64_widen_membase (code, ins->dreg, ins->dreg, 0, FALSE, TRUE);
3812                         break;
3813                 case OP_LOAD_MEMBASE:
3814                         g_assert (amd64_is_imm32 (ins->inst_offset));
3815                         amd64_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, sizeof(gpointer));
3816                         break;
3817                 case OP_LOADI8_MEMBASE:
3818                         /* Use literal 8 instead of sizeof pointer or */
3819                         /* register, we really want 8 for this opcode */
3820                         g_assert (amd64_is_imm32 (ins->inst_offset));
3821                         amd64_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, 8);
3822                         break;
3823                 case OP_LOADI4_MEMBASE:
3824                         amd64_movsxd_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
3825                         break;
3826                 case OP_LOADU4_MEMBASE:
3827                         amd64_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, 4);
3828                         break;
3829                 case OP_LOADU1_MEMBASE:
3830                         /* The cpu zero extends the result into 64 bits */
3831                         amd64_widen_membase_size (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, FALSE, 4);
3832                         break;
3833                 case OP_LOADI1_MEMBASE:
3834                         amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, FALSE);
3835                         break;
3836                 case OP_LOADU2_MEMBASE:
3837                         /* The cpu zero extends the result into 64 bits */
3838                         amd64_widen_membase_size (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, TRUE, 4);
3839                         break;
3840                 case OP_LOADI2_MEMBASE:
3841                         amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, TRUE);
3842                         break;
3843                 case OP_AMD64_LOADI8_MEMINDEX:
3844                         amd64_mov_reg_memindex_size (code, ins->dreg, ins->inst_basereg, 0, ins->inst_indexreg, 0, 8);
3845                         break;
3846                 case OP_LCONV_TO_I1:
3847                 case OP_ICONV_TO_I1:
3848                 case OP_SEXT_I1:
3849                         amd64_widen_reg (code, ins->dreg, ins->sreg1, TRUE, FALSE);
3850                         break;
3851                 case OP_LCONV_TO_I2:
3852                 case OP_ICONV_TO_I2:
3853                 case OP_SEXT_I2:
3854                         amd64_widen_reg (code, ins->dreg, ins->sreg1, TRUE, TRUE);
3855                         break;
3856                 case OP_LCONV_TO_U1:
3857                 case OP_ICONV_TO_U1:
3858                         amd64_widen_reg (code, ins->dreg, ins->sreg1, FALSE, FALSE);
3859                         break;
3860                 case OP_LCONV_TO_U2:
3861                 case OP_ICONV_TO_U2:
3862                         amd64_widen_reg (code, ins->dreg, ins->sreg1, FALSE, TRUE);
3863                         break;
3864                 case OP_ZEXT_I4:
3865                         /* Clean out the upper word */
3866                         amd64_mov_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
3867                         break;
3868                 case OP_SEXT_I4:
3869                         amd64_movsxd_reg_reg (code, ins->dreg, ins->sreg1);
3870                         break;
3871                 case OP_COMPARE:
3872                 case OP_LCOMPARE:
3873                         amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
3874                         break;
3875                 case OP_COMPARE_IMM:
3876                 case OP_LCOMPARE_IMM:
3877                         g_assert (amd64_is_imm32 (ins->inst_imm));
3878                         amd64_alu_reg_imm (code, X86_CMP, ins->sreg1, ins->inst_imm);
3879                         break;
3880                 case OP_X86_COMPARE_REG_MEMBASE:
3881                         amd64_alu_reg_membase (code, X86_CMP, ins->sreg1, ins->sreg2, ins->inst_offset);
3882                         break;
3883                 case OP_X86_TEST_NULL:
3884                         amd64_test_reg_reg_size (code, ins->sreg1, ins->sreg1, 4);
3885                         break;
3886                 case OP_AMD64_TEST_NULL:
3887                         amd64_test_reg_reg (code, ins->sreg1, ins->sreg1);
3888                         break;
3889
3890                 case OP_X86_ADD_REG_MEMBASE:
3891                         amd64_alu_reg_membase_size (code, X86_ADD, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
3892                         break;
3893                 case OP_X86_SUB_REG_MEMBASE:
3894                         amd64_alu_reg_membase_size (code, X86_SUB, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
3895                         break;
3896                 case OP_X86_AND_REG_MEMBASE:
3897                         amd64_alu_reg_membase_size (code, X86_AND, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
3898                         break;
3899                 case OP_X86_OR_REG_MEMBASE:
3900                         amd64_alu_reg_membase_size (code, X86_OR, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
3901                         break;
3902                 case OP_X86_XOR_REG_MEMBASE:
3903                         amd64_alu_reg_membase_size (code, X86_XOR, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
3904                         break;
3905
3906                 case OP_X86_ADD_MEMBASE_IMM:
3907                         /* FIXME: Make a 64 version too */
3908                         amd64_alu_membase_imm_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
3909                         break;
3910                 case OP_X86_SUB_MEMBASE_IMM:
3911                         g_assert (amd64_is_imm32 (ins->inst_imm));
3912                         amd64_alu_membase_imm_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
3913                         break;
3914                 case OP_X86_AND_MEMBASE_IMM:
3915                         g_assert (amd64_is_imm32 (ins->inst_imm));
3916                         amd64_alu_membase_imm_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
3917                         break;
3918                 case OP_X86_OR_MEMBASE_IMM:
3919                         g_assert (amd64_is_imm32 (ins->inst_imm));
3920                         amd64_alu_membase_imm_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
3921                         break;
3922                 case OP_X86_XOR_MEMBASE_IMM:
3923                         g_assert (amd64_is_imm32 (ins->inst_imm));
3924                         amd64_alu_membase_imm_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
3925                         break;
3926                 case OP_X86_ADD_MEMBASE_REG:
3927                         amd64_alu_membase_reg_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
3928                         break;
3929                 case OP_X86_SUB_MEMBASE_REG:
3930                         amd64_alu_membase_reg_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
3931                         break;
3932                 case OP_X86_AND_MEMBASE_REG:
3933                         amd64_alu_membase_reg_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
3934                         break;
3935                 case OP_X86_OR_MEMBASE_REG:
3936                         amd64_alu_membase_reg_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
3937                         break;
3938                 case OP_X86_XOR_MEMBASE_REG:
3939                         amd64_alu_membase_reg_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
3940                         break;
3941                 case OP_X86_INC_MEMBASE:
3942                         amd64_inc_membase_size (code, ins->inst_basereg, ins->inst_offset, 4);
3943                         break;
3944                 case OP_X86_INC_REG:
3945                         amd64_inc_reg_size (code, ins->dreg, 4);
3946                         break;
3947                 case OP_X86_DEC_MEMBASE:
3948                         amd64_dec_membase_size (code, ins->inst_basereg, ins->inst_offset, 4);
3949                         break;
3950                 case OP_X86_DEC_REG:
3951                         amd64_dec_reg_size (code, ins->dreg, 4);
3952                         break;
3953                 case OP_X86_MUL_REG_MEMBASE:
3954                 case OP_X86_MUL_MEMBASE_REG:
3955                         amd64_imul_reg_membase_size (code, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
3956                         break;
3957                 case OP_AMD64_ICOMPARE_MEMBASE_REG:
3958                         amd64_alu_membase_reg_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
3959                         break;
3960                 case OP_AMD64_ICOMPARE_MEMBASE_IMM:
3961                         amd64_alu_membase_imm_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
3962                         break;
3963                 case OP_AMD64_COMPARE_MEMBASE_REG:
3964                         amd64_alu_membase_reg_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
3965                         break;
3966                 case OP_AMD64_COMPARE_MEMBASE_IMM:
3967                         g_assert (amd64_is_imm32 (ins->inst_imm));
3968                         amd64_alu_membase_imm_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
3969                         break;
3970                 case OP_X86_COMPARE_MEMBASE8_IMM:
3971                         amd64_alu_membase8_imm_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
3972                         break;
3973                 case OP_AMD64_ICOMPARE_REG_MEMBASE:
3974                         amd64_alu_reg_membase_size (code, X86_CMP, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
3975                         break;
3976                 case OP_AMD64_COMPARE_REG_MEMBASE:
3977                         amd64_alu_reg_membase_size (code, X86_CMP, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
3978                         break;
3979
3980                 case OP_AMD64_ADD_REG_MEMBASE:
3981                         amd64_alu_reg_membase_size (code, X86_ADD, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
3982                         break;
3983                 case OP_AMD64_SUB_REG_MEMBASE:
3984                         amd64_alu_reg_membase_size (code, X86_SUB, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
3985                         break;
3986                 case OP_AMD64_AND_REG_MEMBASE:
3987                         amd64_alu_reg_membase_size (code, X86_AND, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
3988                         break;
3989                 case OP_AMD64_OR_REG_MEMBASE:
3990                         amd64_alu_reg_membase_size (code, X86_OR, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
3991                         break;
3992                 case OP_AMD64_XOR_REG_MEMBASE:
3993                         amd64_alu_reg_membase_size (code, X86_XOR, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
3994                         break;
3995
3996                 case OP_AMD64_ADD_MEMBASE_REG:
3997                         amd64_alu_membase_reg_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
3998                         break;
3999                 case OP_AMD64_SUB_MEMBASE_REG:
4000                         amd64_alu_membase_reg_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
4001                         break;
4002                 case OP_AMD64_AND_MEMBASE_REG:
4003                         amd64_alu_membase_reg_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
4004                         break;
4005                 case OP_AMD64_OR_MEMBASE_REG:
4006                         amd64_alu_membase_reg_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
4007                         break;
4008                 case OP_AMD64_XOR_MEMBASE_REG:
4009                         amd64_alu_membase_reg_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
4010                         break;
4011
4012                 case OP_AMD64_ADD_MEMBASE_IMM:
4013                         g_assert (amd64_is_imm32 (ins->inst_imm));
4014                         amd64_alu_membase_imm_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
4015                         break;
4016                 case OP_AMD64_SUB_MEMBASE_IMM:
4017                         g_assert (amd64_is_imm32 (ins->inst_imm));
4018                         amd64_alu_membase_imm_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
4019                         break;
4020                 case OP_AMD64_AND_MEMBASE_IMM:
4021                         g_assert (amd64_is_imm32 (ins->inst_imm));
4022                         amd64_alu_membase_imm_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
4023                         break;
4024                 case OP_AMD64_OR_MEMBASE_IMM:
4025                         g_assert (amd64_is_imm32 (ins->inst_imm));
4026                         amd64_alu_membase_imm_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
4027                         break;
4028                 case OP_AMD64_XOR_MEMBASE_IMM:
4029                         g_assert (amd64_is_imm32 (ins->inst_imm));
4030                         amd64_alu_membase_imm_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
4031                         break;
4032
4033                 case OP_BREAK:
4034                         amd64_breakpoint (code);
4035                         break;
4036                 case OP_RELAXED_NOP:
4037                         x86_prefix (code, X86_REP_PREFIX);
4038                         x86_nop (code);
4039                         break;
4040                 case OP_HARD_NOP:
4041                         x86_nop (code);
4042                         break;
4043                 case OP_NOP:
4044                 case OP_DUMMY_USE:
4045                 case OP_DUMMY_STORE:
4046                 case OP_NOT_REACHED:
4047                 case OP_NOT_NULL:
4048                         break;
4049                 case OP_SEQ_POINT: {
4050                         int i;
4051
4052                         if (cfg->compile_aot)
4053                                 NOT_IMPLEMENTED;
4054
4055                         /*
4056                          * Read from the single stepping trigger page. This will cause a
4057                          * SIGSEGV when single stepping is enabled.
4058                          * We do this _before_ the breakpoint, so single stepping after
4059                          * a breakpoint is hit will step to the next IL offset.
4060                          */
4061                         if (ins->flags & MONO_INST_SINGLE_STEP_LOC) {
4062                                 if (((guint64)ss_trigger_page >> 32) == 0)
4063                                         amd64_mov_reg_mem (code, AMD64_R11, (guint64)ss_trigger_page, 4);
4064                                 else {
4065                                         MonoInst *var = cfg->arch.ss_trigger_page_var;
4066
4067                                         amd64_mov_reg_membase (code, AMD64_R11, var->inst_basereg, var->inst_offset, 8);
4068                                         amd64_alu_membase_imm_size (code, X86_CMP, AMD64_R11, 0, 0, 4);
4069                                 }
4070                         }
4071
4072                         /*
4073                          * This is the address which is saved in seq points,
4074                          * get_ip_for_single_step () / get_ip_for_breakpoint () needs to compute this
4075                          * from the address of the instruction causing the fault.
4076                          */
4077                         mono_add_seq_point (cfg, bb, ins, code - cfg->native_code);
4078
4079                         /*
4080                          * A placeholder for a possible breakpoint inserted by
4081                          * mono_arch_set_breakpoint ().
4082                          */
4083                         for (i = 0; i < breakpoint_size; ++i)
4084                                 x86_nop (code);
4085                         break;
4086                 }
4087                 case OP_ADDCC:
4088                 case OP_LADD:
4089                         amd64_alu_reg_reg (code, X86_ADD, ins->sreg1, ins->sreg2);
4090                         break;
4091                 case OP_ADC:
4092                         amd64_alu_reg_reg (code, X86_ADC, ins->sreg1, ins->sreg2);
4093                         break;
4094                 case OP_ADD_IMM:
4095                 case OP_LADD_IMM:
4096                         g_assert (amd64_is_imm32 (ins->inst_imm));
4097                         amd64_alu_reg_imm (code, X86_ADD, ins->dreg, ins->inst_imm);
4098                         break;
4099                 case OP_ADC_IMM:
4100                         g_assert (amd64_is_imm32 (ins->inst_imm));
4101                         amd64_alu_reg_imm (code, X86_ADC, ins->dreg, ins->inst_imm);
4102                         break;
4103                 case OP_SUBCC:
4104                 case OP_LSUB:
4105                         amd64_alu_reg_reg (code, X86_SUB, ins->sreg1, ins->sreg2);
4106                         break;
4107                 case OP_SBB:
4108                         amd64_alu_reg_reg (code, X86_SBB, ins->sreg1, ins->sreg2);
4109                         break;
4110                 case OP_SUB_IMM:
4111                 case OP_LSUB_IMM:
4112                         g_assert (amd64_is_imm32 (ins->inst_imm));
4113                         amd64_alu_reg_imm (code, X86_SUB, ins->dreg, ins->inst_imm);
4114                         break;
4115                 case OP_SBB_IMM:
4116                         g_assert (amd64_is_imm32 (ins->inst_imm));
4117                         amd64_alu_reg_imm (code, X86_SBB, ins->dreg, ins->inst_imm);
4118                         break;
4119                 case OP_LAND:
4120                         amd64_alu_reg_reg (code, X86_AND, ins->sreg1, ins->sreg2);
4121                         break;
4122                 case OP_AND_IMM:
4123                 case OP_LAND_IMM:
4124                         g_assert (amd64_is_imm32 (ins->inst_imm));
4125                         amd64_alu_reg_imm (code, X86_AND, ins->sreg1, ins->inst_imm);
4126                         break;
4127                 case OP_LMUL:
4128                         amd64_imul_reg_reg (code, ins->sreg1, ins->sreg2);
4129                         break;
4130                 case OP_MUL_IMM:
4131                 case OP_LMUL_IMM:
4132                 case OP_IMUL_IMM: {
4133                         guint32 size = (ins->opcode == OP_IMUL_IMM) ? 4 : 8;
4134
4135                         switch (ins->inst_imm) {
4136                         case 2:
4137                                 /* MOV r1, r2 */
4138                                 /* ADD r1, r1 */
4139                                 if (ins->dreg != ins->sreg1)
4140                                         amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, size);
4141                                 amd64_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
4142                                 break;
4143                         case 3:
4144                                 /* LEA r1, [r2 + r2*2] */
4145                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
4146                                 break;
4147                         case 5:
4148                                 /* LEA r1, [r2 + r2*4] */
4149                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
4150                                 break;
4151                         case 6:
4152                                 /* LEA r1, [r2 + r2*2] */
4153                                 /* ADD r1, r1          */
4154                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
4155                                 amd64_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
4156                                 break;
4157                         case 9:
4158                                 /* LEA r1, [r2 + r2*8] */
4159                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 3);
4160                                 break;
4161                         case 10:
4162                                 /* LEA r1, [r2 + r2*4] */
4163                                 /* ADD r1, r1          */
4164                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
4165                                 amd64_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
4166                                 break;
4167                         case 12:
4168                                 /* LEA r1, [r2 + r2*2] */
4169                                 /* SHL r1, 2           */
4170                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
4171                                 amd64_shift_reg_imm (code, X86_SHL, ins->dreg, 2);
4172                                 break;
4173                         case 25:
4174                                 /* LEA r1, [r2 + r2*4] */
4175                                 /* LEA r1, [r1 + r1*4] */
4176                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
4177                                 amd64_lea_memindex (code, ins->dreg, ins->dreg, 0, ins->dreg, 2);
4178                                 break;
4179                         case 100:
4180                                 /* LEA r1, [r2 + r2*4] */
4181                                 /* SHL r1, 2           */
4182                                 /* LEA r1, [r1 + r1*4] */
4183                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
4184                                 amd64_shift_reg_imm (code, X86_SHL, ins->dreg, 2);
4185                                 amd64_lea_memindex (code, ins->dreg, ins->dreg, 0, ins->dreg, 2);
4186                                 break;
4187                         default:
4188                                 amd64_imul_reg_reg_imm_size (code, ins->dreg, ins->sreg1, ins->inst_imm, size);
4189                                 break;
4190                         }
4191                         break;
4192                 }
4193                 case OP_LDIV:
4194                 case OP_LREM:
4195                         /* Regalloc magic makes the div/rem cases the same */
4196                         if (ins->sreg2 == AMD64_RDX) {
4197                                 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
4198                                 amd64_cdq (code);
4199                                 amd64_div_membase (code, AMD64_RSP, -8, TRUE);
4200                         } else {
4201                                 amd64_cdq (code);
4202                                 amd64_div_reg (code, ins->sreg2, TRUE);
4203                         }
4204                         break;
4205                 case OP_LDIV_UN:
4206                 case OP_LREM_UN:
4207                         if (ins->sreg2 == AMD64_RDX) {
4208                                 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
4209                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
4210                                 amd64_div_membase (code, AMD64_RSP, -8, FALSE);
4211                         } else {
4212                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
4213                                 amd64_div_reg (code, ins->sreg2, FALSE);
4214                         }
4215                         break;
4216                 case OP_IDIV:
4217                 case OP_IREM:
4218                         if (ins->sreg2 == AMD64_RDX) {
4219                                 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
4220                                 amd64_cdq_size (code, 4);
4221                                 amd64_div_membase_size (code, AMD64_RSP, -8, TRUE, 4);
4222                         } else {
4223                                 amd64_cdq_size (code, 4);
4224                                 amd64_div_reg_size (code, ins->sreg2, TRUE, 4);
4225                         }
4226                         break;
4227                 case OP_IDIV_UN:
4228                 case OP_IREM_UN:
4229                         if (ins->sreg2 == AMD64_RDX) {
4230                                 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
4231                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
4232                                 amd64_div_membase_size (code, AMD64_RSP, -8, FALSE, 4);
4233                         } else {
4234                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
4235                                 amd64_div_reg_size (code, ins->sreg2, FALSE, 4);
4236                         }
4237                         break;
4238                 case OP_IREM_IMM: {
4239                         int power = mono_is_power_of_two (ins->inst_imm);
4240
4241                         g_assert (ins->sreg1 == X86_EAX);
4242                         g_assert (ins->dreg == X86_EAX);
4243                         g_assert (power >= 0);
4244
4245                         if (power == 0) {
4246                                 amd64_mov_reg_imm (code, ins->dreg, 0);
4247                                 break;
4248                         }
4249
4250                         /* Based on gcc code */
4251
4252                         /* Add compensation for negative dividents */
4253                         amd64_mov_reg_reg_size (code, AMD64_RDX, AMD64_RAX, 4);
4254                         if (power > 1)
4255                                 amd64_shift_reg_imm_size (code, X86_SAR, AMD64_RDX, 31, 4);
4256                         amd64_shift_reg_imm_size (code, X86_SHR, AMD64_RDX, 32 - power, 4);
4257                         amd64_alu_reg_reg_size (code, X86_ADD, AMD64_RAX, AMD64_RDX, 4);
4258                         /* Compute remainder */
4259                         amd64_alu_reg_imm_size (code, X86_AND, AMD64_RAX, (1 << power) - 1, 4);
4260                         /* Remove compensation */
4261                         amd64_alu_reg_reg_size (code, X86_SUB, AMD64_RAX, AMD64_RDX, 4);
4262                         break;
4263                 }
4264                 case OP_LMUL_OVF:
4265                         amd64_imul_reg_reg (code, ins->sreg1, ins->sreg2);
4266                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
4267                         break;
4268                 case OP_LOR:
4269                         amd64_alu_reg_reg (code, X86_OR, ins->sreg1, ins->sreg2);
4270                         break;
4271                 case OP_OR_IMM:
4272                 case OP_LOR_IMM:
4273                         g_assert (amd64_is_imm32 (ins->inst_imm));
4274                         amd64_alu_reg_imm (code, X86_OR, ins->sreg1, ins->inst_imm);
4275                         break;
4276                 case OP_LXOR:
4277                         amd64_alu_reg_reg (code, X86_XOR, ins->sreg1, ins->sreg2);
4278                         break;
4279                 case OP_XOR_IMM:
4280                 case OP_LXOR_IMM:
4281                         g_assert (amd64_is_imm32 (ins->inst_imm));
4282                         amd64_alu_reg_imm (code, X86_XOR, ins->sreg1, ins->inst_imm);
4283                         break;
4284                 case OP_LSHL:
4285                         g_assert (ins->sreg2 == AMD64_RCX);
4286                         amd64_shift_reg (code, X86_SHL, ins->dreg);
4287                         break;
4288                 case OP_LSHR:
4289                         g_assert (ins->sreg2 == AMD64_RCX);
4290                         amd64_shift_reg (code, X86_SAR, ins->dreg);
4291                         break;
4292                 case OP_SHR_IMM:
4293                         g_assert (amd64_is_imm32 (ins->inst_imm));
4294                         amd64_shift_reg_imm_size (code, X86_SAR, ins->dreg, ins->inst_imm, 4);
4295                         break;
4296                 case OP_LSHR_IMM:
4297                         g_assert (amd64_is_imm32 (ins->inst_imm));
4298                         amd64_shift_reg_imm (code, X86_SAR, ins->dreg, ins->inst_imm);
4299                         break;
4300                 case OP_SHR_UN_IMM:
4301                         g_assert (amd64_is_imm32 (ins->inst_imm));
4302                         amd64_shift_reg_imm_size (code, X86_SHR, ins->dreg, ins->inst_imm, 4);
4303                         break;
4304                 case OP_LSHR_UN_IMM:
4305                         g_assert (amd64_is_imm32 (ins->inst_imm));
4306                         amd64_shift_reg_imm (code, X86_SHR, ins->dreg, ins->inst_imm);
4307                         break;
4308                 case OP_LSHR_UN:
4309                         g_assert (ins->sreg2 == AMD64_RCX);
4310                         amd64_shift_reg (code, X86_SHR, ins->dreg);
4311                         break;
4312                 case OP_SHL_IMM:
4313                         g_assert (amd64_is_imm32 (ins->inst_imm));
4314                         amd64_shift_reg_imm_size (code, X86_SHL, ins->dreg, ins->inst_imm, 4);
4315                         break;
4316                 case OP_LSHL_IMM:
4317                         g_assert (amd64_is_imm32 (ins->inst_imm));
4318                         amd64_shift_reg_imm (code, X86_SHL, ins->dreg, ins->inst_imm);
4319                         break;
4320
4321                 case OP_IADDCC:
4322                 case OP_IADD:
4323                         amd64_alu_reg_reg_size (code, X86_ADD, ins->sreg1, ins->sreg2, 4);
4324                         break;
4325                 case OP_IADC:
4326                         amd64_alu_reg_reg_size (code, X86_ADC, ins->sreg1, ins->sreg2, 4);
4327                         break;
4328                 case OP_IADD_IMM:
4329                         amd64_alu_reg_imm_size (code, X86_ADD, ins->dreg, ins->inst_imm, 4);
4330                         break;
4331                 case OP_IADC_IMM:
4332                         amd64_alu_reg_imm_size (code, X86_ADC, ins->dreg, ins->inst_imm, 4);
4333                         break;
4334                 case OP_ISUBCC:
4335                 case OP_ISUB:
4336                         amd64_alu_reg_reg_size (code, X86_SUB, ins->sreg1, ins->sreg2, 4);
4337                         break;
4338                 case OP_ISBB:
4339                         amd64_alu_reg_reg_size (code, X86_SBB, ins->sreg1, ins->sreg2, 4);
4340                         break;
4341                 case OP_ISUB_IMM:
4342                         amd64_alu_reg_imm_size (code, X86_SUB, ins->dreg, ins->inst_imm, 4);
4343                         break;
4344                 case OP_ISBB_IMM:
4345                         amd64_alu_reg_imm_size (code, X86_SBB, ins->dreg, ins->inst_imm, 4);
4346                         break;
4347                 case OP_IAND:
4348                         amd64_alu_reg_reg_size (code, X86_AND, ins->sreg1, ins->sreg2, 4);
4349                         break;
4350                 case OP_IAND_IMM:
4351                         amd64_alu_reg_imm_size (code, X86_AND, ins->sreg1, ins->inst_imm, 4);
4352                         break;
4353                 case OP_IOR:
4354                         amd64_alu_reg_reg_size (code, X86_OR, ins->sreg1, ins->sreg2, 4);
4355                         break;
4356                 case OP_IOR_IMM:
4357                         amd64_alu_reg_imm_size (code, X86_OR, ins->sreg1, ins->inst_imm, 4);
4358                         break;
4359                 case OP_IXOR:
4360                         amd64_alu_reg_reg_size (code, X86_XOR, ins->sreg1, ins->sreg2, 4);
4361                         break;
4362                 case OP_IXOR_IMM:
4363                         amd64_alu_reg_imm_size (code, X86_XOR, ins->sreg1, ins->inst_imm, 4);
4364                         break;
4365                 case OP_INEG:
4366                         amd64_neg_reg_size (code, ins->sreg1, 4);
4367                         break;
4368                 case OP_INOT:
4369                         amd64_not_reg_size (code, ins->sreg1, 4);
4370                         break;
4371                 case OP_ISHL:
4372                         g_assert (ins->sreg2 == AMD64_RCX);
4373                         amd64_shift_reg_size (code, X86_SHL, ins->dreg, 4);
4374                         break;
4375                 case OP_ISHR:
4376                         g_assert (ins->sreg2 == AMD64_RCX);
4377                         amd64_shift_reg_size (code, X86_SAR, ins->dreg, 4);
4378                         break;
4379                 case OP_ISHR_IMM:
4380                         amd64_shift_reg_imm_size (code, X86_SAR, ins->dreg, ins->inst_imm, 4);
4381                         break;
4382                 case OP_ISHR_UN_IMM:
4383                         amd64_shift_reg_imm_size (code, X86_SHR, ins->dreg, ins->inst_imm, 4);
4384                         break;
4385                 case OP_ISHR_UN:
4386                         g_assert (ins->sreg2 == AMD64_RCX);
4387                         amd64_shift_reg_size (code, X86_SHR, ins->dreg, 4);
4388                         break;
4389                 case OP_ISHL_IMM:
4390                         amd64_shift_reg_imm_size (code, X86_SHL, ins->dreg, ins->inst_imm, 4);
4391                         break;
4392                 case OP_IMUL:
4393                         amd64_imul_reg_reg_size (code, ins->sreg1, ins->sreg2, 4);
4394                         break;
4395                 case OP_IMUL_OVF:
4396                         amd64_imul_reg_reg_size (code, ins->sreg1, ins->sreg2, 4);
4397                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
4398                         break;
4399                 case OP_IMUL_OVF_UN:
4400                 case OP_LMUL_OVF_UN: {
4401                         /* the mul operation and the exception check should most likely be split */
4402                         int non_eax_reg, saved_eax = FALSE, saved_edx = FALSE;
4403                         int size = (ins->opcode == OP_IMUL_OVF_UN) ? 4 : 8;
4404                         /*g_assert (ins->sreg2 == X86_EAX);
4405                         g_assert (ins->dreg == X86_EAX);*/
4406                         if (ins->sreg2 == X86_EAX) {
4407                                 non_eax_reg = ins->sreg1;
4408                         } else if (ins->sreg1 == X86_EAX) {
4409                                 non_eax_reg = ins->sreg2;
4410                         } else {
4411                                 /* no need to save since we're going to store to it anyway */
4412                                 if (ins->dreg != X86_EAX) {
4413                                         saved_eax = TRUE;
4414                                         amd64_push_reg (code, X86_EAX);
4415                                 }
4416                                 amd64_mov_reg_reg (code, X86_EAX, ins->sreg1, size);
4417                                 non_eax_reg = ins->sreg2;
4418                         }
4419                         if (ins->dreg == X86_EDX) {
4420                                 if (!saved_eax) {
4421                                         saved_eax = TRUE;
4422                                         amd64_push_reg (code, X86_EAX);
4423                                 }
4424                         } else {
4425                                 saved_edx = TRUE;
4426                                 amd64_push_reg (code, X86_EDX);
4427                         }
4428                         amd64_mul_reg_size (code, non_eax_reg, FALSE, size);
4429                         /* save before the check since pop and mov don't change the flags */
4430                         if (ins->dreg != X86_EAX)
4431                                 amd64_mov_reg_reg (code, ins->dreg, X86_EAX, size);
4432                         if (saved_edx)
4433                                 amd64_pop_reg (code, X86_EDX);
4434                         if (saved_eax)
4435                                 amd64_pop_reg (code, X86_EAX);
4436                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
4437                         break;
4438                 }
4439                 case OP_ICOMPARE:
4440                         amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
4441                         break;
4442                 case OP_ICOMPARE_IMM:
4443                         amd64_alu_reg_imm_size (code, X86_CMP, ins->sreg1, ins->inst_imm, 4);
4444                         break;
4445                 case OP_IBEQ:
4446                 case OP_IBLT:
4447                 case OP_IBGT:
4448                 case OP_IBGE:
4449                 case OP_IBLE:
4450                 case OP_LBEQ:
4451                 case OP_LBLT:
4452                 case OP_LBGT:
4453                 case OP_LBGE:
4454                 case OP_LBLE:
4455                 case OP_IBNE_UN:
4456                 case OP_IBLT_UN:
4457                 case OP_IBGT_UN:
4458                 case OP_IBGE_UN:
4459                 case OP_IBLE_UN:
4460                 case OP_LBNE_UN:
4461                 case OP_LBLT_UN:
4462                 case OP_LBGT_UN:
4463                 case OP_LBGE_UN:
4464                 case OP_LBLE_UN:
4465                         EMIT_COND_BRANCH (ins, cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)]);
4466                         break;
4467
4468                 case OP_CMOV_IEQ:
4469                 case OP_CMOV_IGE:
4470                 case OP_CMOV_IGT:
4471                 case OP_CMOV_ILE:
4472                 case OP_CMOV_ILT:
4473                 case OP_CMOV_INE_UN:
4474                 case OP_CMOV_IGE_UN:
4475                 case OP_CMOV_IGT_UN:
4476                 case OP_CMOV_ILE_UN:
4477                 case OP_CMOV_ILT_UN:
4478                 case OP_CMOV_LEQ:
4479                 case OP_CMOV_LGE:
4480                 case OP_CMOV_LGT:
4481                 case OP_CMOV_LLE:
4482                 case OP_CMOV_LLT:
4483                 case OP_CMOV_LNE_UN:
4484                 case OP_CMOV_LGE_UN:
4485                 case OP_CMOV_LGT_UN:
4486                 case OP_CMOV_LLE_UN:
4487                 case OP_CMOV_LLT_UN:
4488                         g_assert (ins->dreg == ins->sreg1);
4489                         /* This needs to operate on 64 bit values */
4490                         amd64_cmov_reg (code, cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)], ins->dreg, ins->sreg2);
4491                         break;
4492
4493                 case OP_LNOT:
4494                         amd64_not_reg (code, ins->sreg1);
4495                         break;
4496                 case OP_LNEG:
4497                         amd64_neg_reg (code, ins->sreg1);
4498                         break;
4499
4500                 case OP_ICONST:
4501                 case OP_I8CONST:
4502                         if ((((guint64)ins->inst_c0) >> 32) == 0)
4503                                 amd64_mov_reg_imm_size (code, ins->dreg, ins->inst_c0, 4);
4504                         else
4505                                 amd64_mov_reg_imm_size (code, ins->dreg, ins->inst_c0, 8);
4506                         break;
4507                 case OP_AOTCONST:
4508                         mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_i1, ins->inst_p0);
4509                         amd64_mov_reg_membase (code, ins->dreg, AMD64_RIP, 0, sizeof(gpointer));
4510                         break;
4511                 case OP_JUMP_TABLE:
4512                         mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_i1, ins->inst_p0);
4513                         amd64_mov_reg_imm_size (code, ins->dreg, 0, 8);
4514                         break;
4515                 case OP_MOVE:
4516                         amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, sizeof(mgreg_t));
4517                         break;
4518                 case OP_AMD64_SET_XMMREG_R4: {
4519                         amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg1);
4520                         break;
4521                 }
4522                 case OP_AMD64_SET_XMMREG_R8: {
4523                         if (ins->dreg != ins->sreg1)
4524                                 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
4525                         break;
4526                 }
4527                 case OP_TAILCALL: {
4528                         MonoCallInst *call = (MonoCallInst*)ins;
4529                         int pos = 0, i;
4530
4531                         /* FIXME: no tracing support... */
4532                         if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
4533                                 code = mono_arch_instrument_epilog_full (cfg, mono_profiler_method_leave, code, FALSE, FALSE);
4534
4535                         g_assert (!cfg->method->save_lmf);
4536
4537                         if (cfg->arch.omit_fp) {
4538                                 guint32 save_offset = 0;
4539                                 /* Pop callee-saved registers */
4540                                 for (i = 0; i < AMD64_NREG; ++i)
4541                                         if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
4542                                                 amd64_mov_reg_membase (code, i, AMD64_RSP, save_offset, 8);
4543                                                 save_offset += 8;
4544                                         }
4545                                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, cfg->arch.stack_alloc_size);
4546
4547                                 // FIXME:
4548                                 if (call->stack_usage)
4549                                         NOT_IMPLEMENTED;
4550                         }
4551                         else {
4552                                 for (i = 0; i < AMD64_NREG; ++i)
4553                                         if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i)))
4554                                                 pos -= sizeof(mgreg_t);
4555
4556                                 /* Restore callee-saved registers */
4557                                 for (i = AMD64_NREG - 1; i > 0; --i) {
4558                                         if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
4559                                                 amd64_mov_reg_membase (code, i, AMD64_RBP, pos, sizeof(mgreg_t));
4560                                                 pos += sizeof(mgreg_t);
4561                                         }
4562                                 }
4563
4564                                 /* Copy arguments on the stack to our argument area */
4565                                 for (i = 0; i < call->stack_usage; i += sizeof(mgreg_t)) {
4566                                         amd64_mov_reg_membase (code, AMD64_RAX, AMD64_RSP, i, sizeof(mgreg_t));
4567                                         amd64_mov_membase_reg (code, AMD64_RBP, 16 + i, AMD64_RAX, sizeof(mgreg_t));
4568                                 }
4569
4570                                 if (pos)
4571                                         amd64_lea_membase (code, AMD64_RSP, AMD64_RBP, pos);
4572
4573                                 amd64_leave (code);
4574                         }
4575
4576                         offset = code - cfg->native_code;
4577                         mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_METHOD_JUMP, ins->inst_p0);
4578                         if (cfg->compile_aot)
4579                                 amd64_mov_reg_membase (code, AMD64_R11, AMD64_RIP, 0, 8);
4580                         else
4581                                 amd64_set_reg_template (code, AMD64_R11);
4582                         amd64_jump_reg (code, AMD64_R11);
4583                         break;
4584                 }
4585                 case OP_CHECK_THIS:
4586                         /* ensure ins->sreg1 is not NULL */
4587                         amd64_alu_membase_imm_size (code, X86_CMP, ins->sreg1, 0, 0, 4);
4588                         break;
4589                 case OP_ARGLIST: {
4590                         amd64_lea_membase (code, AMD64_R11, cfg->frame_reg, cfg->sig_cookie);
4591                         amd64_mov_membase_reg (code, ins->sreg1, 0, AMD64_R11, sizeof(gpointer));
4592                         break;
4593                 }
4594                 case OP_CALL:
4595                 case OP_FCALL:
4596                 case OP_LCALL:
4597                 case OP_VCALL:
4598                 case OP_VCALL2:
4599                 case OP_VOIDCALL:
4600                         call = (MonoCallInst*)ins;
4601                         /*
4602                          * The AMD64 ABI forces callers to know about varargs.
4603                          */
4604                         if ((call->signature->call_convention == MONO_CALL_VARARG) && (call->signature->pinvoke))
4605                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
4606                         else if ((cfg->method->wrapper_type == MONO_WRAPPER_MANAGED_TO_NATIVE) && (cfg->method->klass->image != mono_defaults.corlib)) {
4607                                 /*
4608                                  * Since the unmanaged calling convention doesn't contain a
4609                                  * 'vararg' entry, we have to treat every pinvoke call as a
4610                                  * potential vararg call.
4611                                  */
4612                                 guint32 nregs, i;
4613                                 nregs = 0;
4614                                 for (i = 0; i < AMD64_XMM_NREG; ++i)
4615                                         if (call->used_fregs & (1 << i))
4616                                                 nregs ++;
4617                                 if (!nregs)
4618                                         amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
4619                                 else
4620                                         amd64_mov_reg_imm (code, AMD64_RAX, nregs);
4621                         }
4622
4623                         if (ins->flags & MONO_INST_HAS_METHOD)
4624                                 code = emit_call (cfg, code, MONO_PATCH_INFO_METHOD, call->method, FALSE);
4625                         else
4626                                 code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, call->fptr, FALSE);
4627                         if (call->stack_usage && !CALLCONV_IS_STDCALL (call->signature->call_convention) && !cfg->arch.no_pushes)
4628                                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, call->stack_usage);
4629                         code = emit_move_return_value (cfg, ins, code);
4630                         break;
4631                 case OP_FCALL_REG:
4632                 case OP_LCALL_REG:
4633                 case OP_VCALL_REG:
4634                 case OP_VCALL2_REG:
4635                 case OP_VOIDCALL_REG:
4636                 case OP_CALL_REG:
4637                         call = (MonoCallInst*)ins;
4638
4639                         if (AMD64_IS_ARGUMENT_REG (ins->sreg1)) {
4640                                 amd64_mov_reg_reg (code, AMD64_R11, ins->sreg1, 8);
4641                                 ins->sreg1 = AMD64_R11;
4642                         }
4643
4644                         /*
4645                          * The AMD64 ABI forces callers to know about varargs.
4646                          */
4647                         if ((call->signature->call_convention == MONO_CALL_VARARG) && (call->signature->pinvoke)) {
4648                                 if (ins->sreg1 == AMD64_RAX) {
4649                                         amd64_mov_reg_reg (code, AMD64_R11, AMD64_RAX, 8);
4650                                         ins->sreg1 = AMD64_R11;
4651                                 }
4652                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
4653                         } else if ((cfg->method->wrapper_type == MONO_WRAPPER_MANAGED_TO_NATIVE) && (cfg->method->klass->image != mono_defaults.corlib)) {
4654                                 /*
4655                                  * Since the unmanaged calling convention doesn't contain a
4656                                  * 'vararg' entry, we have to treat every pinvoke call as a
4657                                  * potential vararg call.
4658                                  */
4659                                 guint32 nregs, i;
4660                                 nregs = 0;
4661                                 for (i = 0; i < AMD64_XMM_NREG; ++i)
4662                                         if (call->used_fregs & (1 << i))
4663                                                 nregs ++;
4664                                 if (ins->sreg1 == AMD64_RAX) {
4665                                         amd64_mov_reg_reg (code, AMD64_R11, AMD64_RAX, 8);
4666                                         ins->sreg1 = AMD64_R11;
4667                                 }
4668                                 if (!nregs)
4669                                         amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
4670                                 else
4671                                         amd64_mov_reg_imm (code, AMD64_RAX, nregs);
4672                         }
4673
4674                         amd64_call_reg (code, ins->sreg1);
4675                         if (call->stack_usage && !CALLCONV_IS_STDCALL (call->signature->call_convention) && !cfg->arch.no_pushes)
4676                                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, call->stack_usage);
4677                         code = emit_move_return_value (cfg, ins, code);
4678                         break;
4679                 case OP_FCALL_MEMBASE:
4680                 case OP_LCALL_MEMBASE:
4681                 case OP_VCALL_MEMBASE:
4682                 case OP_VCALL2_MEMBASE:
4683                 case OP_VOIDCALL_MEMBASE:
4684                 case OP_CALL_MEMBASE:
4685                         call = (MonoCallInst*)ins;
4686
4687                         amd64_call_membase (code, ins->sreg1, ins->inst_offset);
4688                         if (call->stack_usage && !CALLCONV_IS_STDCALL (call->signature->call_convention) && !cfg->arch.no_pushes)
4689                                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, call->stack_usage);
4690                         code = emit_move_return_value (cfg, ins, code);
4691                         break;
4692                 case OP_DYN_CALL: {
4693                         int i;
4694                         MonoInst *var = cfg->dyn_call_var;
4695
4696                         g_assert (var->opcode == OP_REGOFFSET);
4697
4698                         /* r11 = args buffer filled by mono_arch_get_dyn_call_args () */
4699                         amd64_mov_reg_reg (code, AMD64_R11, ins->sreg1, 8);
4700                         /* r10 = ftn */
4701                         amd64_mov_reg_reg (code, AMD64_R10, ins->sreg2, 8);
4702
4703                         /* Save args buffer */
4704                         amd64_mov_membase_reg (code, var->inst_basereg, var->inst_offset, AMD64_R11, 8);
4705
4706                         /* Set argument registers */
4707                         for (i = 0; i < PARAM_REGS; ++i)
4708                                 amd64_mov_reg_membase (code, param_regs [i], AMD64_R11, i * sizeof(mgreg_t), sizeof(mgreg_t));
4709
4710                         /* Make the call */
4711                         amd64_call_reg (code, AMD64_R10);
4712
4713                         /* Save result */
4714                         amd64_mov_reg_membase (code, AMD64_R11, var->inst_basereg, var->inst_offset, 8);
4715                         amd64_mov_membase_reg (code, AMD64_R11, G_STRUCT_OFFSET (DynCallArgs, res), AMD64_RAX, 8);
4716                         break;
4717                 }
4718                 case OP_AMD64_SAVE_SP_TO_LMF:
4719                         amd64_mov_membase_reg (code, cfg->frame_reg, cfg->arch.lmf_offset + G_STRUCT_OFFSET (MonoLMF, rsp), AMD64_RSP, 8);
4720                         break;
4721                 case OP_X86_PUSH:
4722                         g_assert (!cfg->arch.no_pushes);
4723                         amd64_push_reg (code, ins->sreg1);
4724                         break;
4725                 case OP_X86_PUSH_IMM:
4726                         g_assert (!cfg->arch.no_pushes);
4727                         g_assert (amd64_is_imm32 (ins->inst_imm));
4728                         amd64_push_imm (code, ins->inst_imm);
4729                         break;
4730                 case OP_X86_PUSH_MEMBASE:
4731                         g_assert (!cfg->arch.no_pushes);
4732                         amd64_push_membase (code, ins->inst_basereg, ins->inst_offset);
4733                         break;
4734                 case OP_X86_PUSH_OBJ: {
4735                         int size = ALIGN_TO (ins->inst_imm, 8);
4736
4737                         g_assert (!cfg->arch.no_pushes);
4738
4739                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, size);
4740                         amd64_push_reg (code, AMD64_RDI);
4741                         amd64_push_reg (code, AMD64_RSI);
4742                         amd64_push_reg (code, AMD64_RCX);
4743                         if (ins->inst_offset)
4744                                 amd64_lea_membase (code, AMD64_RSI, ins->inst_basereg, ins->inst_offset);
4745                         else
4746                                 amd64_mov_reg_reg (code, AMD64_RSI, ins->inst_basereg, 8);
4747                         amd64_lea_membase (code, AMD64_RDI, AMD64_RSP, (3 * 8));
4748                         amd64_mov_reg_imm (code, AMD64_RCX, (size >> 3));
4749                         amd64_cld (code);
4750                         amd64_prefix (code, X86_REP_PREFIX);
4751                         amd64_movsd (code);
4752                         amd64_pop_reg (code, AMD64_RCX);
4753                         amd64_pop_reg (code, AMD64_RSI);
4754                         amd64_pop_reg (code, AMD64_RDI);
4755                         break;
4756                 }
4757                 case OP_X86_LEA:
4758                         amd64_lea_memindex (code, ins->dreg, ins->sreg1, ins->inst_imm, ins->sreg2, ins->backend.shift_amount);
4759                         break;
4760                 case OP_X86_LEA_MEMBASE:
4761                         amd64_lea_membase (code, ins->dreg, ins->sreg1, ins->inst_imm);
4762                         break;
4763                 case OP_X86_XCHG:
4764                         amd64_xchg_reg_reg (code, ins->sreg1, ins->sreg2, 4);
4765                         break;
4766                 case OP_LOCALLOC:
4767                         /* keep alignment */
4768                         amd64_alu_reg_imm (code, X86_ADD, ins->sreg1, MONO_ARCH_FRAME_ALIGNMENT - 1);
4769                         amd64_alu_reg_imm (code, X86_AND, ins->sreg1, ~(MONO_ARCH_FRAME_ALIGNMENT - 1));
4770                         code = mono_emit_stack_alloc (cfg, code, ins);
4771                         amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
4772                         if (cfg->param_area && cfg->arch.no_pushes)
4773                                 amd64_alu_reg_imm (code, X86_ADD, ins->dreg, cfg->param_area);
4774                         break;
4775                 case OP_LOCALLOC_IMM: {
4776                         guint32 size = ins->inst_imm;
4777                         size = (size + (MONO_ARCH_FRAME_ALIGNMENT - 1)) & ~ (MONO_ARCH_FRAME_ALIGNMENT - 1);
4778
4779                         if (ins->flags & MONO_INST_INIT) {
4780                                 if (size < 64) {
4781                                         int i;
4782
4783                                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, size);
4784                                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
4785
4786                                         for (i = 0; i < size; i += 8)
4787                                                 amd64_mov_membase_reg (code, AMD64_RSP, i, ins->dreg, 8);
4788                                         amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
4789                                 } else {
4790                                         amd64_mov_reg_imm (code, ins->dreg, size);
4791                                         ins->sreg1 = ins->dreg;
4792
4793                                         code = mono_emit_stack_alloc (cfg, code, ins);
4794                                         amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
4795                                 }
4796                         } else {
4797                                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, size);
4798                                 amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
4799                         }
4800                         if (cfg->param_area && cfg->arch.no_pushes)
4801                                 amd64_alu_reg_imm (code, X86_ADD, ins->dreg, cfg->param_area);
4802                         break;
4803                 }
4804                 case OP_THROW: {
4805                         amd64_mov_reg_reg (code, AMD64_ARG_REG1, ins->sreg1, 8);
4806                         code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
4807                                              (gpointer)"mono_arch_throw_exception", FALSE);
4808                         break;
4809                 }
4810                 case OP_RETHROW: {
4811                         amd64_mov_reg_reg (code, AMD64_ARG_REG1, ins->sreg1, 8);
4812                         code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
4813                                              (gpointer)"mono_arch_rethrow_exception", FALSE);
4814                         break;
4815                 }
4816                 case OP_CALL_HANDLER:
4817                         /* Align stack */
4818                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
4819                         mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_target_bb);
4820                         amd64_call_imm (code, 0);
4821                         mono_cfg_add_try_hole (cfg, ins->inst_eh_block, code, bb);
4822                         /* Restore stack alignment */
4823                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
4824                         break;
4825                 case OP_START_HANDLER: {
4826                         /* Even though we're saving RSP, use sizeof */
4827                         /* gpointer because spvar is of type IntPtr */
4828                         /* see: mono_create_spvar_for_region */
4829                         MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
4830                         amd64_mov_membase_reg (code, spvar->inst_basereg, spvar->inst_offset, AMD64_RSP, sizeof(gpointer));
4831
4832                         if ((MONO_BBLOCK_IS_IN_REGION (bb, MONO_REGION_FINALLY) ||
4833                                  MONO_BBLOCK_IS_IN_REGION (bb, MONO_REGION_FINALLY)) &&
4834                                 cfg->param_area && cfg->arch.no_pushes) {
4835                                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, ALIGN_TO (cfg->param_area, MONO_ARCH_FRAME_ALIGNMENT));
4836                         }
4837                         break;
4838                 }
4839                 case OP_ENDFINALLY: {
4840                         MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
4841                         amd64_mov_reg_membase (code, AMD64_RSP, spvar->inst_basereg, spvar->inst_offset, sizeof(gpointer));
4842                         amd64_ret (code);
4843                         break;
4844                 }
4845                 case OP_ENDFILTER: {
4846                         MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
4847                         amd64_mov_reg_membase (code, AMD64_RSP, spvar->inst_basereg, spvar->inst_offset, sizeof(gpointer));
4848                         /* The local allocator will put the result into RAX */
4849                         amd64_ret (code);
4850                         break;
4851                 }
4852
4853                 case OP_LABEL:
4854                         ins->inst_c0 = code - cfg->native_code;
4855                         break;
4856                 case OP_BR:
4857                         //g_print ("target: %p, next: %p, curr: %p, last: %p\n", ins->inst_target_bb, bb->next_bb, ins, bb->last_ins);
4858                         //if ((ins->inst_target_bb == bb->next_bb) && ins == bb->last_ins)
4859                         //break;
4860                                 if (ins->inst_target_bb->native_offset) {
4861                                         amd64_jump_code (code, cfg->native_code + ins->inst_target_bb->native_offset);
4862                                 } else {
4863                                         mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_BB, ins->inst_target_bb);
4864                                         if ((cfg->opt & MONO_OPT_BRANCH) &&
4865                                             x86_is_imm8 (ins->inst_target_bb->max_offset - offset))
4866                                                 x86_jump8 (code, 0);
4867                                         else
4868                                                 x86_jump32 (code, 0);
4869                         }
4870                         break;
4871                 case OP_BR_REG:
4872                         amd64_jump_reg (code, ins->sreg1);
4873                         break;
4874                 case OP_CEQ:
4875                 case OP_LCEQ:
4876                 case OP_ICEQ:
4877                 case OP_CLT:
4878                 case OP_LCLT:
4879                 case OP_ICLT:
4880                 case OP_CGT:
4881                 case OP_ICGT:
4882                 case OP_LCGT:
4883                 case OP_CLT_UN:
4884                 case OP_LCLT_UN:
4885                 case OP_ICLT_UN:
4886                 case OP_CGT_UN:
4887                 case OP_LCGT_UN:
4888                 case OP_ICGT_UN:
4889                         amd64_set_reg (code, cc_table [mono_opcode_to_cond (ins->opcode)], ins->dreg, cc_signed_table [mono_opcode_to_cond (ins->opcode)]);
4890                         amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
4891                         break;
4892                 case OP_COND_EXC_EQ:
4893                 case OP_COND_EXC_NE_UN:
4894                 case OP_COND_EXC_LT:
4895                 case OP_COND_EXC_LT_UN:
4896                 case OP_COND_EXC_GT:
4897                 case OP_COND_EXC_GT_UN:
4898                 case OP_COND_EXC_GE:
4899                 case OP_COND_EXC_GE_UN:
4900                 case OP_COND_EXC_LE:
4901                 case OP_COND_EXC_LE_UN:
4902                 case OP_COND_EXC_IEQ:
4903                 case OP_COND_EXC_INE_UN:
4904                 case OP_COND_EXC_ILT:
4905                 case OP_COND_EXC_ILT_UN:
4906                 case OP_COND_EXC_IGT:
4907                 case OP_COND_EXC_IGT_UN:
4908                 case OP_COND_EXC_IGE:
4909                 case OP_COND_EXC_IGE_UN:
4910                 case OP_COND_EXC_ILE:
4911                 case OP_COND_EXC_ILE_UN:
4912                         EMIT_COND_SYSTEM_EXCEPTION (cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)], ins->inst_p1);
4913                         break;
4914                 case OP_COND_EXC_OV:
4915                 case OP_COND_EXC_NO:
4916                 case OP_COND_EXC_C:
4917                 case OP_COND_EXC_NC:
4918                         EMIT_COND_SYSTEM_EXCEPTION (branch_cc_table [ins->opcode - OP_COND_EXC_EQ],
4919                                                     (ins->opcode < OP_COND_EXC_NE_UN), ins->inst_p1);
4920                         break;
4921                 case OP_COND_EXC_IOV:
4922                 case OP_COND_EXC_INO:
4923                 case OP_COND_EXC_IC:
4924                 case OP_COND_EXC_INC:
4925                         EMIT_COND_SYSTEM_EXCEPTION (branch_cc_table [ins->opcode - OP_COND_EXC_IEQ],
4926                                                     (ins->opcode < OP_COND_EXC_INE_UN), ins->inst_p1);
4927                         break;
4928
4929                 /* floating point opcodes */
4930                 case OP_R8CONST: {
4931                         double d = *(double *)ins->inst_p0;
4932
4933                         if ((d == 0.0) && (mono_signbit (d) == 0)) {
4934                                 amd64_sse_xorpd_reg_reg (code, ins->dreg, ins->dreg);
4935                         }
4936                         else {
4937                                 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R8, ins->inst_p0);
4938                                 amd64_sse_movsd_reg_membase (code, ins->dreg, AMD64_RIP, 0);
4939                         }
4940                         break;
4941                 }
4942                 case OP_R4CONST: {
4943                         float f = *(float *)ins->inst_p0;
4944
4945                         if ((f == 0.0) && (mono_signbit (f) == 0)) {
4946                                 amd64_sse_xorpd_reg_reg (code, ins->dreg, ins->dreg);
4947                         }
4948                         else {
4949                                 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R4, ins->inst_p0);
4950                                 amd64_sse_movss_reg_membase (code, ins->dreg, AMD64_RIP, 0);
4951                                 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
4952                         }
4953                         break;
4954                 }
4955                 case OP_STORER8_MEMBASE_REG:
4956                         amd64_sse_movsd_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1);
4957                         break;
4958                 case OP_LOADR8_MEMBASE:
4959                         amd64_sse_movsd_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
4960                         break;
4961                 case OP_STORER4_MEMBASE_REG:
4962                         /* This requires a double->single conversion */
4963                         amd64_sse_cvtsd2ss_reg_reg (code, AMD64_XMM15, ins->sreg1);
4964                         amd64_sse_movss_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, AMD64_XMM15);
4965                         break;
4966                 case OP_LOADR4_MEMBASE:
4967                         amd64_sse_movss_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
4968                         amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
4969                         break;
4970                 case OP_ICONV_TO_R4: /* FIXME: change precision */
4971                 case OP_ICONV_TO_R8:
4972                         amd64_sse_cvtsi2sd_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
4973                         break;
4974                 case OP_LCONV_TO_R4: /* FIXME: change precision */
4975                 case OP_LCONV_TO_R8:
4976                         amd64_sse_cvtsi2sd_reg_reg (code, ins->dreg, ins->sreg1);
4977                         break;
4978                 case OP_FCONV_TO_R4:
4979                         /* FIXME: nothing to do ?? */
4980                         break;
4981                 case OP_FCONV_TO_I1:
4982                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 1, TRUE);
4983                         break;
4984                 case OP_FCONV_TO_U1:
4985                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 1, FALSE);
4986                         break;
4987                 case OP_FCONV_TO_I2:
4988                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 2, TRUE);
4989                         break;
4990                 case OP_FCONV_TO_U2:
4991                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 2, FALSE);
4992                         break;
4993                 case OP_FCONV_TO_U4:
4994                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 4, FALSE);
4995                         break;
4996                 case OP_FCONV_TO_I4:
4997                 case OP_FCONV_TO_I:
4998                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 4, TRUE);
4999                         break;
5000                 case OP_FCONV_TO_I8:
5001                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 8, TRUE);
5002                         break;
5003                 case OP_LCONV_TO_R_UN: {
5004                         guint8 *br [2];
5005
5006                         /* Based on gcc code */
5007                         amd64_test_reg_reg (code, ins->sreg1, ins->sreg1);
5008                         br [0] = code; x86_branch8 (code, X86_CC_S, 0, TRUE);
5009
5010                         /* Positive case */
5011                         amd64_sse_cvtsi2sd_reg_reg (code, ins->dreg, ins->sreg1);
5012                         br [1] = code; x86_jump8 (code, 0);
5013                         amd64_patch (br [0], code);
5014
5015                         /* Negative case */
5016                         /* Save to the red zone */
5017                         amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RAX, 8);
5018                         amd64_mov_membase_reg (code, AMD64_RSP, -16, AMD64_RCX, 8);
5019                         amd64_mov_reg_reg (code, AMD64_RCX, ins->sreg1, 8);
5020                         amd64_mov_reg_reg (code, AMD64_RAX, ins->sreg1, 8);
5021                         amd64_alu_reg_imm (code, X86_AND, AMD64_RCX, 1);
5022                         amd64_shift_reg_imm (code, X86_SHR, AMD64_RAX, 1);
5023                         amd64_alu_reg_imm (code, X86_OR, AMD64_RAX, AMD64_RCX);
5024                         amd64_sse_cvtsi2sd_reg_reg (code, ins->dreg, AMD64_RAX);
5025                         amd64_sse_addsd_reg_reg (code, ins->dreg, ins->dreg);
5026                         /* Restore */
5027                         amd64_mov_reg_membase (code, AMD64_RCX, AMD64_RSP, -16, 8);
5028                         amd64_mov_reg_membase (code, AMD64_RAX, AMD64_RSP, -8, 8);
5029                         amd64_patch (br [1], code);
5030                         break;
5031                 }
5032                 case OP_LCONV_TO_OVF_U4:
5033                         amd64_alu_reg_imm (code, X86_CMP, ins->sreg1, 0);
5034                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_LT, TRUE, "OverflowException");
5035                         amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, 8);
5036                         break;
5037                 case OP_LCONV_TO_OVF_I4_UN:
5038                         amd64_alu_reg_imm (code, X86_CMP, ins->sreg1, 0x7fffffff);
5039                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_GT, FALSE, "OverflowException");
5040                         amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, 8);
5041                         break;
5042                 case OP_FMOVE:
5043                         if (ins->dreg != ins->sreg1)
5044                                 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
5045                         break;
5046                 case OP_FADD:
5047                         amd64_sse_addsd_reg_reg (code, ins->dreg, ins->sreg2);
5048                         break;
5049                 case OP_FSUB:
5050                         amd64_sse_subsd_reg_reg (code, ins->dreg, ins->sreg2);
5051                         break;
5052                 case OP_FMUL:
5053                         amd64_sse_mulsd_reg_reg (code, ins->dreg, ins->sreg2);
5054                         break;
5055                 case OP_FDIV:
5056                         amd64_sse_divsd_reg_reg (code, ins->dreg, ins->sreg2);
5057                         break;
5058                 case OP_FNEG: {
5059                         static double r8_0 = -0.0;
5060
5061                         g_assert (ins->sreg1 == ins->dreg);
5062
5063                         mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R8, &r8_0);
5064                         amd64_sse_xorpd_reg_membase (code, ins->dreg, AMD64_RIP, 0);
5065                         break;
5066                 }
5067                 case OP_SIN:
5068                         EMIT_SSE2_FPFUNC (code, fsin, ins->dreg, ins->sreg1);
5069                         break;
5070                 case OP_COS:
5071                         EMIT_SSE2_FPFUNC (code, fcos, ins->dreg, ins->sreg1);
5072                         break;
5073                 case OP_ABS: {
5074                         static guint64 d = 0x7fffffffffffffffUL;
5075
5076                         g_assert (ins->sreg1 == ins->dreg);
5077
5078                         mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R8, &d);
5079                         amd64_sse_andpd_reg_membase (code, ins->dreg, AMD64_RIP, 0);
5080                         break;
5081                 }
5082                 case OP_SQRT:
5083                         EMIT_SSE2_FPFUNC (code, fsqrt, ins->dreg, ins->sreg1);
5084                         break;
5085                 case OP_IMIN:
5086                         g_assert (cfg->opt & MONO_OPT_CMOV);
5087                         g_assert (ins->dreg == ins->sreg1);
5088                         amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
5089                         amd64_cmov_reg_size (code, X86_CC_GT, TRUE, ins->dreg, ins->sreg2, 4);
5090                         break;
5091                 case OP_IMIN_UN:
5092                         g_assert (cfg->opt & MONO_OPT_CMOV);
5093                         g_assert (ins->dreg == ins->sreg1);
5094                         amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
5095                         amd64_cmov_reg_size (code, X86_CC_GT, FALSE, ins->dreg, ins->sreg2, 4);
5096                         break;
5097                 case OP_IMAX:
5098                         g_assert (cfg->opt & MONO_OPT_CMOV);
5099                         g_assert (ins->dreg == ins->sreg1);
5100                         amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
5101                         amd64_cmov_reg_size (code, X86_CC_LT, TRUE, ins->dreg, ins->sreg2, 4);
5102                         break;
5103                 case OP_IMAX_UN:
5104                         g_assert (cfg->opt & MONO_OPT_CMOV);
5105                         g_assert (ins->dreg == ins->sreg1);
5106                         amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
5107                         amd64_cmov_reg_size (code, X86_CC_LT, FALSE, ins->dreg, ins->sreg2, 4);
5108                         break;
5109                 case OP_LMIN:
5110                         g_assert (cfg->opt & MONO_OPT_CMOV);
5111                         g_assert (ins->dreg == ins->sreg1);
5112                         amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
5113                         amd64_cmov_reg (code, X86_CC_GT, TRUE, ins->dreg, ins->sreg2);
5114                         break;
5115                 case OP_LMIN_UN:
5116                         g_assert (cfg->opt & MONO_OPT_CMOV);
5117                         g_assert (ins->dreg == ins->sreg1);
5118                         amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
5119                         amd64_cmov_reg (code, X86_CC_GT, FALSE, ins->dreg, ins->sreg2);
5120                         break;
5121                 case OP_LMAX:
5122                         g_assert (cfg->opt & MONO_OPT_CMOV);
5123                         g_assert (ins->dreg == ins->sreg1);
5124                         amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
5125                         amd64_cmov_reg (code, X86_CC_LT, TRUE, ins->dreg, ins->sreg2);
5126                         break;
5127                 case OP_LMAX_UN:
5128                         g_assert (cfg->opt & MONO_OPT_CMOV);
5129                         g_assert (ins->dreg == ins->sreg1);
5130                         amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
5131                         amd64_cmov_reg (code, X86_CC_LT, FALSE, ins->dreg, ins->sreg2);
5132                         break;
5133                 case OP_X86_FPOP:
5134                         break;
5135                 case OP_FCOMPARE:
5136                         /*
5137                          * The two arguments are swapped because the fbranch instructions
5138                          * depend on this for the non-sse case to work.
5139                          */
5140                         amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
5141                         break;
5142                 case OP_FCEQ: {
5143                         /* zeroing the register at the start results in
5144                          * shorter and faster code (we can also remove the widening op)
5145                          */
5146                         guchar *unordered_check;
5147                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5148                         amd64_sse_comisd_reg_reg (code, ins->sreg1, ins->sreg2);
5149                         unordered_check = code;
5150                         x86_branch8 (code, X86_CC_P, 0, FALSE);
5151                         amd64_set_reg (code, X86_CC_EQ, ins->dreg, FALSE);
5152                         amd64_patch (unordered_check, code);
5153                         break;
5154                 }
5155                 case OP_FCLT:
5156                 case OP_FCLT_UN:
5157                         /* zeroing the register at the start results in
5158                          * shorter and faster code (we can also remove the widening op)
5159                          */
5160                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5161                         amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
5162                         if (ins->opcode == OP_FCLT_UN) {
5163                                 guchar *unordered_check = code;
5164                                 guchar *jump_to_end;
5165                                 x86_branch8 (code, X86_CC_P, 0, FALSE);
5166                                 amd64_set_reg (code, X86_CC_GT, ins->dreg, FALSE);
5167                                 jump_to_end = code;
5168                                 x86_jump8 (code, 0);
5169                                 amd64_patch (unordered_check, code);
5170                                 amd64_inc_reg (code, ins->dreg);
5171                                 amd64_patch (jump_to_end, code);
5172                         } else {
5173                                 amd64_set_reg (code, X86_CC_GT, ins->dreg, FALSE);
5174                         }
5175                         break;
5176                 case OP_FCGT:
5177                 case OP_FCGT_UN: {
5178                         /* zeroing the register at the start results in
5179                          * shorter and faster code (we can also remove the widening op)
5180                          */
5181                         guchar *unordered_check;
5182                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5183                         amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
5184                         if (ins->opcode == OP_FCGT) {
5185                                 unordered_check = code;
5186                                 x86_branch8 (code, X86_CC_P, 0, FALSE);
5187                                 amd64_set_reg (code, X86_CC_LT, ins->dreg, FALSE);
5188                                 amd64_patch (unordered_check, code);
5189                         } else {
5190                                 amd64_set_reg (code, X86_CC_LT, ins->dreg, FALSE);
5191                         }
5192                         break;
5193                 }
5194                 case OP_FCLT_MEMBASE:
5195                 case OP_FCGT_MEMBASE:
5196                 case OP_FCLT_UN_MEMBASE:
5197                 case OP_FCGT_UN_MEMBASE:
5198                 case OP_FCEQ_MEMBASE: {
5199                         guchar *unordered_check, *jump_to_end;
5200                         int x86_cond;
5201
5202                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5203                         amd64_sse_comisd_reg_membase (code, ins->sreg1, ins->sreg2, ins->inst_offset);
5204
5205                         switch (ins->opcode) {
5206                         case OP_FCEQ_MEMBASE:
5207                                 x86_cond = X86_CC_EQ;
5208                                 break;
5209                         case OP_FCLT_MEMBASE:
5210                         case OP_FCLT_UN_MEMBASE:
5211                                 x86_cond = X86_CC_LT;
5212                                 break;
5213                         case OP_FCGT_MEMBASE:
5214                         case OP_FCGT_UN_MEMBASE:
5215                                 x86_cond = X86_CC_GT;
5216                                 break;
5217                         default:
5218                                 g_assert_not_reached ();
5219                         }
5220
5221                         unordered_check = code;
5222                         x86_branch8 (code, X86_CC_P, 0, FALSE);
5223                         amd64_set_reg (code, x86_cond, ins->dreg, FALSE);
5224
5225                         switch (ins->opcode) {
5226                         case OP_FCEQ_MEMBASE:
5227                         case OP_FCLT_MEMBASE:
5228                         case OP_FCGT_MEMBASE:
5229                                 amd64_patch (unordered_check, code);
5230                                 break;
5231                         case OP_FCLT_UN_MEMBASE:
5232                         case OP_FCGT_UN_MEMBASE:
5233                                 jump_to_end = code;
5234                                 x86_jump8 (code, 0);
5235                                 amd64_patch (unordered_check, code);
5236                                 amd64_inc_reg (code, ins->dreg);
5237                                 amd64_patch (jump_to_end, code);
5238                                 break;
5239                         default:
5240                                 break;
5241                         }
5242                         break;
5243                 }
5244                 case OP_FBEQ: {
5245                         guchar *jump = code;
5246                         x86_branch8 (code, X86_CC_P, 0, TRUE);
5247                         EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
5248                         amd64_patch (jump, code);
5249                         break;
5250                 }
5251                 case OP_FBNE_UN:
5252                         /* Branch if C013 != 100 */
5253                         /* branch if !ZF or (PF|CF) */
5254                         EMIT_COND_BRANCH (ins, X86_CC_NE, FALSE);
5255                         EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
5256                         EMIT_COND_BRANCH (ins, X86_CC_B, FALSE);
5257                         break;
5258                 case OP_FBLT:
5259                         EMIT_COND_BRANCH (ins, X86_CC_GT, FALSE);
5260                         break;
5261                 case OP_FBLT_UN:
5262                         EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
5263                         EMIT_COND_BRANCH (ins, X86_CC_GT, FALSE);
5264                         break;
5265                 case OP_FBGT:
5266                 case OP_FBGT_UN:
5267                         if (ins->opcode == OP_FBGT) {
5268                                 guchar *br1;
5269
5270                                 /* skip branch if C1=1 */
5271                                 br1 = code;
5272                                 x86_branch8 (code, X86_CC_P, 0, FALSE);
5273                                 /* branch if (C0 | C3) = 1 */
5274                                 EMIT_COND_BRANCH (ins, X86_CC_LT, FALSE);
5275                                 amd64_patch (br1, code);
5276                                 break;
5277                         } else {
5278                                 EMIT_COND_BRANCH (ins, X86_CC_LT, FALSE);
5279                         }
5280                         break;
5281                 case OP_FBGE: {
5282                         /* Branch if C013 == 100 or 001 */
5283                         guchar *br1;
5284
5285                         /* skip branch if C1=1 */
5286                         br1 = code;
5287                         x86_branch8 (code, X86_CC_P, 0, FALSE);
5288                         /* branch if (C0 | C3) = 1 */
5289                         EMIT_COND_BRANCH (ins, X86_CC_BE, FALSE);
5290                         amd64_patch (br1, code);
5291                         break;
5292                 }
5293                 case OP_FBGE_UN:
5294                         /* Branch if C013 == 000 */
5295                         EMIT_COND_BRANCH (ins, X86_CC_LE, FALSE);
5296                         break;
5297                 case OP_FBLE: {
5298                         /* Branch if C013=000 or 100 */
5299                         guchar *br1;
5300
5301                         /* skip branch if C1=1 */
5302                         br1 = code;
5303                         x86_branch8 (code, X86_CC_P, 0, FALSE);
5304                         /* branch if C0=0 */
5305                         EMIT_COND_BRANCH (ins, X86_CC_NB, FALSE);
5306                         amd64_patch (br1, code);
5307                         break;
5308                 }
5309                 case OP_FBLE_UN:
5310                         /* Branch if C013 != 001 */
5311                         EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
5312                         EMIT_COND_BRANCH (ins, X86_CC_GE, FALSE);
5313                         break;
5314                 case OP_CKFINITE:
5315                         /* Transfer value to the fp stack */
5316                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 16);
5317                         amd64_movsd_membase_reg (code, AMD64_RSP, 0, ins->sreg1);
5318                         amd64_fld_membase (code, AMD64_RSP, 0, TRUE);
5319
5320                         amd64_push_reg (code, AMD64_RAX);
5321                         amd64_fxam (code);
5322                         amd64_fnstsw (code);
5323                         amd64_alu_reg_imm (code, X86_AND, AMD64_RAX, 0x4100);
5324                         amd64_alu_reg_imm (code, X86_CMP, AMD64_RAX, X86_FP_C0);
5325                         amd64_pop_reg (code, AMD64_RAX);
5326                         amd64_fstp (code, 0);
5327                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ, FALSE, "ArithmeticException");
5328                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 16);
5329                         break;
5330                 case OP_TLS_GET: {
5331                         code = mono_amd64_emit_tls_get (code, ins->dreg, ins->inst_offset);
5332                         break;
5333                 }
5334                 case OP_MEMORY_BARRIER: {
5335                         /* http://blogs.sun.com/dave/resource/NHM-Pipeline-Blog-V2.txt */
5336                         x86_prefix (code, X86_LOCK_PREFIX);
5337                         amd64_alu_membase_imm (code, X86_ADD, AMD64_RSP, 0, 0);
5338                         break;
5339                 }
5340                 case OP_ATOMIC_ADD_I4:
5341                 case OP_ATOMIC_ADD_I8: {
5342                         int dreg = ins->dreg;
5343                         guint32 size = (ins->opcode == OP_ATOMIC_ADD_I4) ? 4 : 8;
5344
5345                         if (dreg == ins->inst_basereg)
5346                                 dreg = AMD64_R11;
5347
5348                         if (dreg != ins->sreg2)
5349                                 amd64_mov_reg_reg (code, ins->dreg, ins->sreg2, size);
5350
5351                         x86_prefix (code, X86_LOCK_PREFIX);
5352                         amd64_xadd_membase_reg (code, ins->inst_basereg, ins->inst_offset, dreg, size);
5353
5354                         if (dreg != ins->dreg)
5355                                 amd64_mov_reg_reg (code, ins->dreg, dreg, size);
5356
5357                         break;
5358                 }
5359                 case OP_ATOMIC_ADD_NEW_I4:
5360                 case OP_ATOMIC_ADD_NEW_I8: {
5361                         int dreg = ins->dreg;
5362                         guint32 size = (ins->opcode == OP_ATOMIC_ADD_NEW_I4) ? 4 : 8;
5363
5364                         if ((dreg == ins->sreg2) || (dreg == ins->inst_basereg))
5365                                 dreg = AMD64_R11;
5366
5367                         amd64_mov_reg_reg (code, dreg, ins->sreg2, size);
5368                         amd64_prefix (code, X86_LOCK_PREFIX);
5369                         amd64_xadd_membase_reg (code, ins->inst_basereg, ins->inst_offset, dreg, size);
5370                         /* dreg contains the old value, add with sreg2 value */
5371                         amd64_alu_reg_reg_size (code, X86_ADD, dreg, ins->sreg2, size);
5372
5373                         if (ins->dreg != dreg)
5374                                 amd64_mov_reg_reg (code, ins->dreg, dreg, size);
5375
5376                         break;
5377                 }
5378                 case OP_ATOMIC_EXCHANGE_I4:
5379                 case OP_ATOMIC_EXCHANGE_I8: {
5380                         guchar *br[2];
5381                         int sreg2 = ins->sreg2;
5382                         int breg = ins->inst_basereg;
5383                         guint32 size;
5384                         gboolean need_push = FALSE, rdx_pushed = FALSE;
5385
5386                         if (ins->opcode == OP_ATOMIC_EXCHANGE_I8)
5387                                 size = 8;
5388                         else
5389                                 size = 4;
5390
5391                         /*
5392                          * See http://msdn.microsoft.com/en-us/magazine/cc302329.aspx for
5393                          * an explanation of how this works.
5394                          */
5395
5396                         /* cmpxchg uses eax as comperand, need to make sure we can use it
5397                          * hack to overcome limits in x86 reg allocator
5398                          * (req: dreg == eax and sreg2 != eax and breg != eax)
5399                          */
5400                         g_assert (ins->dreg == AMD64_RAX);
5401
5402                         if (breg == AMD64_RAX && ins->sreg2 == AMD64_RAX)
5403                                 /* Highly unlikely, but possible */
5404                                 need_push = TRUE;
5405
5406                         /* The pushes invalidate rsp */
5407                         if ((breg == AMD64_RAX) || need_push) {
5408                                 amd64_mov_reg_reg (code, AMD64_R11, breg, 8);
5409                                 breg = AMD64_R11;
5410                         }
5411
5412                         /* We need the EAX reg for the comparand */
5413                         if (ins->sreg2 == AMD64_RAX) {
5414                                 if (breg != AMD64_R11) {
5415                                         amd64_mov_reg_reg (code, AMD64_R11, AMD64_RAX, 8);
5416                                         sreg2 = AMD64_R11;
5417                                 } else {
5418                                         g_assert (need_push);
5419                                         amd64_push_reg (code, AMD64_RDX);
5420                                         amd64_mov_reg_reg (code, AMD64_RDX, AMD64_RAX, size);
5421                                         sreg2 = AMD64_RDX;
5422                                         rdx_pushed = TRUE;
5423                                 }
5424                         }
5425
5426                         amd64_mov_reg_membase (code, AMD64_RAX, breg, ins->inst_offset, size);
5427
5428                         br [0] = code; amd64_prefix (code, X86_LOCK_PREFIX);
5429                         amd64_cmpxchg_membase_reg_size (code, breg, ins->inst_offset, sreg2, size);
5430                         br [1] = code; amd64_branch8 (code, X86_CC_NE, -1, FALSE);
5431                         amd64_patch (br [1], br [0]);
5432
5433                         if (rdx_pushed)
5434                                 amd64_pop_reg (code, AMD64_RDX);
5435
5436                         break;
5437                 }
5438                 case OP_ATOMIC_CAS_I4:
5439                 case OP_ATOMIC_CAS_I8: {
5440                         guint32 size;
5441
5442                         if (ins->opcode == OP_ATOMIC_CAS_I8)
5443                                 size = 8;
5444                         else
5445                                 size = 4;
5446
5447                         /*
5448                          * See http://msdn.microsoft.com/en-us/magazine/cc302329.aspx for
5449                          * an explanation of how this works.
5450                          */
5451                         g_assert (ins->sreg3 == AMD64_RAX);
5452                         g_assert (ins->sreg1 != AMD64_RAX);
5453                         g_assert (ins->sreg1 != ins->sreg2);
5454
5455                         amd64_prefix (code, X86_LOCK_PREFIX);
5456                         amd64_cmpxchg_membase_reg_size (code, ins->sreg1, ins->inst_offset, ins->sreg2, size);
5457
5458                         if (ins->dreg != AMD64_RAX)
5459                                 amd64_mov_reg_reg (code, ins->dreg, AMD64_RAX, size);
5460                         break;
5461                 }
5462                 case OP_CARD_TABLE_WBARRIER: {
5463                         int ptr = ins->sreg1;
5464                         int value = ins->sreg2;
5465                         guchar *br;
5466                         int nursery_shift, card_table_shift;
5467                         gpointer card_table_mask;
5468                         size_t nursery_size;
5469
5470                         gpointer card_table = mono_gc_get_card_table (&card_table_shift, &card_table_mask);
5471                         guint64 nursery_start = (guint64)mono_gc_get_nursery (&nursery_shift, &nursery_size);
5472
5473                         /*If either point to the stack we can simply avoid the WB. This happens due to
5474                          * optimizations revealing a stack store that was not visible when op_cardtable was emited.
5475                          */
5476                         if (ins->sreg1 == AMD64_RSP || ins->sreg2 == AMD64_RSP)
5477                                 continue;
5478
5479                         /*
5480                          * We need one register we can clobber, we choose EDX and make sreg1
5481                          * fixed EAX to work around limitations in the local register allocator.
5482                          * sreg2 might get allocated to EDX, but that is not a problem since
5483                          * we use it before clobbering EDX.
5484                          */
5485                         g_assert (ins->sreg1 == AMD64_RAX);
5486
5487                         /*
5488                          * This is the code we produce:
5489                          *
5490                          *   edx = value
5491                          *   edx >>= nursery_shift
5492                          *   cmp edx, (nursery_start >> nursery_shift)
5493                          *   jne done
5494                          *   edx = ptr
5495                          *   edx >>= card_table_shift
5496                          *   edx += cardtable
5497                          *   [edx] = 1
5498                          * done:
5499                          */
5500
5501                         if (value != AMD64_RDX)
5502                                 amd64_mov_reg_reg (code, AMD64_RDX, value, 8);
5503                         amd64_shift_reg_imm (code, X86_SHR, AMD64_RDX, nursery_shift);
5504                         amd64_alu_reg_imm (code, X86_CMP, AMD64_RDX, nursery_start >> nursery_shift);
5505                         br = code; x86_branch8 (code, X86_CC_NE, -1, FALSE);
5506                         amd64_mov_reg_reg (code, AMD64_RDX, ptr, 8);
5507                         amd64_shift_reg_imm (code, X86_SHR, AMD64_RDX, card_table_shift);
5508                         if (card_table_mask)
5509                                 amd64_alu_reg_imm (code, X86_AND, AMD64_RDX, (guint32)(guint64)card_table_mask);
5510
5511                         mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_GC_CARD_TABLE_ADDR, card_table);
5512                         amd64_alu_reg_membase (code, X86_ADD, AMD64_RDX, AMD64_RIP, 0);
5513
5514                         amd64_mov_membase_imm (code, AMD64_RDX, 0, 1, 1);
5515                         x86_patch (br, code);
5516                         break;
5517                 }
5518 #ifdef MONO_ARCH_SIMD_INTRINSICS
5519                 /* TODO: Some of these IR opcodes are marked as no clobber when they indeed do. */
5520                 case OP_ADDPS:
5521                         amd64_sse_addps_reg_reg (code, ins->sreg1, ins->sreg2);
5522                         break;
5523                 case OP_DIVPS:
5524                         amd64_sse_divps_reg_reg (code, ins->sreg1, ins->sreg2);
5525                         break;
5526                 case OP_MULPS:
5527                         amd64_sse_mulps_reg_reg (code, ins->sreg1, ins->sreg2);
5528                         break;
5529                 case OP_SUBPS:
5530                         amd64_sse_subps_reg_reg (code, ins->sreg1, ins->sreg2);
5531                         break;
5532                 case OP_MAXPS:
5533                         amd64_sse_maxps_reg_reg (code, ins->sreg1, ins->sreg2);
5534                         break;
5535                 case OP_MINPS:
5536                         amd64_sse_minps_reg_reg (code, ins->sreg1, ins->sreg2);
5537                         break;
5538                 case OP_COMPPS:
5539                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 7);
5540                         amd64_sse_cmpps_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
5541                         break;
5542                 case OP_ANDPS:
5543                         amd64_sse_andps_reg_reg (code, ins->sreg1, ins->sreg2);
5544                         break;
5545                 case OP_ANDNPS:
5546                         amd64_sse_andnps_reg_reg (code, ins->sreg1, ins->sreg2);
5547                         break;
5548                 case OP_ORPS:
5549                         amd64_sse_orps_reg_reg (code, ins->sreg1, ins->sreg2);
5550                         break;
5551                 case OP_XORPS:
5552                         amd64_sse_xorps_reg_reg (code, ins->sreg1, ins->sreg2);
5553                         break;
5554                 case OP_SQRTPS:
5555                         amd64_sse_sqrtps_reg_reg (code, ins->dreg, ins->sreg1);
5556                         break;
5557                 case OP_RSQRTPS:
5558                         amd64_sse_rsqrtps_reg_reg (code, ins->dreg, ins->sreg1);
5559                         break;
5560                 case OP_RCPPS:
5561                         amd64_sse_rcpps_reg_reg (code, ins->dreg, ins->sreg1);
5562                         break;
5563                 case OP_ADDSUBPS:
5564                         amd64_sse_addsubps_reg_reg (code, ins->sreg1, ins->sreg2);
5565                         break;
5566                 case OP_HADDPS:
5567                         amd64_sse_haddps_reg_reg (code, ins->sreg1, ins->sreg2);
5568                         break;
5569                 case OP_HSUBPS:
5570                         amd64_sse_hsubps_reg_reg (code, ins->sreg1, ins->sreg2);
5571                         break;
5572                 case OP_DUPPS_HIGH:
5573                         amd64_sse_movshdup_reg_reg (code, ins->dreg, ins->sreg1);
5574                         break;
5575                 case OP_DUPPS_LOW:
5576                         amd64_sse_movsldup_reg_reg (code, ins->dreg, ins->sreg1);
5577                         break;
5578
5579                 case OP_PSHUFLEW_HIGH:
5580                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
5581                         amd64_sse_pshufhw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
5582                         break;
5583                 case OP_PSHUFLEW_LOW:
5584                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
5585                         amd64_sse_pshuflw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
5586                         break;
5587                 case OP_PSHUFLED:
5588                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
5589                         amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
5590                         break;
5591
5592                 case OP_ADDPD:
5593                         amd64_sse_addpd_reg_reg (code, ins->sreg1, ins->sreg2);
5594                         break;
5595                 case OP_DIVPD:
5596                         amd64_sse_divpd_reg_reg (code, ins->sreg1, ins->sreg2);
5597                         break;
5598                 case OP_MULPD:
5599                         amd64_sse_mulpd_reg_reg (code, ins->sreg1, ins->sreg2);
5600                         break;
5601                 case OP_SUBPD:
5602                         amd64_sse_subpd_reg_reg (code, ins->sreg1, ins->sreg2);
5603                         break;
5604                 case OP_MAXPD:
5605                         amd64_sse_maxpd_reg_reg (code, ins->sreg1, ins->sreg2);
5606                         break;
5607                 case OP_MINPD:
5608                         amd64_sse_minpd_reg_reg (code, ins->sreg1, ins->sreg2);
5609                         break;
5610                 case OP_COMPPD:
5611                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 7);
5612                         amd64_sse_cmppd_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
5613                         break;
5614                 case OP_ANDPD:
5615                         amd64_sse_andpd_reg_reg (code, ins->sreg1, ins->sreg2);
5616                         break;
5617                 case OP_ANDNPD:
5618                         amd64_sse_andnpd_reg_reg (code, ins->sreg1, ins->sreg2);
5619                         break;
5620                 case OP_ORPD:
5621                         amd64_sse_orpd_reg_reg (code, ins->sreg1, ins->sreg2);
5622                         break;
5623                 case OP_XORPD:
5624                         amd64_sse_xorpd_reg_reg (code, ins->sreg1, ins->sreg2);
5625                         break;
5626                 case OP_SQRTPD:
5627                         amd64_sse_sqrtpd_reg_reg (code, ins->dreg, ins->sreg1);
5628                         break;
5629                 case OP_ADDSUBPD:
5630                         amd64_sse_addsubpd_reg_reg (code, ins->sreg1, ins->sreg2);
5631                         break;
5632                 case OP_HADDPD:
5633                         amd64_sse_haddpd_reg_reg (code, ins->sreg1, ins->sreg2);
5634                         break;
5635                 case OP_HSUBPD:
5636                         amd64_sse_hsubpd_reg_reg (code, ins->sreg1, ins->sreg2);
5637                         break;
5638                 case OP_DUPPD:
5639                         amd64_sse_movddup_reg_reg (code, ins->dreg, ins->sreg1);
5640                         break;
5641
5642                 case OP_EXTRACT_MASK:
5643                         amd64_sse_pmovmskb_reg_reg (code, ins->dreg, ins->sreg1);
5644                         break;
5645
5646                 case OP_PAND:
5647                         amd64_sse_pand_reg_reg (code, ins->sreg1, ins->sreg2);
5648                         break;
5649                 case OP_POR:
5650                         amd64_sse_por_reg_reg (code, ins->sreg1, ins->sreg2);
5651                         break;
5652                 case OP_PXOR:
5653                         amd64_sse_pxor_reg_reg (code, ins->sreg1, ins->sreg2);
5654                         break;
5655
5656                 case OP_PADDB:
5657                         amd64_sse_paddb_reg_reg (code, ins->sreg1, ins->sreg2);
5658                         break;
5659                 case OP_PADDW:
5660                         amd64_sse_paddw_reg_reg (code, ins->sreg1, ins->sreg2);
5661                         break;
5662                 case OP_PADDD:
5663                         amd64_sse_paddd_reg_reg (code, ins->sreg1, ins->sreg2);
5664                         break;
5665                 case OP_PADDQ:
5666                         amd64_sse_paddq_reg_reg (code, ins->sreg1, ins->sreg2);
5667                         break;
5668
5669                 case OP_PSUBB:
5670                         amd64_sse_psubb_reg_reg (code, ins->sreg1, ins->sreg2);
5671                         break;
5672                 case OP_PSUBW:
5673                         amd64_sse_psubw_reg_reg (code, ins->sreg1, ins->sreg2);
5674                         break;
5675                 case OP_PSUBD:
5676                         amd64_sse_psubd_reg_reg (code, ins->sreg1, ins->sreg2);
5677                         break;
5678                 case OP_PSUBQ:
5679                         amd64_sse_psubq_reg_reg (code, ins->sreg1, ins->sreg2);
5680                         break;
5681
5682                 case OP_PMAXB_UN:
5683                         amd64_sse_pmaxub_reg_reg (code, ins->sreg1, ins->sreg2);
5684                         break;
5685                 case OP_PMAXW_UN:
5686                         amd64_sse_pmaxuw_reg_reg (code, ins->sreg1, ins->sreg2);
5687                         break;
5688                 case OP_PMAXD_UN:
5689                         amd64_sse_pmaxud_reg_reg (code, ins->sreg1, ins->sreg2);
5690                         break;
5691
5692                 case OP_PMAXB:
5693                         amd64_sse_pmaxsb_reg_reg (code, ins->sreg1, ins->sreg2);
5694                         break;
5695                 case OP_PMAXW:
5696                         amd64_sse_pmaxsw_reg_reg (code, ins->sreg1, ins->sreg2);
5697                         break;
5698                 case OP_PMAXD:
5699                         amd64_sse_pmaxsd_reg_reg (code, ins->sreg1, ins->sreg2);
5700                         break;
5701
5702                 case OP_PAVGB_UN:
5703                         amd64_sse_pavgb_reg_reg (code, ins->sreg1, ins->sreg2);
5704                         break;
5705                 case OP_PAVGW_UN:
5706                         amd64_sse_pavgw_reg_reg (code, ins->sreg1, ins->sreg2);
5707                         break;
5708
5709                 case OP_PMINB_UN:
5710                         amd64_sse_pminub_reg_reg (code, ins->sreg1, ins->sreg2);
5711                         break;
5712                 case OP_PMINW_UN:
5713                         amd64_sse_pminuw_reg_reg (code, ins->sreg1, ins->sreg2);
5714                         break;
5715                 case OP_PMIND_UN:
5716                         amd64_sse_pminud_reg_reg (code, ins->sreg1, ins->sreg2);
5717                         break;
5718
5719                 case OP_PMINB:
5720                         amd64_sse_pminsb_reg_reg (code, ins->sreg1, ins->sreg2);
5721                         break;
5722                 case OP_PMINW:
5723                         amd64_sse_pminsw_reg_reg (code, ins->sreg1, ins->sreg2);
5724                         break;
5725                 case OP_PMIND:
5726                         amd64_sse_pminsd_reg_reg (code, ins->sreg1, ins->sreg2);
5727                         break;
5728
5729                 case OP_PCMPEQB:
5730                         amd64_sse_pcmpeqb_reg_reg (code, ins->sreg1, ins->sreg2);
5731                         break;
5732                 case OP_PCMPEQW:
5733                         amd64_sse_pcmpeqw_reg_reg (code, ins->sreg1, ins->sreg2);
5734                         break;
5735                 case OP_PCMPEQD:
5736                         amd64_sse_pcmpeqd_reg_reg (code, ins->sreg1, ins->sreg2);
5737                         break;
5738                 case OP_PCMPEQQ:
5739                         amd64_sse_pcmpeqq_reg_reg (code, ins->sreg1, ins->sreg2);
5740                         break;
5741
5742                 case OP_PCMPGTB:
5743                         amd64_sse_pcmpgtb_reg_reg (code, ins->sreg1, ins->sreg2);
5744                         break;
5745                 case OP_PCMPGTW:
5746                         amd64_sse_pcmpgtw_reg_reg (code, ins->sreg1, ins->sreg2);
5747                         break;
5748                 case OP_PCMPGTD:
5749                         amd64_sse_pcmpgtd_reg_reg (code, ins->sreg1, ins->sreg2);
5750                         break;
5751                 case OP_PCMPGTQ:
5752                         amd64_sse_pcmpgtq_reg_reg (code, ins->sreg1, ins->sreg2);
5753                         break;
5754
5755                 case OP_PSUM_ABS_DIFF:
5756                         amd64_sse_psadbw_reg_reg (code, ins->sreg1, ins->sreg2);
5757                         break;
5758
5759                 case OP_UNPACK_LOWB:
5760                         amd64_sse_punpcklbw_reg_reg (code, ins->sreg1, ins->sreg2);
5761                         break;
5762                 case OP_UNPACK_LOWW:
5763                         amd64_sse_punpcklwd_reg_reg (code, ins->sreg1, ins->sreg2);
5764                         break;
5765                 case OP_UNPACK_LOWD:
5766                         amd64_sse_punpckldq_reg_reg (code, ins->sreg1, ins->sreg2);
5767                         break;
5768                 case OP_UNPACK_LOWQ:
5769                         amd64_sse_punpcklqdq_reg_reg (code, ins->sreg1, ins->sreg2);
5770                         break;
5771                 case OP_UNPACK_LOWPS:
5772                         amd64_sse_unpcklps_reg_reg (code, ins->sreg1, ins->sreg2);
5773                         break;
5774                 case OP_UNPACK_LOWPD:
5775                         amd64_sse_unpcklpd_reg_reg (code, ins->sreg1, ins->sreg2);
5776                         break;
5777
5778                 case OP_UNPACK_HIGHB:
5779                         amd64_sse_punpckhbw_reg_reg (code, ins->sreg1, ins->sreg2);
5780                         break;
5781                 case OP_UNPACK_HIGHW:
5782                         amd64_sse_punpckhwd_reg_reg (code, ins->sreg1, ins->sreg2);
5783                         break;
5784                 case OP_UNPACK_HIGHD:
5785                         amd64_sse_punpckhdq_reg_reg (code, ins->sreg1, ins->sreg2);
5786                         break;
5787                 case OP_UNPACK_HIGHQ:
5788                         amd64_sse_punpckhqdq_reg_reg (code, ins->sreg1, ins->sreg2);
5789                         break;
5790                 case OP_UNPACK_HIGHPS:
5791                         amd64_sse_unpckhps_reg_reg (code, ins->sreg1, ins->sreg2);
5792                         break;
5793                 case OP_UNPACK_HIGHPD:
5794                         amd64_sse_unpckhpd_reg_reg (code, ins->sreg1, ins->sreg2);
5795                         break;
5796
5797                 case OP_PACKW:
5798                         amd64_sse_packsswb_reg_reg (code, ins->sreg1, ins->sreg2);
5799                         break;
5800                 case OP_PACKD:
5801                         amd64_sse_packssdw_reg_reg (code, ins->sreg1, ins->sreg2);
5802                         break;
5803                 case OP_PACKW_UN:
5804                         amd64_sse_packuswb_reg_reg (code, ins->sreg1, ins->sreg2);
5805                         break;
5806                 case OP_PACKD_UN:
5807                         amd64_sse_packusdw_reg_reg (code, ins->sreg1, ins->sreg2);
5808                         break;
5809
5810                 case OP_PADDB_SAT_UN:
5811                         amd64_sse_paddusb_reg_reg (code, ins->sreg1, ins->sreg2);
5812                         break;
5813                 case OP_PSUBB_SAT_UN:
5814                         amd64_sse_psubusb_reg_reg (code, ins->sreg1, ins->sreg2);
5815                         break;
5816                 case OP_PADDW_SAT_UN:
5817                         amd64_sse_paddusw_reg_reg (code, ins->sreg1, ins->sreg2);
5818                         break;
5819                 case OP_PSUBW_SAT_UN:
5820                         amd64_sse_psubusw_reg_reg (code, ins->sreg1, ins->sreg2);
5821                         break;
5822
5823                 case OP_PADDB_SAT:
5824                         amd64_sse_paddsb_reg_reg (code, ins->sreg1, ins->sreg2);
5825                         break;
5826                 case OP_PSUBB_SAT:
5827                         amd64_sse_psubsb_reg_reg (code, ins->sreg1, ins->sreg2);
5828                         break;
5829                 case OP_PADDW_SAT:
5830                         amd64_sse_paddsw_reg_reg (code, ins->sreg1, ins->sreg2);
5831                         break;
5832                 case OP_PSUBW_SAT:
5833                         amd64_sse_psubsw_reg_reg (code, ins->sreg1, ins->sreg2);
5834                         break;
5835
5836                 case OP_PMULW:
5837                         amd64_sse_pmullw_reg_reg (code, ins->sreg1, ins->sreg2);
5838                         break;
5839                 case OP_PMULD:
5840                         amd64_sse_pmulld_reg_reg (code, ins->sreg1, ins->sreg2);
5841                         break;
5842                 case OP_PMULQ:
5843                         amd64_sse_pmuludq_reg_reg (code, ins->sreg1, ins->sreg2);
5844                         break;
5845                 case OP_PMULW_HIGH_UN:
5846                         amd64_sse_pmulhuw_reg_reg (code, ins->sreg1, ins->sreg2);
5847                         break;
5848                 case OP_PMULW_HIGH:
5849                         amd64_sse_pmulhw_reg_reg (code, ins->sreg1, ins->sreg2);
5850                         break;
5851
5852                 case OP_PSHRW:
5853                         amd64_sse_psrlw_reg_imm (code, ins->dreg, ins->inst_imm);
5854                         break;
5855                 case OP_PSHRW_REG:
5856                         amd64_sse_psrlw_reg_reg (code, ins->dreg, ins->sreg2);
5857                         break;
5858
5859                 case OP_PSARW:
5860                         amd64_sse_psraw_reg_imm (code, ins->dreg, ins->inst_imm);
5861                         break;
5862                 case OP_PSARW_REG:
5863                         amd64_sse_psraw_reg_reg (code, ins->dreg, ins->sreg2);
5864                         break;
5865
5866                 case OP_PSHLW:
5867                         amd64_sse_psllw_reg_imm (code, ins->dreg, ins->inst_imm);
5868                         break;
5869                 case OP_PSHLW_REG:
5870                         amd64_sse_psllw_reg_reg (code, ins->dreg, ins->sreg2);
5871                         break;
5872
5873                 case OP_PSHRD:
5874                         amd64_sse_psrld_reg_imm (code, ins->dreg, ins->inst_imm);
5875                         break;
5876                 case OP_PSHRD_REG:
5877                         amd64_sse_psrld_reg_reg (code, ins->dreg, ins->sreg2);
5878                         break;
5879
5880                 case OP_PSARD:
5881                         amd64_sse_psrad_reg_imm (code, ins->dreg, ins->inst_imm);
5882                         break;
5883                 case OP_PSARD_REG:
5884                         amd64_sse_psrad_reg_reg (code, ins->dreg, ins->sreg2);
5885                         break;
5886
5887                 case OP_PSHLD:
5888                         amd64_sse_pslld_reg_imm (code, ins->dreg, ins->inst_imm);
5889                         break;
5890                 case OP_PSHLD_REG:
5891                         amd64_sse_pslld_reg_reg (code, ins->dreg, ins->sreg2);
5892                         break;
5893
5894                 case OP_PSHRQ:
5895                         amd64_sse_psrlq_reg_imm (code, ins->dreg, ins->inst_imm);
5896                         break;
5897                 case OP_PSHRQ_REG:
5898                         amd64_sse_psrlq_reg_reg (code, ins->dreg, ins->sreg2);
5899                         break;
5900
5901                 /*TODO: This is appart of the sse spec but not added
5902                 case OP_PSARQ:
5903                         amd64_sse_psraq_reg_imm (code, ins->dreg, ins->inst_imm);
5904                         break;
5905                 case OP_PSARQ_REG:
5906                         amd64_sse_psraq_reg_reg (code, ins->dreg, ins->sreg2);
5907                         break;
5908                 */
5909
5910                 case OP_PSHLQ:
5911                         amd64_sse_psllq_reg_imm (code, ins->dreg, ins->inst_imm);
5912                         break;
5913                 case OP_PSHLQ_REG:
5914                         amd64_sse_psllq_reg_reg (code, ins->dreg, ins->sreg2);
5915                         break;
5916
5917                 case OP_ICONV_TO_X:
5918                         amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 4);
5919                         break;
5920                 case OP_EXTRACT_I4:
5921                         amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 4);
5922                         break;
5923                 case OP_EXTRACT_I8:
5924                         if (ins->inst_c0) {
5925                                 amd64_movhlps_reg_reg (code, AMD64_XMM15, ins->sreg1);
5926                                 amd64_movd_reg_xreg_size (code, ins->dreg, AMD64_XMM15, 8);
5927                         } else {
5928                                 amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 8);
5929                         }
5930                         break;
5931                 case OP_EXTRACT_I1:
5932                 case OP_EXTRACT_U1:
5933                         amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 4);
5934                         if (ins->inst_c0)
5935                                 amd64_shift_reg_imm (code, X86_SHR, ins->dreg, ins->inst_c0 * 8);
5936                         amd64_widen_reg (code, ins->dreg, ins->dreg, ins->opcode == OP_EXTRACT_I1, FALSE);
5937                         break;
5938                 case OP_EXTRACT_I2:
5939                 case OP_EXTRACT_U2:
5940                         /*amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 4);
5941                         if (ins->inst_c0)
5942                                 amd64_shift_reg_imm_size (code, X86_SHR, ins->dreg, 16, 4);*/
5943                         amd64_sse_pextrw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
5944                         amd64_widen_reg_size (code, ins->dreg, ins->dreg, ins->opcode == OP_EXTRACT_I2, TRUE, 4);
5945                         break;
5946                 case OP_EXTRACT_R8:
5947                         if (ins->inst_c0)
5948                                 amd64_movhlps_reg_reg (code, ins->dreg, ins->sreg1);
5949                         else
5950                                 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
5951                         break;
5952                 case OP_INSERT_I2:
5953                         amd64_sse_pinsrw_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
5954                         break;
5955                 case OP_EXTRACTX_U2:
5956                         amd64_sse_pextrw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
5957                         break;
5958                 case OP_INSERTX_U1_SLOW:
5959                         /*sreg1 is the extracted ireg (scratch)
5960                         /sreg2 is the to be inserted ireg (scratch)
5961                         /dreg is the xreg to receive the value*/
5962
5963                         /*clear the bits from the extracted word*/
5964                         amd64_alu_reg_imm (code, X86_AND, ins->sreg1, ins->inst_c0 & 1 ? 0x00FF : 0xFF00);
5965                         /*shift the value to insert if needed*/
5966                         if (ins->inst_c0 & 1)
5967                                 amd64_shift_reg_imm_size (code, X86_SHL, ins->sreg2, 8, 4);
5968                         /*join them together*/
5969                         amd64_alu_reg_reg (code, X86_OR, ins->sreg1, ins->sreg2);
5970                         amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0 / 2);
5971                         break;
5972                 case OP_INSERTX_I4_SLOW:
5973                         amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg2, ins->inst_c0 * 2);
5974                         amd64_shift_reg_imm (code, X86_SHR, ins->sreg2, 16);
5975                         amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg2, ins->inst_c0 * 2 + 1);
5976                         break;
5977                 case OP_INSERTX_I8_SLOW:
5978                         amd64_movd_xreg_reg_size(code, AMD64_XMM15, ins->sreg2, 8);
5979                         if (ins->inst_c0)
5980                                 amd64_movlhps_reg_reg (code, ins->dreg, AMD64_XMM15);
5981                         else
5982                                 amd64_sse_movsd_reg_reg (code, ins->dreg, AMD64_XMM15);
5983                         break;
5984
5985                 case OP_INSERTX_R4_SLOW:
5986                         switch (ins->inst_c0) {
5987                         case 0:
5988                                 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg2);
5989                                 break;
5990                         case 1:
5991                                 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(1, 0, 2, 3));
5992                                 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg2);
5993                                 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(1, 0, 2, 3));
5994                                 break;
5995                         case 2:
5996                                 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(2, 1, 0, 3));
5997                                 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg2);
5998                                 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(2, 1, 0, 3));
5999                                 break;
6000                         case 3:
6001                                 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(3, 1, 2, 0));
6002                                 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg2);
6003                                 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(3, 1, 2, 0));
6004                                 break;
6005                         }
6006                         break;
6007                 case OP_INSERTX_R8_SLOW:
6008                         if (ins->inst_c0)
6009                                 amd64_movlhps_reg_reg (code, ins->dreg, ins->sreg2);
6010                         else
6011                                 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg2);
6012                         break;
6013                 case OP_STOREX_MEMBASE_REG:
6014                 case OP_STOREX_MEMBASE:
6015                         amd64_sse_movups_membase_reg (code, ins->dreg, ins->inst_offset, ins->sreg1);
6016                         break;
6017                 case OP_LOADX_MEMBASE:
6018                         amd64_sse_movups_reg_membase (code, ins->dreg, ins->sreg1, ins->inst_offset);
6019                         break;
6020                 case OP_LOADX_ALIGNED_MEMBASE:
6021                         amd64_sse_movaps_reg_membase (code, ins->dreg, ins->sreg1, ins->inst_offset);
6022                         break;
6023                 case OP_STOREX_ALIGNED_MEMBASE_REG:
6024                         amd64_sse_movaps_membase_reg (code, ins->dreg, ins->inst_offset, ins->sreg1);
6025                         break;
6026                 case OP_STOREX_NTA_MEMBASE_REG:
6027                         amd64_sse_movntps_reg_membase (code, ins->dreg, ins->sreg1, ins->inst_offset);
6028                         break;
6029                 case OP_PREFETCH_MEMBASE:
6030                         amd64_sse_prefetch_reg_membase (code, ins->backend.arg_info, ins->sreg1, ins->inst_offset);
6031                         break;
6032
6033                 case OP_XMOVE:
6034                         /*FIXME the peephole pass should have killed this*/
6035                         if (ins->dreg != ins->sreg1)
6036                                 amd64_sse_movaps_reg_reg (code, ins->dreg, ins->sreg1);
6037                         break;
6038                 case OP_XZERO:
6039                         amd64_sse_pxor_reg_reg (code, ins->dreg, ins->dreg);
6040                         break;
6041                 case OP_ICONV_TO_R8_RAW:
6042                         amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 4);
6043                         amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
6044                         break;
6045
6046                 case OP_FCONV_TO_R8_X:
6047                         amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
6048                         break;
6049
6050                 case OP_XCONV_R8_TO_I4:
6051                         amd64_sse_cvttsd2si_reg_xreg_size (code, ins->dreg, ins->sreg1, 4);
6052                         switch (ins->backend.source_opcode) {
6053                         case OP_FCONV_TO_I1:
6054                                 amd64_widen_reg (code, ins->dreg, ins->dreg, TRUE, FALSE);
6055                                 break;
6056                         case OP_FCONV_TO_U1:
6057                                 amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
6058                                 break;
6059                         case OP_FCONV_TO_I2:
6060                                 amd64_widen_reg (code, ins->dreg, ins->dreg, TRUE, TRUE);
6061                                 break;
6062                         case OP_FCONV_TO_U2:
6063                                 amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, TRUE);
6064                                 break;
6065                         }
6066                         break;
6067
6068                 case OP_EXPAND_I2:
6069                         amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg1, 0);
6070                         amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg1, 1);
6071                         amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0);
6072                         break;
6073                 case OP_EXPAND_I4:
6074                         amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 4);
6075                         amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0);
6076                         break;
6077                 case OP_EXPAND_I8:
6078                         amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 8);
6079                         amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0x44);
6080                         break;
6081                 case OP_EXPAND_R4:
6082                         amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
6083                         amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->dreg);
6084                         amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0);
6085                         break;
6086                 case OP_EXPAND_R8:
6087                         amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
6088                         amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0x44);
6089                         break;
6090 #endif
6091                 case OP_LIVERANGE_START: {
6092                         if (cfg->verbose_level > 1)
6093                                 printf ("R%d START=0x%x\n", MONO_VARINFO (cfg, ins->inst_c0)->vreg, (int)(code - cfg->native_code));
6094                         MONO_VARINFO (cfg, ins->inst_c0)->live_range_start = code - cfg->native_code;
6095                         break;
6096                 }
6097                 case OP_LIVERANGE_END: {
6098                         if (cfg->verbose_level > 1)
6099                                 printf ("R%d END=0x%x\n", MONO_VARINFO (cfg, ins->inst_c0)->vreg, (int)(code - cfg->native_code));
6100                         MONO_VARINFO (cfg, ins->inst_c0)->live_range_end = code - cfg->native_code;
6101                         break;
6102                 }
6103                 case OP_NACL_GC_SAFE_POINT: {
6104 #if defined(__native_client_codegen__)
6105                         code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, (gpointer)mono_nacl_gc, TRUE);
6106 #endif
6107                         break;
6108                 }
6109                 default:
6110                         g_warning ("unknown opcode %s in %s()\n", mono_inst_name (ins->opcode), __FUNCTION__);
6111                         g_assert_not_reached ();
6112                 }
6113
6114                 if ((code - cfg->native_code - offset) > max_len) {
6115 #if !defined(__native_client_codegen__)
6116                         g_warning ("wrong maximal instruction length of instruction %s (expected %d, got %ld)",
6117                                    mono_inst_name (ins->opcode), max_len, code - cfg->native_code - offset);
6118                         g_assert_not_reached ();
6119 #endif
6120                 }
6121
6122                 last_ins = ins;
6123                 last_offset = offset;
6124         }
6125
6126         cfg->code_len = code - cfg->native_code;
6127 }
6128
6129 #endif /* DISABLE_JIT */
6130
6131 void
6132 mono_arch_register_lowlevel_calls (void)
6133 {
6134         /* The signature doesn't matter */
6135         mono_register_jit_icall (mono_amd64_throw_exception, "mono_amd64_throw_exception", mono_create_icall_signature ("void"), TRUE);
6136 }
6137
6138 void
6139 mono_arch_patch_code (MonoMethod *method, MonoDomain *domain, guint8 *code, MonoJumpInfo *ji, gboolean run_cctors)
6140 {
6141         MonoJumpInfo *patch_info;
6142         gboolean compile_aot = !run_cctors;
6143
6144         for (patch_info = ji; patch_info; patch_info = patch_info->next) {
6145                 unsigned char *ip = patch_info->ip.i + code;
6146                 unsigned char *target;
6147
6148                 target = mono_resolve_patch_target (method, domain, code, patch_info, run_cctors);
6149
6150                 if (compile_aot) {
6151                         switch (patch_info->type) {
6152                         case MONO_PATCH_INFO_BB:
6153                         case MONO_PATCH_INFO_LABEL:
6154                                 break;
6155                         default:
6156                                 /* No need to patch these */
6157                                 continue;
6158                         }
6159                 }
6160
6161                 switch (patch_info->type) {
6162                 case MONO_PATCH_INFO_NONE:
6163                         continue;
6164                 case MONO_PATCH_INFO_METHOD_REL:
6165                 case MONO_PATCH_INFO_R8:
6166                 case MONO_PATCH_INFO_R4:
6167                         g_assert_not_reached ();
6168                         continue;
6169                 case MONO_PATCH_INFO_BB:
6170                         break;
6171                 default:
6172                         break;
6173                 }
6174
6175                 /*
6176                  * Debug code to help track down problems where the target of a near call is
6177                  * is not valid.
6178                  */
6179                 if (amd64_is_near_call (ip)) {
6180                         gint64 disp = (guint8*)target - (guint8*)ip;
6181
6182                         if (!amd64_is_imm32 (disp)) {
6183                                 printf ("TYPE: %d\n", patch_info->type);
6184                                 switch (patch_info->type) {
6185                                 case MONO_PATCH_INFO_INTERNAL_METHOD:
6186                                         printf ("V: %s\n", patch_info->data.name);
6187                                         break;
6188                                 case MONO_PATCH_INFO_METHOD_JUMP:
6189                                 case MONO_PATCH_INFO_METHOD:
6190                                         printf ("V: %s\n", patch_info->data.method->name);
6191                                         break;
6192                                 default:
6193                                         break;
6194                                 }
6195                         }
6196                 }
6197
6198                 amd64_patch (ip, (gpointer)target);
6199         }
6200 }
6201
6202 #ifndef DISABLE_JIT
6203
6204 static int
6205 get_max_epilog_size (MonoCompile *cfg)
6206 {
6207         int max_epilog_size = 16;
6208
6209         if (cfg->method->save_lmf)
6210                 max_epilog_size += 256;
6211
6212         if (mono_jit_trace_calls != NULL)
6213                 max_epilog_size += 50;
6214
6215         if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
6216                 max_epilog_size += 50;
6217
6218         max_epilog_size += (AMD64_NREG * 2);
6219
6220         return max_epilog_size;
6221 }
6222
6223 /*
6224  * This macro is used for testing whenever the unwinder works correctly at every point
6225  * where an async exception can happen.
6226  */
6227 /* This will generate a SIGSEGV at the given point in the code */
6228 #define async_exc_point(code) do { \
6229     if (mono_inject_async_exc_method && mono_method_desc_full_match (mono_inject_async_exc_method, cfg->method)) { \
6230          if (cfg->arch.async_point_count == mono_inject_async_exc_pos) \
6231              amd64_mov_reg_mem (code, AMD64_RAX, 0, 4); \
6232          cfg->arch.async_point_count ++; \
6233     } \
6234 } while (0)
6235
6236 guint8 *
6237 mono_arch_emit_prolog (MonoCompile *cfg)
6238 {
6239         MonoMethod *method = cfg->method;
6240         MonoBasicBlock *bb;
6241         MonoMethodSignature *sig;
6242         MonoInst *ins;
6243         int alloc_size, pos, i, cfa_offset, quad, max_epilog_size;
6244         guint8 *code;
6245         CallInfo *cinfo;
6246         gint32 lmf_offset = cfg->arch.lmf_offset;
6247         gboolean args_clobbered = FALSE;
6248         gboolean trace = FALSE;
6249 #ifdef __native_client_codegen__
6250         guint alignment_check;
6251 #endif
6252
6253         cfg->code_size =  MAX (cfg->header->code_size * 4, 10240);
6254
6255 #if defined(__default_codegen__)
6256         code = cfg->native_code = g_malloc (cfg->code_size);
6257 #elif defined(__native_client_codegen__)
6258         /* native_code_alloc is not 32-byte aligned, native_code is. */
6259         cfg->native_code_alloc = g_malloc (cfg->code_size + kNaClAlignment);
6260
6261         /* Align native_code to next nearest kNaclAlignment byte. */
6262         cfg->native_code = (uintptr_t)cfg->native_code_alloc + kNaClAlignment;
6263         cfg->native_code = (uintptr_t)cfg->native_code & ~kNaClAlignmentMask;
6264
6265         code = cfg->native_code;
6266
6267         alignment_check = (guint)cfg->native_code & kNaClAlignmentMask;
6268         g_assert (alignment_check == 0);
6269 #endif
6270
6271         if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
6272                 trace = TRUE;
6273
6274         /* Amount of stack space allocated by register saving code */
6275         pos = 0;
6276
6277         /* Offset between RSP and the CFA */
6278         cfa_offset = 0;
6279
6280         /*
6281          * The prolog consists of the following parts:
6282          * FP present:
6283          * - push rbp, mov rbp, rsp
6284          * - save callee saved regs using pushes
6285          * - allocate frame
6286          * - save rgctx if needed
6287          * - save lmf if needed
6288          * FP not present:
6289          * - allocate frame
6290          * - save rgctx if needed
6291          * - save lmf if needed
6292          * - save callee saved regs using moves
6293          */
6294
6295         // CFA = sp + 8
6296         cfa_offset = 8;
6297         mono_emit_unwind_op_def_cfa (cfg, code, AMD64_RSP, 8);
6298         // IP saved at CFA - 8
6299         mono_emit_unwind_op_offset (cfg, code, AMD64_RIP, -cfa_offset);
6300         async_exc_point (code);
6301
6302         if (!cfg->arch.omit_fp) {
6303                 amd64_push_reg (code, AMD64_RBP);
6304                 cfa_offset += 8;
6305                 mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
6306                 mono_emit_unwind_op_offset (cfg, code, AMD64_RBP, - cfa_offset);
6307                 async_exc_point (code);
6308 #ifdef HOST_WIN32
6309                 mono_arch_unwindinfo_add_push_nonvol (&cfg->arch.unwindinfo, cfg->native_code, code, AMD64_RBP);
6310 #endif
6311
6312                 amd64_mov_reg_reg (code, AMD64_RBP, AMD64_RSP, sizeof(mgreg_t));
6313                 mono_emit_unwind_op_def_cfa_reg (cfg, code, AMD64_RBP);
6314                 async_exc_point (code);
6315 #ifdef HOST_WIN32
6316                 mono_arch_unwindinfo_add_set_fpreg (&cfg->arch.unwindinfo, cfg->native_code, code, AMD64_RBP);
6317 #endif
6318         }
6319
6320         /* Save callee saved registers */
6321         if (!cfg->arch.omit_fp && !method->save_lmf) {
6322                 int offset = cfa_offset;
6323
6324                 for (i = 0; i < AMD64_NREG; ++i)
6325                         if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
6326                                 amd64_push_reg (code, i);
6327                                 pos += 8; /* AMD64 push inst is always 8 bytes, no way to change it */
6328                                 offset += 8;
6329                                 mono_emit_unwind_op_offset (cfg, code, i, - offset);
6330                                 async_exc_point (code);
6331                         }
6332         }
6333
6334         /* The param area is always at offset 0 from sp */
6335         /* This needs to be allocated here, since it has to come after the spill area */
6336         if (cfg->arch.no_pushes && cfg->param_area) {
6337                 if (cfg->arch.omit_fp)
6338                         // FIXME:
6339                         g_assert_not_reached ();
6340                 cfg->stack_offset += ALIGN_TO (cfg->param_area, sizeof(mgreg_t));
6341         }
6342
6343         if (cfg->arch.omit_fp) {
6344                 /*
6345                  * On enter, the stack is misaligned by the the pushing of the return
6346                  * address. It is either made aligned by the pushing of %rbp, or by
6347                  * this.
6348                  */
6349                 alloc_size = ALIGN_TO (cfg->stack_offset, 8);
6350                 if ((alloc_size % 16) == 0)
6351                         alloc_size += 8;
6352         } else {
6353                 alloc_size = ALIGN_TO (cfg->stack_offset, MONO_ARCH_FRAME_ALIGNMENT);
6354
6355                 alloc_size -= pos;
6356         }
6357
6358         cfg->arch.stack_alloc_size = alloc_size;
6359
6360         /* Allocate stack frame */
6361         if (alloc_size) {
6362                 /* See mono_emit_stack_alloc */
6363 #if defined(HOST_WIN32) || defined(MONO_ARCH_SIGSEGV_ON_ALTSTACK)
6364                 guint32 remaining_size = alloc_size;
6365                 /*FIXME handle unbounded code expansion, we should use a loop in case of more than X interactions*/
6366                 guint32 required_code_size = ((remaining_size / 0x1000) + 1) * 10; /*10 is the max size of amd64_alu_reg_imm + amd64_test_membase_reg*/
6367                 guint32 offset = code - cfg->native_code;
6368                 if (G_UNLIKELY (required_code_size >= (cfg->code_size - offset))) {
6369                         while (required_code_size >= (cfg->code_size - offset))
6370                                 cfg->code_size *= 2;
6371                         cfg->native_code = mono_realloc_native_code (cfg);
6372                         code = cfg->native_code + offset;
6373                         mono_jit_stats.code_reallocs++;
6374                 }
6375
6376                 while (remaining_size >= 0x1000) {
6377                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 0x1000);
6378                         if (cfg->arch.omit_fp) {
6379                                 cfa_offset += 0x1000;
6380                                 mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
6381                         }
6382                         async_exc_point (code);
6383 #ifdef HOST_WIN32
6384                         if (cfg->arch.omit_fp)
6385                                 mono_arch_unwindinfo_add_alloc_stack (&cfg->arch.unwindinfo, cfg->native_code, code, 0x1000);
6386 #endif
6387
6388                         amd64_test_membase_reg (code, AMD64_RSP, 0, AMD64_RSP);
6389                         remaining_size -= 0x1000;
6390                 }
6391                 if (remaining_size) {
6392                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, remaining_size);
6393                         if (cfg->arch.omit_fp) {
6394                                 cfa_offset += remaining_size;
6395                                 mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
6396                                 async_exc_point (code);
6397                         }
6398 #ifdef HOST_WIN32
6399                         if (cfg->arch.omit_fp)
6400                                 mono_arch_unwindinfo_add_alloc_stack (&cfg->arch.unwindinfo, cfg->native_code, code, remaining_size);
6401 #endif
6402                 }
6403 #else
6404                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, alloc_size);
6405                 if (cfg->arch.omit_fp) {
6406                         cfa_offset += alloc_size;
6407                         mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
6408                         async_exc_point (code);
6409                 }
6410 #endif
6411         }
6412
6413         /* Stack alignment check */
6414 #if 0
6415         {
6416                 amd64_mov_reg_reg (code, AMD64_RAX, AMD64_RSP, 8);
6417                 amd64_alu_reg_imm (code, X86_AND, AMD64_RAX, 0xf);
6418                 amd64_alu_reg_imm (code, X86_CMP, AMD64_RAX, 0);
6419                 x86_branch8 (code, X86_CC_EQ, 2, FALSE);
6420                 amd64_breakpoint (code);
6421         }
6422 #endif
6423
6424 #ifndef TARGET_WIN32
6425         if (mini_get_debug_options ()->init_stacks) {
6426                 /* Fill the stack frame with a dummy value to force deterministic behavior */
6427
6428                 /* Save registers to the red zone */
6429                 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDI, 8);
6430                 amd64_mov_membase_reg (code, AMD64_RSP, -16, AMD64_RCX, 8);
6431
6432                 amd64_mov_reg_imm (code, AMD64_RAX, 0x2a2a2a2a2a2a2a2a);
6433                 amd64_mov_reg_imm (code, AMD64_RCX, alloc_size / 8);
6434                 amd64_mov_reg_reg (code, AMD64_RDI, AMD64_RSP, 8);
6435
6436                 amd64_cld (code);
6437 #if defined(__default_codegen__)
6438                 amd64_prefix (code, X86_REP_PREFIX);
6439                 amd64_stosl (code);
6440 #elif defined(__native_client_codegen__)
6441                 /* NaCl stos pseudo-instruction */
6442                 amd64_codegen_pre (code);
6443                 /* First, clear the upper 32 bits of RDI (mov %edi, %edi)  */
6444                 amd64_mov_reg_reg (code, AMD64_RDI, AMD64_RDI, 4);
6445                 /* Add %r15 to %rdi using lea, condition flags unaffected. */
6446                 amd64_lea_memindex_size (code, AMD64_RDI, AMD64_R15, 0, AMD64_RDI, 0, 8);
6447                 amd64_prefix (code, X86_REP_PREFIX);
6448                 amd64_stosl (code);
6449                 amd64_codegen_post (code);
6450 #endif /* __native_client_codegen__ */
6451
6452                 amd64_mov_reg_membase (code, AMD64_RDI, AMD64_RSP, -8, 8);
6453                 amd64_mov_reg_membase (code, AMD64_RCX, AMD64_RSP, -16, 8);
6454         }
6455 #endif
6456
6457         /* Save LMF */
6458         if (method->save_lmf) {
6459                 /*
6460                  * The ip field is not set, the exception handling code will obtain it from the stack location pointed to by the sp field.
6461                  */
6462                 /*
6463                  * sp is saved right before calls but we need to save it here too so
6464                  * async stack walks would work.
6465                  */
6466                 amd64_mov_membase_reg (code, cfg->frame_reg, cfg->arch.lmf_offset + G_STRUCT_OFFSET (MonoLMF, rsp), AMD64_RSP, 8);
6467                 /* Skip method (only needed for trampoline LMF frames) */
6468                 /* Save callee saved regs */
6469                 for (i = 0; i < MONO_MAX_IREGS; ++i) {
6470                         int offset;
6471
6472                         switch (i) {
6473                         case AMD64_RBX: offset = G_STRUCT_OFFSET (MonoLMF, rbx); break;
6474                         case AMD64_RBP: offset = G_STRUCT_OFFSET (MonoLMF, rbp); break;
6475                         case AMD64_R12: offset = G_STRUCT_OFFSET (MonoLMF, r12); break;
6476                         case AMD64_R13: offset = G_STRUCT_OFFSET (MonoLMF, r13); break;
6477                         case AMD64_R14: offset = G_STRUCT_OFFSET (MonoLMF, r14); break;
6478 #ifndef __native_client_codegen__
6479                         case AMD64_R15: offset = G_STRUCT_OFFSET (MonoLMF, r15); break;
6480 #endif
6481 #ifdef HOST_WIN32
6482                         case AMD64_RDI: offset = G_STRUCT_OFFSET (MonoLMF, rdi); break;
6483                         case AMD64_RSI: offset = G_STRUCT_OFFSET (MonoLMF, rsi); break;
6484 #endif
6485                         default:
6486                                 offset = -1;
6487                                 break;
6488                         }
6489
6490                         if (offset != -1) {
6491                                 amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + offset, i, 8);
6492                                 if (cfg->arch.omit_fp || (i != AMD64_RBP))
6493                                         mono_emit_unwind_op_offset (cfg, code, i, - (cfa_offset - (lmf_offset + offset)));
6494                         }
6495                 }
6496         }
6497
6498         /* Save callee saved registers */
6499         if (cfg->arch.omit_fp && !method->save_lmf) {
6500                 gint32 save_area_offset = cfg->arch.reg_save_area_offset;
6501
6502                 /* Save caller saved registers after sp is adjusted */
6503                 /* The registers are saved at the bottom of the frame */
6504                 /* FIXME: Optimize this so the regs are saved at the end of the frame in increasing order */
6505                 for (i = 0; i < AMD64_NREG; ++i)
6506                         if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
6507                                 amd64_mov_membase_reg (code, AMD64_RSP, save_area_offset, i, 8);
6508                                 mono_emit_unwind_op_offset (cfg, code, i, - (cfa_offset - save_area_offset));
6509                                 save_area_offset += 8;
6510                                 async_exc_point (code);
6511                         }
6512         }
6513
6514         /* store runtime generic context */
6515         if (cfg->rgctx_var) {
6516                 g_assert (cfg->rgctx_var->opcode == OP_REGOFFSET &&
6517                                 (cfg->rgctx_var->inst_basereg == AMD64_RBP || cfg->rgctx_var->inst_basereg == AMD64_RSP));
6518
6519                 amd64_mov_membase_reg (code, cfg->rgctx_var->inst_basereg, cfg->rgctx_var->inst_offset, MONO_ARCH_RGCTX_REG, sizeof(gpointer));
6520         }
6521
6522         /* compute max_length in order to use short forward jumps */
6523         max_epilog_size = get_max_epilog_size (cfg);
6524         if (cfg->opt & MONO_OPT_BRANCH) {
6525                 for (bb = cfg->bb_entry; bb; bb = bb->next_bb) {
6526                         MonoInst *ins;
6527                         int max_length = 0;
6528
6529                         if (cfg->prof_options & MONO_PROFILE_COVERAGE)
6530                                 max_length += 6;
6531                         /* max alignment for loops */
6532                         if ((cfg->opt & MONO_OPT_LOOP) && bb_is_loop_start (bb))
6533                                 max_length += LOOP_ALIGNMENT;
6534 #ifdef __native_client_codegen__
6535                         /* max alignment for native client */
6536                         max_length += kNaClAlignment;
6537 #endif
6538
6539                         MONO_BB_FOR_EACH_INS (bb, ins) {
6540 #ifdef __native_client_codegen__
6541                                 {
6542                                         int space_in_block = kNaClAlignment -
6543                                                 ((max_length + cfg->code_len) & kNaClAlignmentMask);
6544                                         int max_len = ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
6545                                         if (space_in_block < max_len && max_len < kNaClAlignment) {
6546                                                 max_length += space_in_block;
6547                                         }
6548                                 }
6549 #endif  /*__native_client_codegen__*/
6550                                 max_length += ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
6551                         }
6552
6553                         /* Take prolog and epilog instrumentation into account */
6554                         if (bb == cfg->bb_entry || bb == cfg->bb_exit)
6555                                 max_length += max_epilog_size;
6556
6557                         bb->max_length = max_length;
6558                 }
6559         }
6560
6561         sig = mono_method_signature (method);
6562         pos = 0;
6563
6564         cinfo = cfg->arch.cinfo;
6565
6566         if (sig->ret->type != MONO_TYPE_VOID) {
6567                 /* Save volatile arguments to the stack */
6568                 if (cfg->vret_addr && (cfg->vret_addr->opcode != OP_REGVAR))
6569                         amd64_mov_membase_reg (code, cfg->vret_addr->inst_basereg, cfg->vret_addr->inst_offset, cinfo->ret.reg, 8);
6570         }
6571
6572         /* Keep this in sync with emit_load_volatile_arguments */
6573         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
6574                 ArgInfo *ainfo = cinfo->args + i;
6575                 gint32 stack_offset;
6576                 MonoType *arg_type;
6577
6578                 ins = cfg->args [i];
6579
6580                 if ((ins->flags & MONO_INST_IS_DEAD) && !trace)
6581                         /* Unused arguments */
6582                         continue;
6583
6584                 if (sig->hasthis && (i == 0))
6585                         arg_type = &mono_defaults.object_class->byval_arg;
6586                 else
6587                         arg_type = sig->params [i - sig->hasthis];
6588
6589                 stack_offset = ainfo->offset + ARGS_OFFSET;
6590
6591                 if (cfg->globalra) {
6592                         /* All the other moves are done by the register allocator */
6593                         switch (ainfo->storage) {
6594                         case ArgInFloatSSEReg:
6595                                 amd64_sse_cvtss2sd_reg_reg (code, ainfo->reg, ainfo->reg);
6596                                 break;
6597                         case ArgValuetypeInReg:
6598                                 for (quad = 0; quad < 2; quad ++) {
6599                                         switch (ainfo->pair_storage [quad]) {
6600                                         case ArgInIReg:
6601                                                 amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof(mgreg_t)), ainfo->pair_regs [quad], sizeof(mgreg_t));
6602                                                 break;
6603                                         case ArgInFloatSSEReg:
6604                                                 amd64_movss_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof(mgreg_t)), ainfo->pair_regs [quad]);
6605                                                 break;
6606                                         case ArgInDoubleSSEReg:
6607                                                 amd64_movsd_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof(mgreg_t)), ainfo->pair_regs [quad]);
6608                                                 break;
6609                                         case ArgNone:
6610                                                 break;
6611                                         default:
6612                                                 g_assert_not_reached ();
6613                                         }
6614                                 }
6615                                 break;
6616                         default:
6617                                 break;
6618                         }
6619
6620                         continue;
6621                 }
6622
6623                 /* Save volatile arguments to the stack */
6624                 if (ins->opcode != OP_REGVAR) {
6625                         switch (ainfo->storage) {
6626                         case ArgInIReg: {
6627                                 guint32 size = 8;
6628
6629                                 /* FIXME: I1 etc */
6630                                 /*
6631                                 if (stack_offset & 0x1)
6632                                         size = 1;
6633                                 else if (stack_offset & 0x2)
6634                                         size = 2;
6635                                 else if (stack_offset & 0x4)
6636                                         size = 4;
6637                                 else
6638                                         size = 8;
6639                                 */
6640                                 amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset, ainfo->reg, size);
6641                                 break;
6642                         }
6643                         case ArgInFloatSSEReg:
6644                                 amd64_movss_membase_reg (code, ins->inst_basereg, ins->inst_offset, ainfo->reg);
6645                                 break;
6646                         case ArgInDoubleSSEReg:
6647                                 amd64_movsd_membase_reg (code, ins->inst_basereg, ins->inst_offset, ainfo->reg);
6648                                 break;
6649                         case ArgValuetypeInReg:
6650                                 for (quad = 0; quad < 2; quad ++) {
6651                                         switch (ainfo->pair_storage [quad]) {
6652                                         case ArgInIReg:
6653                                                 amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof(mgreg_t)), ainfo->pair_regs [quad], sizeof(mgreg_t));
6654                                                 break;
6655                                         case ArgInFloatSSEReg:
6656                                                 amd64_movss_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof(mgreg_t)), ainfo->pair_regs [quad]);
6657                                                 break;
6658                                         case ArgInDoubleSSEReg:
6659                                                 amd64_movsd_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof(mgreg_t)), ainfo->pair_regs [quad]);
6660                                                 break;
6661                                         case ArgNone:
6662                                                 break;
6663                                         default:
6664                                                 g_assert_not_reached ();
6665                                         }
6666                                 }
6667                                 break;
6668                         case ArgValuetypeAddrInIReg:
6669                                 if (ainfo->pair_storage [0] == ArgInIReg)
6670                                         amd64_mov_membase_reg (code, ins->inst_left->inst_basereg, ins->inst_left->inst_offset, ainfo->pair_regs [0],  sizeof (gpointer));
6671                                 break;
6672                         default:
6673                                 break;
6674                         }
6675                 } else {
6676                         /* Argument allocated to (non-volatile) register */
6677                         switch (ainfo->storage) {
6678                         case ArgInIReg:
6679                                 amd64_mov_reg_reg (code, ins->dreg, ainfo->reg, 8);
6680                                 break;
6681                         case ArgOnStack:
6682                                 amd64_mov_reg_membase (code, ins->dreg, AMD64_RBP, ARGS_OFFSET + ainfo->offset, 8);
6683                                 break;
6684                         default:
6685                                 g_assert_not_reached ();
6686                         }
6687                 }
6688         }
6689
6690         /* Might need to attach the thread to the JIT  or change the domain for the callback */
6691         if (method->wrapper_type == MONO_WRAPPER_NATIVE_TO_MANAGED) {
6692                 guint64 domain = (guint64)cfg->domain;
6693
6694                 args_clobbered = TRUE;
6695
6696                 /*
6697                  * The call might clobber argument registers, but they are already
6698                  * saved to the stack/global regs.
6699                  */
6700                 if (appdomain_tls_offset != -1 && lmf_tls_offset != -1) {
6701                         guint8 *buf, *no_domain_branch;
6702
6703                         code = mono_amd64_emit_tls_get (code, AMD64_RAX, appdomain_tls_offset);
6704                         if (cfg->compile_aot) {
6705                                 /* AOT code is only used in the root domain */
6706                                 amd64_mov_reg_imm (code, AMD64_ARG_REG1, 0);
6707                         } else {
6708                                 if ((domain >> 32) == 0)
6709                                         amd64_mov_reg_imm_size (code, AMD64_ARG_REG1, domain, 4);
6710                                 else
6711                                         amd64_mov_reg_imm_size (code, AMD64_ARG_REG1, domain, 8);
6712                         }
6713                         amd64_alu_reg_reg (code, X86_CMP, AMD64_RAX, AMD64_ARG_REG1);
6714                         no_domain_branch = code;
6715                         x86_branch8 (code, X86_CC_NE, 0, 0);
6716                         code = mono_amd64_emit_tls_get ( code, AMD64_RAX, lmf_addr_tls_offset);
6717                         amd64_test_reg_reg (code, AMD64_RAX, AMD64_RAX);
6718                         buf = code;
6719                         x86_branch8 (code, X86_CC_NE, 0, 0);
6720                         amd64_patch (no_domain_branch, code);
6721                         code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
6722                                           (gpointer)"mono_jit_thread_attach", TRUE);
6723                         amd64_patch (buf, code);
6724 #ifdef HOST_WIN32
6725                         /* The TLS key actually contains a pointer to the MonoJitTlsData structure */
6726                         /* FIXME: Add a separate key for LMF to avoid this */
6727                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RAX, G_STRUCT_OFFSET (MonoJitTlsData, lmf));
6728 #endif
6729                 } else {
6730                         g_assert (!cfg->compile_aot);
6731                         if (cfg->compile_aot) {
6732                                 /* AOT code is only used in the root domain */
6733                                 amd64_mov_reg_imm (code, AMD64_ARG_REG1, 0);
6734                         } else {
6735                                 if ((domain >> 32) == 0)
6736                                         amd64_mov_reg_imm_size (code, AMD64_ARG_REG1, domain, 4);
6737                                 else
6738                                         amd64_mov_reg_imm_size (code, AMD64_ARG_REG1, domain, 8);
6739                         }
6740                         code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
6741                                           (gpointer)"mono_jit_thread_attach", TRUE);
6742                 }
6743         }
6744
6745         if (method->save_lmf) {
6746                 if ((lmf_tls_offset != -1) && !optimize_for_xen) {
6747                         /*
6748                          * Optimized version which uses the mono_lmf TLS variable instead of
6749                          * indirection through the mono_lmf_addr TLS variable.
6750                          */
6751                         /* %rax = previous_lmf */
6752                         x86_prefix (code, X86_FS_PREFIX);
6753                         amd64_mov_reg_mem (code, AMD64_RAX, lmf_tls_offset, 8);
6754
6755                         /* Save previous_lmf */
6756                         amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, previous_lmf), AMD64_RAX, 8);
6757                         /* Set new lmf */
6758                         if (lmf_offset == 0) {
6759                                 x86_prefix (code, X86_FS_PREFIX);
6760                                 amd64_mov_mem_reg (code, lmf_tls_offset, cfg->frame_reg, 8);
6761                         } else {
6762                                 amd64_lea_membase (code, AMD64_R11, cfg->frame_reg, lmf_offset);
6763                                 x86_prefix (code, X86_FS_PREFIX);
6764                                 amd64_mov_mem_reg (code, lmf_tls_offset, AMD64_R11, 8);
6765                         }
6766                 } else {
6767                         if (lmf_addr_tls_offset != -1) {
6768                                 /* Load lmf quicky using the FS register */
6769                                 code = mono_amd64_emit_tls_get (code, AMD64_RAX, lmf_addr_tls_offset);
6770 #ifdef HOST_WIN32
6771                                 /* The TLS key actually contains a pointer to the MonoJitTlsData structure */
6772                                 /* FIXME: Add a separate key for LMF to avoid this */
6773                                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RAX, G_STRUCT_OFFSET (MonoJitTlsData, lmf));
6774 #endif
6775                         }
6776                         else {
6777                                 /*
6778                                  * The call might clobber argument registers, but they are already
6779                                  * saved to the stack/global regs.
6780                                  */
6781                                 args_clobbered = TRUE;
6782                                 code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
6783                                                                   (gpointer)"mono_get_lmf_addr", TRUE);
6784                         }
6785
6786                         /* Save lmf_addr */
6787                         amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, lmf_addr), AMD64_RAX, sizeof(gpointer));
6788                         /* Save previous_lmf */
6789                         amd64_mov_reg_membase (code, AMD64_R11, AMD64_RAX, 0, sizeof(gpointer));
6790                         amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, previous_lmf), AMD64_R11, sizeof(gpointer));
6791                         /* Set new lmf */
6792                         amd64_lea_membase (code, AMD64_R11, cfg->frame_reg, lmf_offset);
6793                         amd64_mov_membase_reg (code, AMD64_RAX, 0, AMD64_R11, sizeof(gpointer));
6794                 }
6795         }
6796
6797         if (trace) {
6798                 args_clobbered = TRUE;
6799                 code = mono_arch_instrument_prolog (cfg, mono_trace_enter_method, code, TRUE);
6800         }
6801
6802         if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
6803                 args_clobbered = TRUE;
6804
6805         /*
6806          * Optimize the common case of the first bblock making a call with the same
6807          * arguments as the method. This works because the arguments are still in their
6808          * original argument registers.
6809          * FIXME: Generalize this
6810          */
6811         if (!args_clobbered) {
6812                 MonoBasicBlock *first_bb = cfg->bb_entry;
6813                 MonoInst *next;
6814
6815                 next = mono_bb_first_ins (first_bb);
6816                 if (!next && first_bb->next_bb) {
6817                         first_bb = first_bb->next_bb;
6818                         next = mono_bb_first_ins (first_bb);
6819                 }
6820
6821                 if (first_bb->in_count > 1)
6822                         next = NULL;
6823
6824                 for (i = 0; next && i < sig->param_count + sig->hasthis; ++i) {
6825                         ArgInfo *ainfo = cinfo->args + i;
6826                         gboolean match = FALSE;
6827
6828                         ins = cfg->args [i];
6829                         if (ins->opcode != OP_REGVAR) {
6830                                 switch (ainfo->storage) {
6831                                 case ArgInIReg: {
6832                                         if (((next->opcode == OP_LOAD_MEMBASE) || (next->opcode == OP_LOADI4_MEMBASE)) && next->inst_basereg == ins->inst_basereg && next->inst_offset == ins->inst_offset) {
6833                                                 if (next->dreg == ainfo->reg) {
6834                                                         NULLIFY_INS (next);
6835                                                         match = TRUE;
6836                                                 } else {
6837                                                         next->opcode = OP_MOVE;
6838                                                         next->sreg1 = ainfo->reg;
6839                                                         /* Only continue if the instruction doesn't change argument regs */
6840                                                         if (next->dreg == ainfo->reg || next->dreg == AMD64_RAX)
6841                                                                 match = TRUE;
6842                                                 }
6843                                         }
6844                                         break;
6845                                 }
6846                                 default:
6847                                         break;
6848                                 }
6849                         } else {
6850                                 /* Argument allocated to (non-volatile) register */
6851                                 switch (ainfo->storage) {
6852                                 case ArgInIReg:
6853                                         if (next->opcode == OP_MOVE && next->sreg1 == ins->dreg && next->dreg == ainfo->reg) {
6854                                                 NULLIFY_INS (next);
6855                                                 match = TRUE;
6856                                         }
6857                                         break;
6858                                 default:
6859                                         break;
6860                                 }
6861                         }
6862
6863                         if (match) {
6864                                 next = next->next;
6865                                 //next = mono_inst_list_next (&next->node, &first_bb->ins_list);
6866                                 if (!next)
6867                                         break;
6868                         }
6869                 }
6870         }
6871
6872         /* Initialize ss_trigger_page_var */
6873         if (cfg->arch.ss_trigger_page_var) {
6874                 MonoInst *var = cfg->arch.ss_trigger_page_var;
6875
6876                 g_assert (!cfg->compile_aot);
6877                 g_assert (var->opcode == OP_REGOFFSET);
6878
6879                 amd64_mov_reg_imm (code, AMD64_R11, (guint64)ss_trigger_page);
6880                 amd64_mov_membase_reg (code, var->inst_basereg, var->inst_offset, AMD64_R11, 8);
6881         }
6882
6883         cfg->code_len = code - cfg->native_code;
6884
6885         g_assert (cfg->code_len < cfg->code_size);
6886
6887         return code;
6888 }
6889
6890 void
6891 mono_arch_emit_epilog (MonoCompile *cfg)
6892 {
6893         MonoMethod *method = cfg->method;
6894         int quad, pos, i;
6895         guint8 *code;
6896         int max_epilog_size;
6897         CallInfo *cinfo;
6898         gint32 lmf_offset = cfg->arch.lmf_offset;
6899
6900         max_epilog_size = get_max_epilog_size (cfg);
6901
6902         while (cfg->code_len + max_epilog_size > (cfg->code_size - 16)) {
6903                 cfg->code_size *= 2;
6904                 cfg->native_code = mono_realloc_native_code (cfg);
6905                 mono_jit_stats.code_reallocs++;
6906         }
6907
6908         code = cfg->native_code + cfg->code_len;
6909
6910         if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
6911                 code = mono_arch_instrument_epilog (cfg, mono_trace_leave_method, code, TRUE);
6912
6913         /* the code restoring the registers must be kept in sync with OP_JMP */
6914         pos = 0;
6915
6916         if (method->save_lmf) {
6917                 /* check if we need to restore protection of the stack after a stack overflow */
6918                 if (mono_get_jit_tls_offset () != -1) {
6919                         guint8 *patch;
6920                         code = mono_amd64_emit_tls_get (code, X86_ECX, mono_get_jit_tls_offset ());
6921                         /* we load the value in a separate instruction: this mechanism may be
6922                          * used later as a safer way to do thread interruption
6923                          */
6924                         amd64_mov_reg_membase (code, X86_ECX, X86_ECX, G_STRUCT_OFFSET (MonoJitTlsData, restore_stack_prot), 8);
6925                         x86_alu_reg_imm (code, X86_CMP, X86_ECX, 0);
6926                         patch = code;
6927                         x86_branch8 (code, X86_CC_Z, 0, FALSE);
6928                         /* note that the call trampoline will preserve eax/edx */
6929                         x86_call_reg (code, X86_ECX);
6930                         x86_patch (patch, code);
6931                 } else {
6932                         /* FIXME: maybe save the jit tls in the prolog */
6933                 }
6934                 if ((lmf_tls_offset != -1) && !optimize_for_xen) {
6935                         /*
6936                          * Optimized version which uses the mono_lmf TLS variable instead of indirection
6937                          * through the mono_lmf_addr TLS variable.
6938                          */
6939                         /* reg = previous_lmf */
6940                         amd64_mov_reg_membase (code, AMD64_R11, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, previous_lmf), sizeof(gpointer));
6941                         x86_prefix (code, X86_FS_PREFIX);
6942                         amd64_mov_mem_reg (code, lmf_tls_offset, AMD64_R11, 8);
6943                 } else {
6944                         /* Restore previous lmf */
6945                         amd64_mov_reg_membase (code, AMD64_RCX, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, previous_lmf), sizeof(gpointer));
6946                         amd64_mov_reg_membase (code, AMD64_R11, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, lmf_addr), sizeof(gpointer));
6947                         amd64_mov_membase_reg (code, AMD64_R11, 0, AMD64_RCX, sizeof(gpointer));
6948                 }
6949
6950                 /* Restore caller saved regs */
6951                 if (cfg->used_int_regs & (1 << AMD64_RBP)) {
6952                         amd64_mov_reg_membase (code, AMD64_RBP, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, rbp), 8);
6953                 }
6954                 if (cfg->used_int_regs & (1 << AMD64_RBX)) {
6955                         amd64_mov_reg_membase (code, AMD64_RBX, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, rbx), 8);
6956                 }
6957                 if (cfg->used_int_regs & (1 << AMD64_R12)) {
6958                         amd64_mov_reg_membase (code, AMD64_R12, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, r12), 8);
6959                 }
6960                 if (cfg->used_int_regs & (1 << AMD64_R13)) {
6961                         amd64_mov_reg_membase (code, AMD64_R13, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, r13), 8);
6962                 }
6963                 if (cfg->used_int_regs & (1 << AMD64_R14)) {
6964                         amd64_mov_reg_membase (code, AMD64_R14, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, r14), 8);
6965                 }
6966                 if (cfg->used_int_regs & (1 << AMD64_R15)) {
6967 #if defined(__default_codegen__)
6968                         amd64_mov_reg_membase (code, AMD64_R15, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, r15), 8);
6969 #elif defined(__native_client_codegen__)
6970                         g_assert_not_reached();
6971 #endif
6972                 }
6973 #ifdef HOST_WIN32
6974                 if (cfg->used_int_regs & (1 << AMD64_RDI)) {
6975                         amd64_mov_reg_membase (code, AMD64_RDI, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, rdi), 8);
6976                 }
6977                 if (cfg->used_int_regs & (1 << AMD64_RSI)) {
6978                         amd64_mov_reg_membase (code, AMD64_RSI, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, rsi), 8);
6979                 }
6980 #endif
6981         } else {
6982
6983                 if (cfg->arch.omit_fp) {
6984                         gint32 save_area_offset = cfg->arch.reg_save_area_offset;
6985
6986                         for (i = 0; i < AMD64_NREG; ++i)
6987                                 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
6988                                         amd64_mov_reg_membase (code, i, AMD64_RSP, save_area_offset, 8);
6989                                         save_area_offset += 8;
6990                                 }
6991                 }
6992                 else {
6993                         for (i = 0; i < AMD64_NREG; ++i)
6994                                 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i)))
6995                                         pos -= sizeof(mgreg_t);
6996
6997                         if (pos) {
6998                                 if (pos == - sizeof(mgreg_t)) {
6999                                         /* Only one register, so avoid lea */
7000                                         for (i = AMD64_NREG - 1; i > 0; --i)
7001                                                 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
7002                                                         amd64_mov_reg_membase (code, i, AMD64_RBP, pos, 8);
7003                                                 }
7004                                 }
7005                                 else {
7006                                         amd64_lea_membase (code, AMD64_RSP, AMD64_RBP, pos);
7007
7008                                         /* Pop registers in reverse order */
7009                                         for (i = AMD64_NREG - 1; i > 0; --i)
7010                                                 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
7011                                                         amd64_pop_reg (code, i);
7012                                                 }
7013                                 }
7014                         }
7015                 }
7016         }
7017
7018         /* Load returned vtypes into registers if needed */
7019         cinfo = cfg->arch.cinfo;
7020         if (cinfo->ret.storage == ArgValuetypeInReg) {
7021                 ArgInfo *ainfo = &cinfo->ret;
7022                 MonoInst *inst = cfg->ret;
7023
7024                 for (quad = 0; quad < 2; quad ++) {
7025                         switch (ainfo->pair_storage [quad]) {
7026                         case ArgInIReg:
7027                                 amd64_mov_reg_membase (code, ainfo->pair_regs [quad], inst->inst_basereg, inst->inst_offset + (quad * sizeof(mgreg_t)), sizeof(mgreg_t));
7028                                 break;
7029                         case ArgInFloatSSEReg:
7030                                 amd64_movss_reg_membase (code, ainfo->pair_regs [quad], inst->inst_basereg, inst->inst_offset + (quad * sizeof(mgreg_t)));
7031                                 break;
7032                         case ArgInDoubleSSEReg:
7033                                 amd64_movsd_reg_membase (code, ainfo->pair_regs [quad], inst->inst_basereg, inst->inst_offset + (quad * sizeof(mgreg_t)));
7034                                 break;
7035                         case ArgNone:
7036                                 break;
7037                         default:
7038                                 g_assert_not_reached ();
7039                         }
7040                 }
7041         }
7042
7043         if (cfg->arch.omit_fp) {
7044                 if (cfg->arch.stack_alloc_size)
7045                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, cfg->arch.stack_alloc_size);
7046         } else {
7047                 amd64_leave (code);
7048         }
7049         async_exc_point (code);
7050         amd64_ret (code);
7051
7052         cfg->code_len = code - cfg->native_code;
7053
7054         g_assert (cfg->code_len < cfg->code_size);
7055 }
7056
7057 void
7058 mono_arch_emit_exceptions (MonoCompile *cfg)
7059 {
7060         MonoJumpInfo *patch_info;
7061         int nthrows, i;
7062         guint8 *code;
7063         MonoClass *exc_classes [16];
7064         guint8 *exc_throw_start [16], *exc_throw_end [16];
7065         guint32 code_size = 0;
7066
7067         /* Compute needed space */
7068         for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
7069                 if (patch_info->type == MONO_PATCH_INFO_EXC)
7070                         code_size += 40;
7071                 if (patch_info->type == MONO_PATCH_INFO_R8)
7072                         code_size += 8 + 15; /* sizeof (double) + alignment */
7073                 if (patch_info->type == MONO_PATCH_INFO_R4)
7074                         code_size += 4 + 15; /* sizeof (float) + alignment */
7075                 if (patch_info->type == MONO_PATCH_INFO_GC_CARD_TABLE_ADDR)
7076                         code_size += 8 + 7; /*sizeof (void*) + alignment */
7077         }
7078
7079 #ifdef __native_client_codegen__
7080         /* Give us extra room on Native Client.  This could be   */
7081         /* more carefully calculated, but bundle alignment makes */
7082         /* it much trickier, so *2 like other places is good.    */
7083         code_size *= 2;
7084 #endif
7085
7086         while (cfg->code_len + code_size > (cfg->code_size - 16)) {
7087                 cfg->code_size *= 2;
7088                 cfg->native_code = mono_realloc_native_code (cfg);
7089                 mono_jit_stats.code_reallocs++;
7090         }
7091
7092         code = cfg->native_code + cfg->code_len;
7093
7094         /* add code to raise exceptions */
7095         nthrows = 0;
7096         for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
7097                 switch (patch_info->type) {
7098                 case MONO_PATCH_INFO_EXC: {
7099                         MonoClass *exc_class;
7100                         guint8 *buf, *buf2;
7101                         guint32 throw_ip;
7102
7103                         amd64_patch (patch_info->ip.i + cfg->native_code, code);
7104
7105                         exc_class = mono_class_from_name (mono_defaults.corlib, "System", patch_info->data.name);
7106                         g_assert (exc_class);
7107                         throw_ip = patch_info->ip.i;
7108
7109                         //x86_breakpoint (code);
7110                         /* Find a throw sequence for the same exception class */
7111                         for (i = 0; i < nthrows; ++i)
7112                                 if (exc_classes [i] == exc_class)
7113                                         break;
7114                         if (i < nthrows) {
7115                                 amd64_mov_reg_imm (code, AMD64_ARG_REG2, (exc_throw_end [i] - cfg->native_code) - throw_ip);
7116                                 x86_jump_code (code, exc_throw_start [i]);
7117                                 patch_info->type = MONO_PATCH_INFO_NONE;
7118                         }
7119                         else {
7120                                 buf = code;
7121                                 amd64_mov_reg_imm_size (code, AMD64_ARG_REG2, 0xf0f0f0f0, 4);
7122                                 buf2 = code;
7123
7124                                 if (nthrows < 16) {
7125                                         exc_classes [nthrows] = exc_class;
7126                                         exc_throw_start [nthrows] = code;
7127                                 }
7128                                 amd64_mov_reg_imm (code, AMD64_ARG_REG1, exc_class->type_token - MONO_TOKEN_TYPE_DEF);
7129
7130                                 patch_info->type = MONO_PATCH_INFO_NONE;
7131
7132                                 code = emit_call_body (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD, "mono_arch_throw_corlib_exception");
7133
7134                                 amd64_mov_reg_imm (buf, AMD64_ARG_REG2, (code - cfg->native_code) - throw_ip);
7135                                 while (buf < buf2)
7136                                         x86_nop (buf);
7137
7138                                 if (nthrows < 16) {
7139                                         exc_throw_end [nthrows] = code;
7140                                         nthrows ++;
7141                                 }
7142                         }
7143                         break;
7144                 }
7145                 default:
7146                         /* do nothing */
7147                         break;
7148                 }
7149                 g_assert(code < cfg->native_code + cfg->code_size);
7150         }
7151
7152         /* Handle relocations with RIP relative addressing */
7153         for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
7154                 gboolean remove = FALSE;
7155                 guint8 *orig_code = code;
7156
7157                 switch (patch_info->type) {
7158                 case MONO_PATCH_INFO_R8:
7159                 case MONO_PATCH_INFO_R4: {
7160                         guint8 *pos, *patch_pos, *target_pos;
7161
7162                         /* The SSE opcodes require a 16 byte alignment */
7163 #if defined(__default_codegen__)
7164                         code = (guint8*)ALIGN_TO (code, 16);
7165 #elif defined(__native_client_codegen__)
7166                         {
7167                                 /* Pad this out with HLT instructions  */
7168                                 /* or we can get garbage bytes emitted */
7169                                 /* which will fail validation          */
7170                                 guint8 *aligned_code;
7171                                 /* extra align to make room for  */
7172                                 /* mov/push below                      */
7173                                 int extra_align = patch_info->type == MONO_PATCH_INFO_R8 ? 2 : 1;
7174                                 aligned_code = (guint8*)ALIGN_TO (code + extra_align, 16);
7175                                 /* The technique of hiding data in an  */
7176                                 /* instruction has a problem here: we  */
7177                                 /* need the data aligned to a 16-byte  */
7178                                 /* boundary but the instruction cannot */
7179                                 /* cross the bundle boundary. so only  */
7180                                 /* odd multiples of 16 can be used     */
7181                                 if ((intptr_t)aligned_code % kNaClAlignment == 0) {
7182                                         aligned_code += 16;
7183                                 }
7184                                 while (code < aligned_code) {
7185                                         *(code++) = 0xf4; /* hlt */
7186                                 }
7187                         }
7188 #endif
7189
7190                         pos = cfg->native_code + patch_info->ip.i;
7191                         if (IS_REX (pos [1])) {
7192                                 patch_pos = pos + 5;
7193                                 target_pos = code - pos - 9;
7194                         }
7195                         else {
7196                                 patch_pos = pos + 4;
7197                                 target_pos = code - pos - 8;
7198                         }
7199
7200                         if (patch_info->type == MONO_PATCH_INFO_R8) {
7201 #ifdef __native_client_codegen__
7202                                 /* Hide 64-bit data in a         */
7203                                 /* "mov imm64, r11" instruction. */
7204                                 /* write it before the start of  */
7205                                 /* the data*/
7206                                 *(code-2) = 0x49; /* prefix      */
7207                                 *(code-1) = 0xbb; /* mov X, %r11 */
7208 #endif
7209                                 *(double*)code = *(double*)patch_info->data.target;
7210                                 code += sizeof (double);
7211                         } else {
7212 #ifdef __native_client_codegen__
7213                                 /* Hide 32-bit data in a        */
7214                                 /* "push imm32" instruction.    */
7215                                 *(code-1) = 0x68; /* push */
7216 #endif
7217                                 *(float*)code = *(float*)patch_info->data.target;
7218                                 code += sizeof (float);
7219                         }
7220
7221                         *(guint32*)(patch_pos) = target_pos;
7222
7223                         remove = TRUE;
7224                         break;
7225                 }
7226                 case MONO_PATCH_INFO_GC_CARD_TABLE_ADDR: {
7227                         guint8 *pos;
7228
7229                         if (cfg->compile_aot)
7230                                 continue;
7231
7232                         /*loading is faster against aligned addresses.*/
7233                         code = (guint8*)ALIGN_TO (code, 8);
7234                         memset (orig_code, 0, code - orig_code);
7235
7236                         pos = cfg->native_code + patch_info->ip.i;
7237
7238                         /*alu_op [rex] modr/m imm32 - 7 or 8 bytes */
7239                         if (IS_REX (pos [1]))
7240                                 *(guint32*)(pos + 4) = (guint8*)code - pos - 8;
7241                         else
7242                                 *(guint32*)(pos + 3) = (guint8*)code - pos - 7;
7243
7244                         *(gpointer*)code = (gpointer)patch_info->data.target;
7245                         code += sizeof (gpointer);
7246
7247                         remove = TRUE;
7248                         break;
7249                 }
7250                 default:
7251                         break;
7252                 }
7253
7254                 if (remove) {
7255                         if (patch_info == cfg->patch_info)
7256                                 cfg->patch_info = patch_info->next;
7257                         else {
7258                                 MonoJumpInfo *tmp;
7259
7260                                 for (tmp = cfg->patch_info; tmp->next != patch_info; tmp = tmp->next)
7261                                         ;
7262                                 tmp->next = patch_info->next;
7263                         }
7264                 }
7265                 g_assert (code < cfg->native_code + cfg->code_size);
7266         }
7267
7268         cfg->code_len = code - cfg->native_code;
7269
7270         g_assert (cfg->code_len < cfg->code_size);
7271
7272 }
7273
7274 #endif /* DISABLE_JIT */
7275
7276 void*
7277 mono_arch_instrument_prolog (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments)
7278 {
7279         guchar *code = p;
7280         CallInfo *cinfo = NULL;
7281         MonoMethodSignature *sig;
7282         MonoInst *inst;
7283         int i, n, stack_area = 0;
7284
7285         /* Keep this in sync with mono_arch_get_argument_info */
7286
7287         if (enable_arguments) {
7288                 /* Allocate a new area on the stack and save arguments there */
7289                 sig = mono_method_signature (cfg->method);
7290
7291                 cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig);
7292
7293                 n = sig->param_count + sig->hasthis;
7294
7295                 stack_area = ALIGN_TO (n * 8, 16);
7296
7297                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, stack_area);
7298
7299                 for (i = 0; i < n; ++i) {
7300                         inst = cfg->args [i];
7301
7302                         if (inst->opcode == OP_REGVAR)
7303                                 amd64_mov_membase_reg (code, AMD64_RSP, (i * 8), inst->dreg, 8);
7304                         else {
7305                                 amd64_mov_reg_membase (code, AMD64_R11, inst->inst_basereg, inst->inst_offset, 8);
7306                                 amd64_mov_membase_reg (code, AMD64_RSP, (i * 8), AMD64_R11, 8);
7307                         }
7308                 }
7309         }
7310
7311         mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_METHODCONST, cfg->method);
7312         amd64_set_reg_template (code, AMD64_ARG_REG1);
7313         amd64_mov_reg_reg (code, AMD64_ARG_REG2, AMD64_RSP, 8);
7314         code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, (gpointer)func, TRUE);
7315
7316         if (enable_arguments)
7317                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, stack_area);
7318
7319         return code;
7320 }
7321
7322 enum {
7323         SAVE_NONE,
7324         SAVE_STRUCT,
7325         SAVE_EAX,
7326         SAVE_EAX_EDX,
7327         SAVE_XMM
7328 };
7329
7330 void*
7331 mono_arch_instrument_epilog_full (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments, gboolean preserve_argument_registers)
7332 {
7333         guchar *code = p;
7334         int save_mode = SAVE_NONE;
7335         MonoMethod *method = cfg->method;
7336         MonoType *ret_type = mini_type_get_underlying_type (NULL, mono_method_signature (method)->ret);
7337
7338         switch (ret_type->type) {
7339         case MONO_TYPE_VOID:
7340                 /* special case string .ctor icall */
7341                 if (strcmp (".ctor", method->name) && method->klass == mono_defaults.string_class)
7342                         save_mode = SAVE_EAX;
7343                 else
7344                         save_mode = SAVE_NONE;
7345                 break;
7346         case MONO_TYPE_I8:
7347         case MONO_TYPE_U8:
7348                 save_mode = SAVE_EAX;
7349                 break;
7350         case MONO_TYPE_R4:
7351         case MONO_TYPE_R8:
7352                 save_mode = SAVE_XMM;
7353                 break;
7354         case MONO_TYPE_GENERICINST:
7355                 if (!mono_type_generic_inst_is_valuetype (ret_type)) {
7356                         save_mode = SAVE_EAX;
7357                         break;
7358                 }
7359                 /* Fall through */
7360         case MONO_TYPE_VALUETYPE:
7361                 save_mode = SAVE_STRUCT;
7362                 break;
7363         default:
7364                 save_mode = SAVE_EAX;
7365                 break;
7366         }
7367
7368         /* Save the result and copy it into the proper argument register */
7369         switch (save_mode) {
7370         case SAVE_EAX:
7371                 amd64_push_reg (code, AMD64_RAX);
7372                 /* Align stack */
7373                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
7374                 if (enable_arguments)
7375                         amd64_mov_reg_reg (code, AMD64_ARG_REG2, AMD64_RAX, 8);
7376                 break;
7377         case SAVE_STRUCT:
7378                 /* FIXME: */
7379                 if (enable_arguments)
7380                         amd64_mov_reg_imm (code, AMD64_ARG_REG2, 0);
7381                 break;
7382         case SAVE_XMM:
7383                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
7384                 amd64_movsd_membase_reg (code, AMD64_RSP, 0, AMD64_XMM0);
7385                 /* Align stack */
7386                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
7387                 /*
7388                  * The result is already in the proper argument register so no copying
7389                  * needed.
7390                  */
7391                 break;
7392         case SAVE_NONE:
7393                 break;
7394         default:
7395                 g_assert_not_reached ();
7396         }
7397
7398         /* Set %al since this is a varargs call */
7399         if (save_mode == SAVE_XMM)
7400                 amd64_mov_reg_imm (code, AMD64_RAX, 1);
7401         else
7402                 amd64_mov_reg_imm (code, AMD64_RAX, 0);
7403
7404         if (preserve_argument_registers) {
7405                 amd64_push_reg (code, MONO_AMD64_ARG_REG1);
7406                 amd64_push_reg (code, MONO_AMD64_ARG_REG2);
7407         }
7408
7409         mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_METHODCONST, method);
7410         amd64_set_reg_template (code, AMD64_ARG_REG1);
7411         code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, (gpointer)func, TRUE);
7412
7413         if (preserve_argument_registers) {
7414                 amd64_pop_reg (code, MONO_AMD64_ARG_REG2);
7415                 amd64_pop_reg (code, MONO_AMD64_ARG_REG1);
7416         }
7417
7418         /* Restore result */
7419         switch (save_mode) {
7420         case SAVE_EAX:
7421                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
7422                 amd64_pop_reg (code, AMD64_RAX);
7423                 break;
7424         case SAVE_STRUCT:
7425                 /* FIXME: */
7426                 break;
7427         case SAVE_XMM:
7428                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
7429                 amd64_movsd_reg_membase (code, AMD64_XMM0, AMD64_RSP, 0);
7430                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
7431                 break;
7432         case SAVE_NONE:
7433                 break;
7434         default:
7435                 g_assert_not_reached ();
7436         }
7437
7438         return code;
7439 }
7440
7441 void
7442 mono_arch_flush_icache (guint8 *code, gint size)
7443 {
7444         /* Not needed */
7445 }
7446
7447 void
7448 mono_arch_flush_register_windows (void)
7449 {
7450 }
7451
7452 gboolean
7453 mono_arch_is_inst_imm (gint64 imm)
7454 {
7455         return amd64_is_imm32 (imm);
7456 }
7457
7458 /*
7459  * Determine whenever the trap whose info is in SIGINFO is caused by
7460  * integer overflow.
7461  */
7462 gboolean
7463 mono_arch_is_int_overflow (void *sigctx, void *info)
7464 {
7465         MonoContext ctx;
7466         guint8* rip;
7467         int reg;
7468         gint64 value;
7469
7470         mono_arch_sigctx_to_monoctx (sigctx, &ctx);
7471
7472         rip = (guint8*)ctx.rip;
7473
7474         if (IS_REX (rip [0])) {
7475                 reg = amd64_rex_b (rip [0]);
7476                 rip ++;
7477         }
7478         else
7479                 reg = 0;
7480
7481         if ((rip [0] == 0xf7) && (x86_modrm_mod (rip [1]) == 0x3) && (x86_modrm_reg (rip [1]) == 0x7)) {
7482                 /* idiv REG */
7483                 reg += x86_modrm_rm (rip [1]);
7484
7485                 switch (reg) {
7486                 case AMD64_RAX:
7487                         value = ctx.rax;
7488                         break;
7489                 case AMD64_RBX:
7490                         value = ctx.rbx;
7491                         break;
7492                 case AMD64_RCX:
7493                         value = ctx.rcx;
7494                         break;
7495                 case AMD64_RDX:
7496                         value = ctx.rdx;
7497                         break;
7498                 case AMD64_RBP:
7499                         value = ctx.rbp;
7500                         break;
7501                 case AMD64_RSP:
7502                         value = ctx.rsp;
7503                         break;
7504                 case AMD64_RSI:
7505                         value = ctx.rsi;
7506                         break;
7507                 case AMD64_RDI:
7508                         value = ctx.rdi;
7509                         break;
7510                 case AMD64_R12:
7511                         value = ctx.r12;
7512                         break;
7513                 case AMD64_R13:
7514                         value = ctx.r13;
7515                         break;
7516                 case AMD64_R14:
7517                         value = ctx.r14;
7518                         break;
7519                 case AMD64_R15:
7520                         value = ctx.r15;
7521                         break;
7522                 default:
7523                         g_assert_not_reached ();
7524                         reg = -1;
7525                 }
7526
7527                 if (value == -1)
7528                         return TRUE;
7529         }
7530
7531         return FALSE;
7532 }
7533
7534 guint32
7535 mono_arch_get_patch_offset (guint8 *code)
7536 {
7537         return 3;
7538 }
7539
7540 /**
7541  * mono_breakpoint_clean_code:
7542  *
7543  * Copy @size bytes from @code - @offset to the buffer @buf. If the debugger inserted software
7544  * breakpoints in the original code, they are removed in the copy.
7545  *
7546  * Returns TRUE if no sw breakpoint was present.
7547  */
7548 gboolean
7549 mono_breakpoint_clean_code (guint8 *method_start, guint8 *code, int offset, guint8 *buf, int size)
7550 {
7551         int i;
7552         gboolean can_write = TRUE;
7553         /*
7554          * If method_start is non-NULL we need to perform bound checks, since we access memory
7555          * at code - offset we could go before the start of the method and end up in a different
7556          * page of memory that is not mapped or read incorrect data anyway. We zero-fill the bytes
7557          * instead.
7558          */
7559         if (!method_start || code - offset >= method_start) {
7560                 memcpy (buf, code - offset, size);
7561         } else {
7562                 int diff = code - method_start;
7563                 memset (buf, 0, size);
7564                 memcpy (buf + offset - diff, method_start, diff + size - offset);
7565         }
7566         code -= offset;
7567         for (i = 0; i < MONO_BREAKPOINT_ARRAY_SIZE; ++i) {
7568                 int idx = mono_breakpoint_info_index [i];
7569                 guint8 *ptr;
7570                 if (idx < 1)
7571                         continue;
7572                 ptr = mono_breakpoint_info [idx].address;
7573                 if (ptr >= code && ptr < code + size) {
7574                         guint8 saved_byte = mono_breakpoint_info [idx].saved_byte;
7575                         can_write = FALSE;
7576                         /*g_print ("patching %p with 0x%02x (was: 0x%02x)\n", ptr, saved_byte, buf [ptr - code]);*/
7577                         buf [ptr - code] = saved_byte;
7578                 }
7579         }
7580         return can_write;
7581 }
7582
7583 #if defined(__native_client_codegen__)
7584 /* For membase calls, we want the base register. for Native Client,  */
7585 /* all indirect calls have the following sequence with the given sizes: */
7586 /* mov %eXX,%eXX                                [2-3]   */
7587 /* mov disp(%r15,%rXX,scale),%r11d              [4-8]   */
7588 /* and $0xffffffffffffffe0,%r11d                [4]     */
7589 /* add %r15,%r11                                [3]     */
7590 /* callq *%r11                                  [3]     */
7591
7592
7593 /* Determine if code points to a NaCl call-through-register sequence, */
7594 /* (i.e., the last 3 instructions listed above) */
7595 int
7596 is_nacl_call_reg_sequence(guint8* code)
7597 {
7598         const char *sequence = "\x41\x83\xe3\xe0" /* and */
7599                                "\x4d\x03\xdf"     /* add */
7600                                "\x41\xff\xd3";   /* call */
7601         return memcmp(code, sequence, 10) == 0;
7602 }
7603
7604 /* Determine if code points to the first opcode of the mov membase component */
7605 /* of an indirect call sequence (i.e. the first 2 instructions listed above) */
7606 /* (there could be a REX prefix before the opcode but it is ignored) */
7607 static int
7608 is_nacl_indirect_call_membase_sequence(guint8* code)
7609 {
7610                /* Check for mov opcode, reg-reg addressing mode (mod = 3), */
7611         return code[0] == 0x8b && amd64_modrm_mod(code[1]) == 3 &&
7612                /* and that src reg = dest reg */
7613                amd64_modrm_reg(code[1]) == amd64_modrm_rm(code[1]) &&
7614                /* Check that next inst is mov, uses SIB byte (rm = 4), */
7615                IS_REX(code[2]) &&
7616                code[3] == 0x8b && amd64_modrm_rm(code[4]) == 4 &&
7617                /* and has dst of r11 and base of r15 */
7618                (amd64_modrm_reg(code[4]) + amd64_rex_r(code[2])) == AMD64_R11 &&
7619                (amd64_sib_base(code[5]) + amd64_rex_b(code[2])) == AMD64_R15;
7620 }
7621 #endif /* __native_client_codegen__ */
7622
7623 int
7624 mono_arch_get_this_arg_reg (guint8 *code)
7625 {
7626         return AMD64_ARG_REG1;
7627 }
7628
7629 gpointer
7630 mono_arch_get_this_arg_from_call (mgreg_t *regs, guint8 *code)
7631 {
7632         return (gpointer)regs [mono_arch_get_this_arg_reg (code)];
7633 }
7634
7635 #define MAX_ARCH_DELEGATE_PARAMS 10
7636
7637 static gpointer
7638 get_delegate_invoke_impl (gboolean has_target, guint32 param_count, guint32 *code_len)
7639 {
7640         guint8 *code, *start;
7641         int i;
7642
7643         if (has_target) {
7644                 start = code = mono_global_codeman_reserve (64);
7645
7646                 /* Replace the this argument with the target */
7647                 amd64_mov_reg_reg (code, AMD64_RAX, AMD64_ARG_REG1, 8);
7648                 amd64_mov_reg_membase (code, AMD64_ARG_REG1, AMD64_RAX, G_STRUCT_OFFSET (MonoDelegate, target), 8);
7649                 amd64_jump_membase (code, AMD64_RAX, G_STRUCT_OFFSET (MonoDelegate, method_ptr));
7650
7651                 g_assert ((code - start) < 64);
7652         } else {
7653                 start = code = mono_global_codeman_reserve (64);
7654
7655                 if (param_count == 0) {
7656                         amd64_jump_membase (code, AMD64_ARG_REG1, G_STRUCT_OFFSET (MonoDelegate, method_ptr));
7657                 } else {
7658                         /* We have to shift the arguments left */
7659                         amd64_mov_reg_reg (code, AMD64_RAX, AMD64_ARG_REG1, 8);
7660                         for (i = 0; i < param_count; ++i) {
7661 #ifdef HOST_WIN32
7662                                 if (i < 3)
7663                                         amd64_mov_reg_reg (code, param_regs [i], param_regs [i + 1], 8);
7664                                 else
7665                                         amd64_mov_reg_membase (code, param_regs [i], AMD64_RSP, 0x28, 8);
7666 #else
7667                                 amd64_mov_reg_reg (code, param_regs [i], param_regs [i + 1], 8);
7668 #endif
7669                         }
7670
7671                         amd64_jump_membase (code, AMD64_RAX, G_STRUCT_OFFSET (MonoDelegate, method_ptr));
7672                 }
7673                 g_assert ((code - start) < 64);
7674         }
7675
7676         nacl_global_codeman_validate(&start, 64, &code);
7677
7678         mono_debug_add_delegate_trampoline (start, code - start);
7679
7680         if (code_len)
7681                 *code_len = code - start;
7682
7683
7684         if (mono_jit_map_is_enabled ()) {
7685                 char *buff;
7686                 if (has_target)
7687                         buff = (char*)"delegate_invoke_has_target";
7688                 else
7689                         buff = g_strdup_printf ("delegate_invoke_no_target_%d", param_count);
7690                 mono_emit_jit_tramp (start, code - start, buff);
7691                 if (!has_target)
7692                         g_free (buff);
7693         }
7694
7695         return start;
7696 }
7697
7698 /*
7699  * mono_arch_get_delegate_invoke_impls:
7700  *
7701  *   Return a list of MonoTrampInfo structures for the delegate invoke impl
7702  * trampolines.
7703  */
7704 GSList*
7705 mono_arch_get_delegate_invoke_impls (void)
7706 {
7707         GSList *res = NULL;
7708         guint8 *code;
7709         guint32 code_len;
7710         int i;
7711
7712         code = get_delegate_invoke_impl (TRUE, 0, &code_len);
7713         res = g_slist_prepend (res, mono_tramp_info_create (g_strdup ("delegate_invoke_impl_has_target"), code, code_len, NULL, NULL));
7714
7715         for (i = 0; i < MAX_ARCH_DELEGATE_PARAMS; ++i) {
7716                 code = get_delegate_invoke_impl (FALSE, i, &code_len);
7717                 res = g_slist_prepend (res, mono_tramp_info_create (g_strdup_printf ("delegate_invoke_impl_target_%d", i), code, code_len, NULL, NULL));
7718         }
7719
7720         return res;
7721 }
7722
7723 gpointer
7724 mono_arch_get_delegate_invoke_impl (MonoMethodSignature *sig, gboolean has_target)
7725 {
7726         guint8 *code, *start;
7727         int i;
7728
7729         if (sig->param_count > MAX_ARCH_DELEGATE_PARAMS)
7730                 return NULL;
7731
7732         /* FIXME: Support more cases */
7733         if (MONO_TYPE_ISSTRUCT (sig->ret))
7734                 return NULL;
7735
7736         if (has_target) {
7737                 static guint8* cached = NULL;
7738
7739                 if (cached)
7740                         return cached;
7741
7742                 if (mono_aot_only)
7743                         start = mono_aot_get_trampoline ("delegate_invoke_impl_has_target");
7744                 else
7745                         start = get_delegate_invoke_impl (TRUE, 0, NULL);
7746
7747                 mono_memory_barrier ();
7748
7749                 cached = start;
7750         } else {
7751                 static guint8* cache [MAX_ARCH_DELEGATE_PARAMS + 1] = {NULL};
7752                 for (i = 0; i < sig->param_count; ++i)
7753                         if (!mono_is_regsize_var (sig->params [i]))
7754                                 return NULL;
7755                 if (sig->param_count > 4)
7756                         return NULL;
7757
7758                 code = cache [sig->param_count];
7759                 if (code)
7760                         return code;
7761
7762                 if (mono_aot_only) {
7763                         char *name = g_strdup_printf ("delegate_invoke_impl_target_%d", sig->param_count);
7764                         start = mono_aot_get_trampoline (name);
7765                         g_free (name);
7766                 } else {
7767                         start = get_delegate_invoke_impl (FALSE, sig->param_count, NULL);
7768                 }
7769
7770                 mono_memory_barrier ();
7771
7772                 cache [sig->param_count] = start;
7773         }
7774
7775         return start;
7776 }
7777
7778 /*
7779  * Support for fast access to the thread-local lmf structure using the GS
7780  * segment register on NPTL + kernel 2.6.x.
7781  */
7782
7783 static gboolean tls_offset_inited = FALSE;
7784
7785 void
7786 mono_arch_setup_jit_tls_data (MonoJitTlsData *tls)
7787 {
7788         if (!tls_offset_inited) {
7789 #ifdef HOST_WIN32
7790                 /*
7791                  * We need to init this multiple times, since when we are first called, the key might not
7792                  * be initialized yet.
7793                  */
7794                 appdomain_tls_offset = mono_domain_get_tls_key ();
7795                 lmf_tls_offset = mono_get_jit_tls_key ();
7796                 lmf_addr_tls_offset = mono_get_jit_tls_key ();
7797
7798                 /* Only 64 tls entries can be accessed using inline code */
7799                 if (appdomain_tls_offset >= 64)
7800                         appdomain_tls_offset = -1;
7801                 if (lmf_tls_offset >= 64)
7802                         lmf_tls_offset = -1;
7803 #else
7804                 tls_offset_inited = TRUE;
7805 #ifdef MONO_XEN_OPT
7806                 optimize_for_xen = access ("/proc/xen", F_OK) == 0;
7807 #endif
7808                 appdomain_tls_offset = mono_domain_get_tls_offset ();
7809                 lmf_tls_offset = mono_get_lmf_tls_offset ();
7810                 lmf_addr_tls_offset = mono_get_lmf_addr_tls_offset ();
7811 #endif
7812         }
7813 }
7814
7815 void
7816 mono_arch_free_jit_tls_data (MonoJitTlsData *tls)
7817 {
7818 }
7819
7820 #ifdef MONO_ARCH_HAVE_IMT
7821
7822 #if defined(__default_codegen__)
7823 #define CMP_SIZE (6 + 1)
7824 #define CMP_REG_REG_SIZE (4 + 1)
7825 #define BR_SMALL_SIZE 2
7826 #define BR_LARGE_SIZE 6
7827 #define MOV_REG_IMM_SIZE 10
7828 #define MOV_REG_IMM_32BIT_SIZE 6
7829 #define JUMP_REG_SIZE (2 + 1)
7830 #elif defined(__native_client_codegen__)
7831 /* NaCl N-byte instructions can be padded up to N-1 bytes */
7832 #define CMP_SIZE ((6 + 1) * 2 - 1)
7833 #define CMP_REG_REG_SIZE ((4 + 1) * 2 - 1)
7834 #define BR_SMALL_SIZE (2 * 2 - 1)
7835 #define BR_LARGE_SIZE (6 * 2 - 1)
7836 #define MOV_REG_IMM_SIZE (10 * 2 - 1)
7837 #define MOV_REG_IMM_32BIT_SIZE (6 * 2 - 1)
7838 /* Jump reg for NaCl adds a mask (+4) and add (+3) */
7839 #define JUMP_REG_SIZE ((2 + 1 + 4 + 3) * 2 - 1)
7840 /* Jump membase's size is large and unpredictable    */
7841 /* in native client, just pad it out a whole bundle. */
7842 #define JUMP_MEMBASE_SIZE (kNaClAlignment)
7843 #endif
7844
7845 static int
7846 imt_branch_distance (MonoIMTCheckItem **imt_entries, int start, int target)
7847 {
7848         int i, distance = 0;
7849         for (i = start; i < target; ++i)
7850                 distance += imt_entries [i]->chunk_size;
7851         return distance;
7852 }
7853
7854 /*
7855  * LOCKING: called with the domain lock held
7856  */
7857 gpointer
7858 mono_arch_build_imt_thunk (MonoVTable *vtable, MonoDomain *domain, MonoIMTCheckItem **imt_entries, int count,
7859         gpointer fail_tramp)
7860 {
7861         int i;
7862         int size = 0;
7863         guint8 *code, *start;
7864         gboolean vtable_is_32bit = ((gsize)(vtable) == (gsize)(int)(gsize)(vtable));
7865
7866         for (i = 0; i < count; ++i) {
7867                 MonoIMTCheckItem *item = imt_entries [i];
7868                 if (item->is_equals) {
7869                         if (item->check_target_idx) {
7870                                 if (!item->compare_done) {
7871                                         if (amd64_is_imm32 (item->key))
7872                                                 item->chunk_size += CMP_SIZE;
7873                                         else
7874                                                 item->chunk_size += MOV_REG_IMM_SIZE + CMP_REG_REG_SIZE;
7875                                 }
7876                                 if (item->has_target_code) {
7877                                         item->chunk_size += MOV_REG_IMM_SIZE;
7878                                 } else {
7879                                         if (vtable_is_32bit)
7880                                                 item->chunk_size += MOV_REG_IMM_32BIT_SIZE;
7881                                         else
7882                                                 item->chunk_size += MOV_REG_IMM_SIZE;
7883 #ifdef __native_client_codegen__
7884                                         item->chunk_size += JUMP_MEMBASE_SIZE;
7885 #endif
7886                                 }
7887                                 item->chunk_size += BR_SMALL_SIZE + JUMP_REG_SIZE;
7888                         } else {
7889                                 if (fail_tramp) {
7890                                         item->chunk_size += MOV_REG_IMM_SIZE * 3 + CMP_REG_REG_SIZE +
7891                                                 BR_SMALL_SIZE + JUMP_REG_SIZE * 2;
7892                                 } else {
7893                                         if (vtable_is_32bit)
7894                                                 item->chunk_size += MOV_REG_IMM_32BIT_SIZE;
7895                                         else
7896                                                 item->chunk_size += MOV_REG_IMM_SIZE;
7897                                         item->chunk_size += JUMP_REG_SIZE;
7898                                         /* with assert below:
7899                                          * item->chunk_size += CMP_SIZE + BR_SMALL_SIZE + 1;
7900                                          */
7901 #ifdef __native_client_codegen__
7902                                         item->chunk_size += JUMP_MEMBASE_SIZE;
7903 #endif
7904                                 }
7905                         }
7906                 } else {
7907                         if (amd64_is_imm32 (item->key))
7908                                 item->chunk_size += CMP_SIZE;
7909                         else
7910                                 item->chunk_size += MOV_REG_IMM_SIZE + CMP_REG_REG_SIZE;
7911                         item->chunk_size += BR_LARGE_SIZE;
7912                         imt_entries [item->check_target_idx]->compare_done = TRUE;
7913                 }
7914                 size += item->chunk_size;
7915         }
7916 #if defined(__native_client__) && defined(__native_client_codegen__)
7917         /* In Native Client, we don't re-use thunks, allocate from the */
7918         /* normal code manager paths. */
7919         code = mono_domain_code_reserve (domain, size);
7920 #else
7921         if (fail_tramp)
7922                 code = mono_method_alloc_generic_virtual_thunk (domain, size);
7923         else
7924                 code = mono_domain_code_reserve (domain, size);
7925 #endif
7926         start = code;
7927         for (i = 0; i < count; ++i) {
7928                 MonoIMTCheckItem *item = imt_entries [i];
7929                 item->code_target = code;
7930                 if (item->is_equals) {
7931                         gboolean fail_case = !item->check_target_idx && fail_tramp;
7932
7933                         if (item->check_target_idx || fail_case) {
7934                                 if (!item->compare_done || fail_case) {
7935                                         if (amd64_is_imm32 (item->key))
7936                                                 amd64_alu_reg_imm (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)(gssize)item->key);
7937                                         else {
7938                                                 amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, item->key);
7939                                                 amd64_alu_reg_reg (code, X86_CMP, MONO_ARCH_IMT_REG, MONO_ARCH_IMT_SCRATCH_REG);
7940                                         }
7941                                 }
7942                                 item->jmp_code = code;
7943                                 amd64_branch8 (code, X86_CC_NE, 0, FALSE);
7944                                 if (item->has_target_code) {
7945                                         amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, item->value.target_code);
7946                                         amd64_jump_reg (code, MONO_ARCH_IMT_SCRATCH_REG);
7947                                 } else {
7948                                         amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, & (vtable->vtable [item->value.vtable_slot]));
7949                                         amd64_jump_membase (code, MONO_ARCH_IMT_SCRATCH_REG, 0);
7950                                 }
7951
7952                                 if (fail_case) {
7953                                         amd64_patch (item->jmp_code, code);
7954                                         amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, fail_tramp);
7955                                         amd64_jump_reg (code, MONO_ARCH_IMT_SCRATCH_REG);
7956                                         item->jmp_code = NULL;
7957                                 }
7958                         } else {
7959                                 /* enable the commented code to assert on wrong method */
7960 #if 0
7961                                 if (amd64_is_imm32 (item->key))
7962                                         amd64_alu_reg_imm (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)(gssize)item->key);
7963                                 else {
7964                                         amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, item->key);
7965                                         amd64_alu_reg_reg (code, X86_CMP, MONO_ARCH_IMT_REG, MONO_ARCH_IMT_SCRATCH_REG);
7966                                 }
7967                                 item->jmp_code = code;
7968                                 amd64_branch8 (code, X86_CC_NE, 0, FALSE);
7969                                 /* See the comment below about R10 */
7970                                 amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, & (vtable->vtable [item->value.vtable_slot]));
7971                                 amd64_jump_membase (code, MONO_ARCH_IMT_SCRATCH_REG, 0);
7972                                 amd64_patch (item->jmp_code, code);
7973                                 amd64_breakpoint (code);
7974                                 item->jmp_code = NULL;
7975 #else
7976                                 /* We're using R10 (MONO_ARCH_IMT_SCRATCH_REG) here because R11 (MONO_ARCH_IMT_REG)
7977                                    needs to be preserved.  R10 needs
7978                                    to be preserved for calls which
7979                                    require a runtime generic context,
7980                                    but interface calls don't. */
7981                                 amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, & (vtable->vtable [item->value.vtable_slot]));
7982                                 amd64_jump_membase (code, MONO_ARCH_IMT_SCRATCH_REG, 0);
7983 #endif
7984                         }
7985                 } else {
7986                         if (amd64_is_imm32 (item->key))
7987                                 amd64_alu_reg_imm (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)(gssize)item->key);
7988                         else {
7989                                 amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, item->key);
7990                                 amd64_alu_reg_reg (code, X86_CMP, MONO_ARCH_IMT_REG, MONO_ARCH_IMT_SCRATCH_REG);
7991                         }
7992                         item->jmp_code = code;
7993                         if (x86_is_imm8 (imt_branch_distance (imt_entries, i, item->check_target_idx)))
7994                                 x86_branch8 (code, X86_CC_GE, 0, FALSE);
7995                         else
7996                                 x86_branch32 (code, X86_CC_GE, 0, FALSE);
7997                 }
7998                 g_assert (code - item->code_target <= item->chunk_size);
7999         }
8000         /* patch the branches to get to the target items */
8001         for (i = 0; i < count; ++i) {
8002                 MonoIMTCheckItem *item = imt_entries [i];
8003                 if (item->jmp_code) {
8004                         if (item->check_target_idx) {
8005                                 amd64_patch (item->jmp_code, imt_entries [item->check_target_idx]->code_target);
8006                         }
8007                 }
8008         }
8009
8010         if (!fail_tramp)
8011                 mono_stats.imt_thunks_size += code - start;
8012         g_assert (code - start <= size);
8013
8014         nacl_domain_code_validate(domain, &start, size, &code);
8015
8016         return start;
8017 }
8018
8019 MonoMethod*
8020 mono_arch_find_imt_method (mgreg_t *regs, guint8 *code)
8021 {
8022         return (MonoMethod*)regs [MONO_ARCH_IMT_REG];
8023 }
8024 #endif
8025
8026 MonoVTable*
8027 mono_arch_find_static_call_vtable (mgreg_t *regs, guint8 *code)
8028 {
8029         return (MonoVTable*) regs [MONO_ARCH_RGCTX_REG];
8030 }
8031
8032 GSList*
8033 mono_arch_get_cie_program (void)
8034 {
8035         GSList *l = NULL;
8036
8037         mono_add_unwind_op_def_cfa (l, (guint8*)NULL, (guint8*)NULL, AMD64_RSP, 8);
8038         mono_add_unwind_op_offset (l, (guint8*)NULL, (guint8*)NULL, AMD64_RIP, -8);
8039
8040         return l;
8041 }
8042
8043 MonoInst*
8044 mono_arch_emit_inst_for_method (MonoCompile *cfg, MonoMethod *cmethod, MonoMethodSignature *fsig, MonoInst **args)
8045 {
8046         MonoInst *ins = NULL;
8047         int opcode = 0;
8048
8049         if (cmethod->klass == mono_defaults.math_class) {
8050                 if (strcmp (cmethod->name, "Sin") == 0) {
8051                         opcode = OP_SIN;
8052                 } else if (strcmp (cmethod->name, "Cos") == 0) {
8053                         opcode = OP_COS;
8054                 } else if (strcmp (cmethod->name, "Sqrt") == 0) {
8055                         opcode = OP_SQRT;
8056                 } else if (strcmp (cmethod->name, "Abs") == 0 && fsig->params [0]->type == MONO_TYPE_R8) {
8057                         opcode = OP_ABS;
8058                 }
8059
8060                 if (opcode) {
8061                         MONO_INST_NEW (cfg, ins, opcode);
8062                         ins->type = STACK_R8;
8063                         ins->dreg = mono_alloc_freg (cfg);
8064                         ins->sreg1 = args [0]->dreg;
8065                         MONO_ADD_INS (cfg->cbb, ins);
8066                 }
8067
8068                 opcode = 0;
8069                 if (cfg->opt & MONO_OPT_CMOV) {
8070                         if (strcmp (cmethod->name, "Min") == 0) {
8071                                 if (fsig->params [0]->type == MONO_TYPE_I4)
8072                                         opcode = OP_IMIN;
8073                                 if (fsig->params [0]->type == MONO_TYPE_U4)
8074                                         opcode = OP_IMIN_UN;
8075                                 else if (fsig->params [0]->type == MONO_TYPE_I8)
8076                                         opcode = OP_LMIN;
8077                                 else if (fsig->params [0]->type == MONO_TYPE_U8)
8078                                         opcode = OP_LMIN_UN;
8079                         } else if (strcmp (cmethod->name, "Max") == 0) {
8080                                 if (fsig->params [0]->type == MONO_TYPE_I4)
8081                                         opcode = OP_IMAX;
8082                                 if (fsig->params [0]->type == MONO_TYPE_U4)
8083                                         opcode = OP_IMAX_UN;
8084                                 else if (fsig->params [0]->type == MONO_TYPE_I8)
8085                                         opcode = OP_LMAX;
8086                                 else if (fsig->params [0]->type == MONO_TYPE_U8)
8087                                         opcode = OP_LMAX_UN;
8088                         }
8089                 }
8090
8091                 if (opcode) {
8092                         MONO_INST_NEW (cfg, ins, opcode);
8093                         ins->type = fsig->params [0]->type == MONO_TYPE_I4 ? STACK_I4 : STACK_I8;
8094                         ins->dreg = mono_alloc_ireg (cfg);
8095                         ins->sreg1 = args [0]->dreg;
8096                         ins->sreg2 = args [1]->dreg;
8097                         MONO_ADD_INS (cfg->cbb, ins);
8098                 }
8099
8100 #if 0
8101                 /* OP_FREM is not IEEE compatible */
8102                 else if (strcmp (cmethod->name, "IEEERemainder") == 0) {
8103                         MONO_INST_NEW (cfg, ins, OP_FREM);
8104                         ins->inst_i0 = args [0];
8105                         ins->inst_i1 = args [1];
8106                 }
8107 #endif
8108         }
8109
8110         /*
8111          * Can't implement CompareExchange methods this way since they have
8112          * three arguments.
8113          */
8114
8115         return ins;
8116 }
8117
8118 gboolean
8119 mono_arch_print_tree (MonoInst *tree, int arity)
8120 {
8121         return 0;
8122 }
8123
8124 MonoInst* mono_arch_get_domain_intrinsic (MonoCompile* cfg)
8125 {
8126         MonoInst* ins;
8127
8128         if (appdomain_tls_offset == -1)
8129                 return NULL;
8130
8131         MONO_INST_NEW (cfg, ins, OP_TLS_GET);
8132         ins->inst_offset = appdomain_tls_offset;
8133         return ins;
8134 }
8135
8136 #define _CTX_REG(ctx,fld,i) ((gpointer)((&ctx->fld)[i]))
8137
8138 gpointer
8139 mono_arch_context_get_int_reg (MonoContext *ctx, int reg)
8140 {
8141         switch (reg) {
8142         case AMD64_RCX: return (gpointer)ctx->rcx;
8143         case AMD64_RDX: return (gpointer)ctx->rdx;
8144         case AMD64_RBX: return (gpointer)ctx->rbx;
8145         case AMD64_RBP: return (gpointer)ctx->rbp;
8146         case AMD64_RSP: return (gpointer)ctx->rsp;
8147         default:
8148                 if (reg < 8)
8149                         return _CTX_REG (ctx, rax, reg);
8150                 else if (reg >= 12)
8151                         return _CTX_REG (ctx, r12, reg - 12);
8152                 else
8153                         g_assert_not_reached ();
8154         }
8155 }
8156
8157 /*MONO_ARCH_HAVE_HANDLER_BLOCK_GUARD*/
8158 gpointer
8159 mono_arch_install_handler_block_guard (MonoJitInfo *ji, MonoJitExceptionInfo *clause, MonoContext *ctx, gpointer new_value)
8160 {
8161         int offset;
8162         gpointer *sp, old_value;
8163         char *bp;
8164         const unsigned char *handler;
8165
8166         /*Decode the first instruction to figure out where did we store the spvar*/
8167         /*Our jit MUST generate the following:
8168          mov    %rsp, ?(%rbp)
8169
8170          Which is encoded as: REX.W 0x89 mod_rm
8171          mod_rm (rsp, rbp, imm) which can be: (imm will never be zero)
8172                 mod (reg + imm8):  01 reg(rsp): 100 rm(rbp): 101 -> 01100101 (0x65)
8173                 mod (reg + imm32): 10 reg(rsp): 100 rm(rbp): 101 -> 10100101 (0xA5)
8174
8175         FIXME can we generate frameless methods on this case?
8176
8177         */
8178         handler = clause->handler_start;
8179
8180         /*REX.W*/
8181         if (*handler != 0x48)
8182                 return NULL;
8183         ++handler;
8184
8185         /*mov r, r/m */
8186         if (*handler != 0x89)
8187                 return NULL;
8188         ++handler;
8189
8190         if (*handler == 0x65)
8191                 offset = *(signed char*)(handler + 1);
8192         else if (*handler == 0xA5)
8193                 offset = *(int*)(handler + 1);
8194         else
8195                 return NULL;
8196
8197         /*Load the spvar*/
8198         bp = MONO_CONTEXT_GET_BP (ctx);
8199         sp = *(gpointer*)(bp + offset);
8200
8201         old_value = *sp;
8202         if (old_value < ji->code_start || (char*)old_value > ((char*)ji->code_start + ji->code_size))
8203                 return old_value;
8204
8205         *sp = new_value;
8206
8207         return old_value;
8208 }
8209
8210 /*
8211  * mono_arch_emit_load_aotconst:
8212  *
8213  *   Emit code to load the contents of the GOT slot identified by TRAMP_TYPE and
8214  * TARGET from the mscorlib GOT in full-aot code.
8215  * On AMD64, the result is placed into R11.
8216  */
8217 guint8*
8218 mono_arch_emit_load_aotconst (guint8 *start, guint8 *code, MonoJumpInfo **ji, int tramp_type, gconstpointer target)
8219 {
8220         *ji = mono_patch_info_list_prepend (*ji, code - start, tramp_type, target);
8221         amd64_mov_reg_membase (code, AMD64_R11, AMD64_RIP, 0, 8);
8222
8223         return code;
8224 }
8225
8226 /*
8227  * mono_arch_get_trampolines:
8228  *
8229  *   Return a list of MonoTrampInfo structures describing arch specific trampolines
8230  * for AOT.
8231  */
8232 GSList *
8233 mono_arch_get_trampolines (gboolean aot)
8234 {
8235         return mono_amd64_get_exception_trampolines (aot);
8236 }
8237
8238 /* Soft Debug support */
8239 #ifdef MONO_ARCH_SOFT_DEBUG_SUPPORTED
8240
8241 /*
8242  * mono_arch_set_breakpoint:
8243  *
8244  *   Set a breakpoint at the native code corresponding to JI at NATIVE_OFFSET.
8245  * The location should contain code emitted by OP_SEQ_POINT.
8246  */
8247 void
8248 mono_arch_set_breakpoint (MonoJitInfo *ji, guint8 *ip)
8249 {
8250         guint8 *code = ip;
8251         guint8 *orig_code = code;
8252
8253         /*
8254          * In production, we will use int3 (has to fix the size in the md
8255          * file). But that could confuse gdb, so during development, we emit a SIGSEGV
8256          * instead.
8257          */
8258         g_assert (code [0] == 0x90);
8259         if (breakpoint_size == 8) {
8260                 amd64_mov_reg_mem (code, AMD64_R11, (guint64)bp_trigger_page, 4);
8261         } else {
8262                 amd64_mov_reg_imm_size (code, AMD64_R11, (guint64)bp_trigger_page, 8);
8263                 amd64_mov_reg_membase (code, AMD64_R11, AMD64_R11, 0, 4);
8264         }
8265
8266         g_assert (code - orig_code == breakpoint_size);
8267 }
8268
8269 /*
8270  * mono_arch_clear_breakpoint:
8271  *
8272  *   Clear the breakpoint at IP.
8273  */
8274 void
8275 mono_arch_clear_breakpoint (MonoJitInfo *ji, guint8 *ip)
8276 {
8277         guint8 *code = ip;
8278         int i;
8279
8280         for (i = 0; i < breakpoint_size; ++i)
8281                 x86_nop (code);
8282 }
8283
8284 gboolean
8285 mono_arch_is_breakpoint_event (void *info, void *sigctx)
8286 {
8287 #ifdef HOST_WIN32
8288         EXCEPTION_RECORD* einfo = (EXCEPTION_RECORD*)info;
8289         return FALSE;
8290 #else
8291         siginfo_t* sinfo = (siginfo_t*) info;
8292         /* Sometimes the address is off by 4 */
8293         if (sinfo->si_addr >= bp_trigger_page && (guint8*)sinfo->si_addr <= (guint8*)bp_trigger_page + 128)
8294                 return TRUE;
8295         else
8296                 return FALSE;
8297 #endif
8298 }
8299
8300 /*
8301  * mono_arch_get_ip_for_breakpoint:
8302  *
8303  *   Convert the ip in CTX to the address where a breakpoint was placed.
8304  */
8305 guint8*
8306 mono_arch_get_ip_for_breakpoint (MonoJitInfo *ji, MonoContext *ctx)
8307 {
8308         guint8 *ip = MONO_CONTEXT_GET_IP (ctx);
8309
8310         /* ip points to the instruction causing the fault */
8311         ip -= (breakpoint_size - breakpoint_fault_size);
8312
8313         return ip;
8314 }
8315
8316 /*
8317  * mono_arch_skip_breakpoint:
8318  *
8319  *   Modify CTX so the ip is placed after the breakpoint instruction, so when
8320  * we resume, the instruction is not executed again.
8321  */
8322 void
8323 mono_arch_skip_breakpoint (MonoContext *ctx)
8324 {
8325         MONO_CONTEXT_SET_IP (ctx, (guint8*)MONO_CONTEXT_GET_IP (ctx) + breakpoint_fault_size);
8326 }
8327
8328 /*
8329  * mono_arch_start_single_stepping:
8330  *
8331  *   Start single stepping.
8332  */
8333 void
8334 mono_arch_start_single_stepping (void)
8335 {
8336         mono_mprotect (ss_trigger_page, mono_pagesize (), 0);
8337 }
8338
8339 /*
8340  * mono_arch_stop_single_stepping:
8341  *
8342  *   Stop single stepping.
8343  */
8344 void
8345 mono_arch_stop_single_stepping (void)
8346 {
8347         mono_mprotect (ss_trigger_page, mono_pagesize (), MONO_MMAP_READ);
8348 }
8349
8350 /*
8351  * mono_arch_is_single_step_event:
8352  *
8353  *   Return whenever the machine state in SIGCTX corresponds to a single
8354  * step event.
8355  */
8356 gboolean
8357 mono_arch_is_single_step_event (void *info, void *sigctx)
8358 {
8359 #ifdef HOST_WIN32
8360         EXCEPTION_RECORD* einfo = (EXCEPTION_RECORD*)info;
8361         return FALSE;
8362 #else
8363         siginfo_t* sinfo = (siginfo_t*) info;
8364         /* Sometimes the address is off by 4 */
8365         if (sinfo->si_addr >= ss_trigger_page && (guint8*)sinfo->si_addr <= (guint8*)ss_trigger_page + 128)
8366                 return TRUE;
8367         else
8368                 return FALSE;
8369 #endif
8370 }
8371
8372 /*
8373  * mono_arch_get_ip_for_single_step:
8374  *
8375  *   Convert the ip in CTX to the address stored in seq_points.
8376  */
8377 guint8*
8378 mono_arch_get_ip_for_single_step (MonoJitInfo *ji, MonoContext *ctx)
8379 {
8380         guint8 *ip = MONO_CONTEXT_GET_IP (ctx);
8381
8382         ip += single_step_fault_size;
8383
8384         return ip;
8385 }
8386
8387 /*
8388  * mono_arch_skip_single_step:
8389  *
8390  *   Modify CTX so the ip is placed after the single step trigger instruction,
8391  * we resume, the instruction is not executed again.
8392  */
8393 void
8394 mono_arch_skip_single_step (MonoContext *ctx)
8395 {
8396         MONO_CONTEXT_SET_IP (ctx, (guint8*)MONO_CONTEXT_GET_IP (ctx) + single_step_fault_size);
8397 }
8398
8399 /*
8400  * mono_arch_create_seq_point_info:
8401  *
8402  *   Return a pointer to a data structure which is used by the sequence
8403  * point implementation in AOTed code.
8404  */
8405 gpointer
8406 mono_arch_get_seq_point_info (MonoDomain *domain, guint8 *code)
8407 {
8408         NOT_IMPLEMENTED;
8409         return NULL;
8410 }
8411
8412 #endif