spartan3e: mapping fuer pc-komm

diff --git a/spartan3e/Makefile b/spartan3e/Makefile
index 0ce3e189425e2ffcda5698b44060da105be70659..963365115be6fb58b15bb4cf64946a8a59e1ba2b 100644 (file)
--- a/spartan3e/Makefile
+++ b/spartan3e/Makefile
@@ -14,6 +14,7 @@ PROJ_VHDL = alu.vhd \
        sp_ram.vhd \
        uart_rx.vhd \
        uart_tx.vhd \
+       pc_communication.vhd \
        textmode_vga/console_sm.vhd \
        textmode_vga/console_sm_beh.vhd \
        textmode_vga/console_sm_sync.vhd \

diff --git a/spartan3e/spartan3e.ucf b/spartan3e/spartan3e.ucf
index 5e47e3b741cf984b7705cdf9ef52748e145cb132..d31e9759d6ba70959a58a69599ed70eee9b834ca 100644 (file)
--- a/spartan3e/spartan3e.ucf
+++ b/spartan3e/spartan3e.ucf
@@ -13,7 +13,7 @@
 #NET "BTN_EAST" LOC = "H13" | IOSTANDARD = LVTTL | PULLDOWN ;
 #NET "BTN_NORTH" LOC = "V4" | IOSTANDARD = LVTTL | PULLDOWN ;
 NET "sys_res" LOC = "K17" | IOSTANDARD = LVTTL | PULLDOWN ;
-#NET "BTN_WEST" LOC = "D18" | IOSTANDARD = LVTTL | PULLDOWN ;
+NET "btn_a" LOC = "D18" | IOSTANDARD = LVTTL | PULLDOWN ;
 # ==== Clock inputs (CLK) ====
 NET "CLK_50MHZ" LOC = "C9" | IOSTANDARD = LVCMOS33 ;
 # Define clock period for 50 MHz oscillator (40%/60% duty-cycle)

diff --git a/src/calc.vhd b/src/calc.vhd
index 21ae1cd12fc19ccfeb02a1537ae594e11aef298a..5f9b832a419f593ead9b7224b3603f6510642426 100644 (file)
--- a/src/calc.vhd
+++ b/src/calc.vhd
@@ -67,14 +67,12 @@ architecture top of calc is
        signal do_it, finished : std_logic;
        -- debouncing
        signal sys_res_n_sync : std_logic;
+       signal btn_a_sync : std_logic;
        -- rs232
        signal rx_new, rxd_sync : std_logic;
        signal rx_data : std_logic_vector (7 downto 0);
        signal tx_new, tx_done : std_logic;
        signal tx_data : std_logic_vector (7 downto 0);
-
-       signal btn_a_sync : std_logic;
-
 begin
        -- vga/ipcore
        textmode_vga_inst : entity work.textmode_vga(struct)
@@ -159,7 +157,6 @@ begin
                pc_char => pc_char,
                pc_busy => pc_busy,
                pc_done => pc_done
-
        );
 
        -- parser
@@ -252,7 +249,7 @@ begin
        )
        port map (
                sys_clk => sys_clk,
-               sys_res_n => '1',
+               sys_res_n => sys_res_n_sync,
                data_in => btn_a,
                data_out => btn_a_sync
        );

diff --git a/src/calc_s3e.vhd b/src/calc_s3e.vhd
index 040034ad3ec94bd49496f72f503241d0cd7d12b4..e1bfe689fb774ca9f809b9b4495aa4b9279148c0 100644 (file)
--- a/src/calc_s3e.vhd
+++ b/src/calc_s3e.vhd
@@ -12,8 +12,8 @@ entity calc is
        port (
                CLK_50MHZ : in std_logic;
                sys_res : in std_logic;
-               -- btnA
-               -- TODO: pins
+               -- btnA (here: "btn west")
+               btn_a : in std_logic;
                -- rs232
                rxd : in std_logic;
                txd : out std_logic;
@@ -57,6 +57,13 @@ architecture top of calc is
        signal p_wdone : std_logic;
        signal p_write : hbyte;
        signal p_finished : std_logic;
+       --history/pc_com
+       signal pc_get : std_logic;
+       signal pc_spalte : hspalte;
+       signal pc_zeile : hzeile;
+       signal pc_char : hbyte;
+       signal pc_done : std_logic;
+       signal pc_busy : std_logic;
        -- parser/scanner
        signal do_it, finished : std_logic;
        -- rs232
@@ -142,7 +149,14 @@ begin
                p_wtake => p_wtake,
                p_wdone => p_wdone,
                p_write => p_write,
-               p_finished => p_finished
+               p_finished => p_finished,
+               -- pc communication
+               pc_get =>  pc_get,
+               pc_spalte => pc_spalte,
+               pc_zeile => pc_zeile,
+               pc_char => pc_char,
+               pc_busy => pc_busy,
+               pc_done => pc_done
        );
 
        -- parser
@@ -238,4 +252,27 @@ begin
                tx_new => tx_new,
                tx_done => tx_done
        );
+
+       -- pc-com
+       pc_com_inst : entity work.pc_communication(beh)
+       port map (
+               sys_clk => CLK_50MHZ,
+               sys_res_n => sys_res_n,
+               --button
+               btn_a => not btn_a,
+               --uart_tx
+               tx_data => tx_data,
+               tx_new => tx_new,
+               tx_done => tx_done,
+               --uart_rx
+               rx_data => rx_data,
+               rx_new => rx_new,
+               -- History
+               pc_zeile => pc_zeile,
+               pc_spalte => pc_spalte,
+               pc_get => pc_get,
+               pc_busy => pc_busy,
+               pc_done => pc_done,
+               pc_char => pc_char
+       );
 end architecture top;