pc-com: new line und carrige return

diff --git a/src/beh_pc_communication_tb.vhd b/src/beh_pc_communication_tb.vhd
index d2a693e017c6c688626255cfd54c6d244cfb026f..d9f8789122d6d1d065b7f58d68f7223c12ccc474 100644 (file)
--- a/src/beh_pc_communication_tb.vhd
+++ b/src/beh_pc_communication_tb.vhd
@@ -23,7 +23,6 @@ architecture sim of beh_pc_communication_tb is
                signal rx_new : std_logic;
                signal pc_get : std_logic;
                signal pc_done : std_logic;
-               signal pc_busy : std_logic;
                signal rx_data, tx_data : std_logic_vector(7 downto 0);
 
                signal pc_zeile : hzeile;
@@ -53,7 +52,6 @@ begin
                pc_spalte => pc_spalte,
                pc_get => pc_get,
                pc_done => pc_done,
-               pc_busy => pc_busy,
                pc_char => pc_char
        );
 
@@ -75,7 +73,6 @@ begin
        begin
                pc_char <= (others => '0');
                pc_done <= '0';
-               pc_busy <= '0';
                wait until sys_res_n = '1';
 
                while not endfile (f) loop
@@ -87,11 +84,9 @@ begin
                                wait until rising_edge(pc_get);
                                wait for 150 ns;
                                pc_char <= (others => '0');
-                               pc_busy <= '1';
                                wait for 30 ns;
                                pc_char <= hbyte(std_logic_vector(to_unsigned(character'pos(buf(i)),8)));
                                i := i + 1;
-                               pc_busy <= '0';
                                pc_done <= '1';
                                wait for 30 ns;
                        end loop;

diff --git a/src/pc_communication.vhd b/src/pc_communication.vhd
index c422ed7ade9d9dfb9cecf4992c4c674ab90ec9b1..ca885dd5da144295b812c08b926f015af20323c0 100644 (file)
--- a/src/pc_communication.vhd
+++ b/src/pc_communication.vhd
@@ -37,7 +37,7 @@ architecture beh of pc_communication is
        signal tx_done_i, tx_done_i_next : std_logic;
        signal tx_data_i, tx_data_i_next : std_logic_vector (7 downto 0);
 
-       type STATE_PC is (IDLE, FETCH, FORWARD, WAIT_UART, UART_DONE, CALC_VAL);
+       type STATE_PC is (IDLE, FETCH, FORWARD, WAIT_UART, UART_DONE, CR, CR_WAIT, NL, NL_WAIT);
        signal state, state_next : STATE_PC ;
 begin
        pc_zeile <= hzeile(std_logic_vector(to_unsigned(zeile,7)));
@@ -68,49 +68,15 @@ begin
                end if;
        end process sync;
 
-       output_pc : process (state, zeile, spalte, tx_data_i, tx_done_i, pc_char)
+       process (state, zeile, spalte, tx_data_i, tx_done_i, pc_char, rx_new, btn_a,
+               pc_done)
        begin
                get_next <= '0';
                new_i_next <= '0';
-
                spalte_next <= spalte;
                zeile_next <= zeile;
                tx_data_i_next <= tx_data_i;
 
-               case state is
-                       when IDLE =>
-                               null;
-                       when FETCH =>
-                               get_next <= '1';
-                       when FORWARD =>
-                               tx_data_i_next <= pc_char;
-                               new_i_next <= '1';
-                               -- halte pc_get weiterhin high sodass pc_char garantiert gleich bleibt
-                               get_next <= '1';
-                       when WAIT_UART =>
-                               new_i_next <= '1';
-                               get_next <= '1';
-                       when UART_DONE => null;
-                               -- get_next <= '0';
-                               -- new_i_next <= '0';
-                       when CALC_VAL =>
-                               spalte_next <= spalte + 1;
-                               if spalte = HSPALTE_MAX + 1 then
-                                       tx_data_i_next <= x"0a";
-                                       new_i_next <= '1';
-
-                                       spalte_next <= 1;
-                                       zeile_next <= zeile + 1;
-                                       if zeile = HZEILE_MAX-1 then
-                                               zeile_next <= 0;
-                                       end if;
-                               end if;
-               end case;
-       end process output_pc;
-
-       next_state_pc : process (btn_a, pc_done, rx_new, rx_data, spalte, state,
-               tx_data_i ,tx_done_i, zeile, pc_char)
-       begin
                state_next <= state;
                case state is
                        when IDLE =>
@@ -119,6 +85,7 @@ begin
                                        state_next <= FETCH;
                                end if;
                        when FETCH =>
+                               get_next <= '1';
                                if pc_done = '1' and tx_done_i = '0' then
                                        if pc_char = x"00" then
                                                state_next <= UART_DONE;
@@ -127,19 +94,46 @@ begin
                                        end if;
                                end if;
                        when FORWARD =>
+                               tx_data_i_next <= pc_char;
+                               new_i_next <= '1';
+                               -- halte pc_get weiterhin high sodass pc_char garantiert gleich bleibt
+                               get_next <= '1';
                                state_next <= WAIT_UART;
                        when WAIT_UART =>
-                               if (tx_done_i = '1') then
+                               new_i_next <= '1';
+                               get_next <= '1';
+                               if tx_done_i = '1' then
                                        state_next <= UART_DONE;
                                end if;
-                       when UART_DONE =>
-                               state_next <= CALC_VAL;
-                       when CALC_VAL =>
-                               if spalte = HSPALTE_MAX + 1 and zeile = HZEILE_MAX - 1 then
+                       when UART_DONE => null;
+                               state_next <= FETCH;
+                               spalte_next <= spalte + 1;
+                               if spalte = HSPALTE_MAX + 1 then
+                                       state_next <= NL;
+                                       spalte_next <= 1;
+                                       zeile_next <= zeile + 1;
+                               end if;
+                       when NL =>
+                               tx_data_i_next <= x"0a";
+                               new_i_next <= '1';
+                               if tx_done_i = '1' then
+                                       state_next <= NL_WAIT;
+                               end if;
+                       when NL_WAIT =>
+                               state_next <= CR;
+                       when CR =>
+                               tx_data_i_next <= x"0d";
+                               new_i_next <= '1';
+                               if tx_done_i = '1' then
+                                       state_next <= CR_WAIT;
+                               end if;
+                       when CR_WAIT =>
+                               state_next <= FETCH;
+                               if zeile = HZEILE_MAX then
                                        state_next <= IDLE;
-                               else
-                                       state_next <= FETCH;
+                                       zeile_next <= 0;
+                                       spalte_next <= 1;
                                end if;
                end case;
-       end process next_state_pc;
+       end process;
 end architecture beh;