2 use ieee.std_logic_1164.all;
3 use ieee.numeric_std.all;
6 entity pc_communication is
8 sys_clk : in std_logic;
9 sys_res_n : in std_logic;
15 tx_data : out std_logic_vector(7 downto 0);
16 tx_new : out std_logic;
17 tx_done : in std_logic;
20 rx_data : in std_logic_vector(7 downto 0);
21 rx_new : in std_logic;
24 pc_zeile : out hzeile;
25 pc_spalte : out hspalte;
26 pc_get : out std_logic;
27 pc_done : in std_logic;
30 end entity pc_communication;
32 architecture beh of pc_communication is
33 signal spalte, spalte_next : integer range 1 to HSPALTE_MAX + 2;
34 signal zeile , zeile_next : integer range 0 to HZEILE_MAX + 1;
35 signal get, get_next : std_logic;
36 signal new_i, new_i_next : std_logic;
37 signal tx_done_i, tx_done_i_next : std_logic;
38 signal tx_data_i, tx_data_i_next : std_logic_vector (7 downto 0);
40 type STATE_PC is (IDLE, FETCH, FORWARD, WAIT_UART, UART_DONE, CR, CR_WAIT, NL, NL_WAIT);
41 signal state, state_next : STATE_PC ;
43 pc_zeile <= hzeile(std_logic_vector(to_unsigned(zeile,7)));
44 pc_spalte <= hspalte(std_logic_vector(to_unsigned(spalte,7)));
47 tx_done_i_next <= tx_done;
50 sync: process (sys_clk, sys_res_n)
52 if sys_res_n = '0' then
60 elsif rising_edge(sys_clk) then
61 spalte <= spalte_next;
66 tx_done_i <= tx_done_i_next;
67 tx_data_i <= tx_data_i_next;
71 process (state, zeile, spalte, tx_data_i, tx_done_i, pc_char, rx_new, btn_a,
76 spalte_next <= spalte;
78 tx_data_i_next <= tx_data_i;
83 -- if (rx_new = '1' and rx_data = x"0a") or btn_a = '0' then
84 if (rx_new = '1') or btn_a = '0' then
89 if pc_done = '1' and tx_done_i = '0' then
90 if pc_char = x"00" then
91 state_next <= UART_DONE;
93 state_next <= FORWARD;
97 tx_data_i_next <= pc_char;
99 -- halte pc_get weiterhin high sodass pc_char garantiert gleich bleibt
101 state_next <= WAIT_UART;
105 if tx_done_i = '1' then
106 state_next <= UART_DONE;
108 when UART_DONE => null;
110 spalte_next <= spalte + 1;
111 if spalte = HSPALTE_MAX + 1 then
114 zeile_next <= zeile + 1;
117 tx_data_i_next <= x"0a";
119 if tx_done_i = '1' then
120 state_next <= NL_WAIT;
125 tx_data_i_next <= x"0d";
127 if tx_done_i = '1' then
128 state_next <= CR_WAIT;
132 if zeile = HZEILE_MAX then
139 end architecture beh;