spartan3e: rx_test

diff --git a/spartan3e/spartan3e.ucf b/spartan3e/spartan3e.ucf
index dd16eed041b76d494a47e46e7848e16ed60074e3..3b6f5306c7213d548a378048488f2ad70c323422 100644 (file)
--- a/spartan3e/spartan3e.ucf
+++ b/spartan3e/spartan3e.ucf
@@ -145,7 +145,7 @@ NET "PS2_DATA" LOC = "G13" | IOSTANDARD = LVCMOS33 ;
 #NET "ROT_B" LOC = "G18" | IOSTANDARD = LVTTL | PULLUP ;
 #NET "ROT_CENTER" LOC = "V16" | IOSTANDARD = LVTTL | PULLDOWN ;
 # ==== RS-232 Serial Ports (RS232) ====
-#NET "rxd" LOC = "E8" | IOSTANDARD = LVTTL ;
+NET "rxd" LOC = "E8" | IOSTANDARD = LVTTL ;
 NET "txd" LOC = "F8" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = SLOW ;
 #NET "RS232_DTE_RXD" LOC = "U8" | IOSTANDARD = LVTTL ;
 #NET "RS232_DTE_TXD" LOC = "M13" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = SLOW ;

diff --git a/src/calc_s3e.vhd b/src/calc_s3e.vhd
index 09a2c941d38a096f504fbc07a3059fc5fafc577a..e5f956e50ac5580bba62e6e4702abfa15df5df7f 100644 (file)
--- a/src/calc_s3e.vhd
+++ b/src/calc_s3e.vhd
@@ -15,7 +15,7 @@ entity calc is
                -- btnA
                -- TODO: pins
                -- rs232
-               --rxd : in std_logic;
+               rxd : in std_logic;
                txd : out std_logic;
                -- vga
                vsync_n : out std_logic;
@@ -63,12 +63,12 @@ architecture top of calc is
        -- parser/scanner
        signal do_it, finished : std_logic;
        -- rs232
-       --signal rx_new, rxd_sync : std_logic;
-       --signal rx_data : std_logic_vector (7 downto 0);
+       signal rx_new, rxd_sync : std_logic;
+       signal rx_data : std_logic_vector (7 downto 0);
        signal tx_new, tx_done : std_logic;
        signal tx_data : std_logic_vector (7 downto 0);
 begin
-       led0 <= '0';
+       led0 <= rxd_sync;
        led1 <= '1';
        sys_res_n <= not sys_res;
 
@@ -186,7 +186,10 @@ begin
                finished => finished,
                -- test: uart_tx
                tx_data => tx_data,
-               tx_new => tx_new
+               tx_new => tx_new,
+               -- test: uart_rx
+               rx_data => rx_data,
+               rx_new => rx_new
        );
 
        -- ps/2
@@ -206,31 +209,31 @@ begin
        );
 
        -- synchronizer fuer rxd
-       --sync_rxd_inst : entity work.sync(beh)
-       --generic map (
-       --      SYNC_STAGES => 2,
-       --      RESET_VALUE => '1'
---     )
-       --port map (
-       --      sys_clk => CLK_50MHZ,
-       --      sys_res_n => sys_res_n,
-       --      data_in => rxd,
-       --      data_out => rxd_sync
-       --);
+       sync_rxd_inst : entity work.sync(beh)
+       generic map (
+               SYNC_STAGES => 2,
+               RESET_VALUE => '1'
+       )
+       port map (
+               sys_clk => CLK_50MHZ,
+               sys_res_n => sys_res_n,
+               data_in => rxd,
+               data_out => rxd_sync
+       );
 
        -- rs232-rx
-       --rs232rx_inst : entity work.uart_rx(beh)
-       --generic map (
-       --      CLK_FREQ => 50000000,
-       --      BAUDRATE => 115200
-       --)
-       --port map (
-       --      sys_clk => CLK_50MHZ,
-       --      sys_res_n => sys_res_n,
-       --      rxd => rxd_sync,
-       --      rx_data => rx_data,
-       --      rx_new => rx_new
-       --);
+       rs232rx_inst : entity work.uart_rx(beh)
+       generic map (
+               CLK_FREQ => 50000000,
+               BAUDRATE => 115200
+       )
+       port map (
+               sys_clk => CLK_50MHZ,
+               sys_res_n => sys_res_n,
+               rxd => rxd_sync,
+               rx_data => rx_data,
+               rx_new => rx_new
+       );
 
        -- rs232-tx
        rs232tx_inst : entity work.uart_tx(beh)

diff --git a/src/scanner.vhd b/src/scanner.vhd
index fde57048fe8c8da0aea576b2be3425ffba88eafb..018677c58b8e581d51992ce8bbe2a22b0fd43d25 100644 (file)
--- a/src/scanner.vhd
+++ b/src/scanner.vhd
@@ -21,12 +21,16 @@ entity scanner is
                finished : in std_logic;
                -- test: uart-tx
                tx_data : out std_logic_vector(7 downto 0);
-               tx_new : out std_logic
+               tx_new : out std_logic;
+               -- test: uart_rx
+               rx_data : in std_logic_vector(7 downto 0);
+               rx_new : in std_logic
        );
 end entity scanner;
 
 architecture beh of scanner is
-       type SCANNER_STATE is (SIDLE, SIGNORE_NEXT, SREAD_NEXT, STAKE, SDEL, SENTER);
+       type SCANNER_STATE is (SIDLE, SIGNORE_NEXT, SREAD_NEXT, STAKE, SDEL, SENTER,
+               STAKE_RS232);
        signal state_int, state_next : SCANNER_STATE;
        signal s_char_int, s_char_next : hbyte;
        signal s_take_int, s_take_next : std_logic;
@@ -97,6 +101,9 @@ begin
                                                when others => state_next <= SIDLE;
                                        end case;
                                end if;
+                               if rx_new = '1' then
+                                       state_next <= STAKE_RS232;
+                               end if;
                        when SIGNORE_NEXT =>
                                if new_data = '1' then
                                        state_next <= SIDLE;
@@ -113,7 +120,7 @@ begin
                                                when others => state_next <= SIDLE;
                                        end case;
                                end if;
-                       when STAKE | SDEL=>
+                       when STAKE | SDEL | STAKE_RS232=>
                                if s_done = '1' then
                                        state_next <= SIDLE;
                                end if;
@@ -127,7 +134,7 @@ begin
        end process;
 
        -- out
-       process(state_int, data, s_char_int, new_data)
+       process(state_int, data, s_char_int, new_data, rx_data)
                function sc2ascii (x : hbyte) return hbyte is
                        variable y : hbyte;
                begin
@@ -164,6 +171,13 @@ begin
                        when STAKE =>
                                s_take_next <= '1';
                                s_char_next <= sc2ascii(hbyte(data));
+                       when STAKE_RS232 =>
+                               s_take_next <= '1';
+                               if rx_data >= x"30" and rx_data <= x"39" then
+                                       s_char_next <= hbyte(rx_data);
+                               else
+                                       s_char_next <= x"41";
+                               end if;
                        when SDEL =>
                                s_take_next <= '1';
                                s_backspace_next <= '1';