spartan3e: tx_test

diff --git a/spartan3e/Makefile b/spartan3e/Makefile
index dd3a8acebc277ab3a6f848d3e320a97ee63bb0a6..0ce3e189425e2ffcda5698b44060da105be70659 100644 (file)
--- a/spartan3e/Makefile
+++ b/spartan3e/Makefile
@@ -12,6 +12,8 @@ PROJ_VHDL = alu.vhd \
        parser.vhd \
        scanner.vhd \
        sp_ram.vhd \
+       uart_rx.vhd \
+       uart_tx.vhd \
        textmode_vga/console_sm.vhd \
        textmode_vga/console_sm_beh.vhd \
        textmode_vga/console_sm_sync.vhd \
@@ -36,7 +38,20 @@ PROJ_VHDL = alu.vhd \
        ps2/ps2_keyboard_controller_pkg.vhd \
        ps2/ps2_transceiver.vhd \
        ps2/ps2_transceiver_beh.vhd \
-       ps2/ps2_transceiver_pkg.vhd
+       ps2/ps2_transceiver_pkg.vhd \
+       debouncing/counter.vhd \
+       debouncing/counter_beh.vhd \
+       debouncing/debounce.vhd \
+       debouncing/debounce_fsm.vhd \
+       debouncing/debounce_fsm_beh.vhd \
+       debouncing/debounce_pkg.vhd \
+       debouncing/debounce_struct.vhd \
+       debouncing/event_counter.vhd \
+       debouncing/event_counter_beh.vhd \
+       debouncing/event_counter_pkg.vhd \
+       debouncing/sync.vhd \
+       debouncing/sync_beh.vhd \
+       debouncing/sync_pkg.vhd
 
 PROJ_VHDL := $(foreach n,$(PROJ_VHDL),$(VHDL_DIR)/$(n))
 

diff --git a/spartan3e/spartan3e.ucf b/spartan3e/spartan3e.ucf
index fc193cd85267cccb69e54683dd34b31b4b4d4f49..dd16eed041b76d494a47e46e7848e16ed60074e3 100644 (file)
--- a/spartan3e/spartan3e.ucf
+++ b/spartan3e/spartan3e.ucf
@@ -145,8 +145,8 @@ NET "PS2_DATA" LOC = "G13" | IOSTANDARD = LVCMOS33 ;
 #NET "ROT_B" LOC = "G18" | IOSTANDARD = LVTTL | PULLUP ;
 #NET "ROT_CENTER" LOC = "V16" | IOSTANDARD = LVTTL | PULLDOWN ;
 # ==== RS-232 Serial Ports (RS232) ====
-#NET "RS232_DCE_RXD" LOC = "F8" | IOSTANDARD = LVTTL ;
-#NET "RS232_DCE_TXD" LOC = "E8" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = SLOW ;
+#NET "rxd" LOC = "E8" | IOSTANDARD = LVTTL ;
+NET "txd" LOC = "F8" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = SLOW ;
 #NET "RS232_DTE_RXD" LOC = "U8" | IOSTANDARD = LVTTL ;
 #NET "RS232_DTE_TXD" LOC = "M13" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = SLOW ;
 # ==== DDR SDRAM (SD) ==== (I/O Bank 3, VCCO=2.5V)

diff --git a/src/beh_loopback_tb.vhd b/src/beh_loopback_tb.vhd
index a44bdbdadbdb5823eafb07ddbed032a48755a66f..f19edf29e774d23e1ef660c4180aaa153a89fcb9 100644 (file)
--- a/src/beh_loopback_tb.vhd
+++ b/src/beh_loopback_tb.vhd
@@ -7,7 +7,7 @@ entity beh_loopback_tb is
 end entity beh_loopback_tb;
 
 architecture sim of beh_loopback_tb is
-       constant CLK_FREQ : integer := 33000000;
+       constant CLK_FREQ : integer := 50000000;
        constant BAUDRATE : integer := 115200;
        constant BAUD : integer := CLK_FREQ/BAUDRATE;
 

diff --git a/src/calc_s3e.vhd b/src/calc_s3e.vhd
index c43749d699d003a3243024e65159bc9dd5d3d3fc..09a2c941d38a096f504fbc07a3059fc5fafc577a 100644 (file)
--- a/src/calc_s3e.vhd
+++ b/src/calc_s3e.vhd
@@ -6,6 +6,7 @@ use work.textmode_vga_component_pkg.all;
 use work.textmode_vga_pkg.all;
 use work.textmode_vga_platform_dependent_pkg.all;
 use work.ps2_keyboard_controller_pkg.all;
+use work.sync_pkg.all;
 
 entity calc is
        port (
@@ -14,7 +15,8 @@ entity calc is
                -- btnA
                -- TODO: pins
                -- rs232
-               -- TODO: pins
+               --rxd : in std_logic;
+               txd : out std_logic;
                -- vga
                vsync_n : out std_logic;
                hsync_n : out std_logic;
@@ -60,6 +62,11 @@ architecture top of calc is
        signal p_finished : std_logic;
        -- parser/scanner
        signal do_it, finished : std_logic;
+       -- rs232
+       --signal rx_new, rxd_sync : std_logic;
+       --signal rx_data : std_logic_vector (7 downto 0);
+       signal tx_new, tx_done : std_logic;
+       signal tx_data : std_logic_vector (7 downto 0);
 begin
        led0 <= '0';
        led1 <= '1';
@@ -176,7 +183,10 @@ begin
                s_backspace => s_backspace,
                -- parser
                do_it => do_it,
-               finished => finished
+               finished => finished,
+               -- test: uart_tx
+               tx_data => tx_data,
+               tx_new => tx_new
        );
 
        -- ps/2
@@ -194,4 +204,46 @@ begin
                ps2_clk => ps2_clk,
                ps2_data => ps2_data
        );
+
+       -- synchronizer fuer rxd
+       --sync_rxd_inst : entity work.sync(beh)
+       --generic map (
+       --      SYNC_STAGES => 2,
+       --      RESET_VALUE => '1'
+--     )
+       --port map (
+       --      sys_clk => CLK_50MHZ,
+       --      sys_res_n => sys_res_n,
+       --      data_in => rxd,
+       --      data_out => rxd_sync
+       --);
+
+       -- rs232-rx
+       --rs232rx_inst : entity work.uart_rx(beh)
+       --generic map (
+       --      CLK_FREQ => 50000000,
+       --      BAUDRATE => 115200
+       --)
+       --port map (
+       --      sys_clk => CLK_50MHZ,
+       --      sys_res_n => sys_res_n,
+       --      rxd => rxd_sync,
+       --      rx_data => rx_data,
+       --      rx_new => rx_new
+       --);
+
+       -- rs232-tx
+       rs232tx_inst : entity work.uart_tx(beh)
+       generic map (
+               CLK_FREQ => 50000000,
+               BAUDRATE => 115200
+       )
+       port map (
+               sys_clk => CLK_50MHZ,
+               sys_res_n => sys_res_n,
+               txd => txd,
+               tx_data => tx_data,
+               tx_new => tx_new,
+               tx_done => tx_done
+       );
 end architecture top;