\emph{error} ein Schl\"usselwort in VHDL ist.
\item Die Richtungen bei den Signalen \emph{p\_read} und \emph{p\_write} wurden
jeweils im Modul Parser und History vertauscht.
-\item TODO: \emph{p\_rw} und \emph{p\_spalte} unnoetig (wenn man es in history richtig
-behandelt??)
+\item Parser $\Rightarrow$ History: \emph{p\_rw} und \emph{p\_spalte} unnoetig.
\item aussagekr\"aftigere Fehlermeldungen.
\item ALU: signal \emph{opM} fuer restberechnung
\item Parser: Signale der ALU bleiben intern.
hernehmen
-- vga:
- 1. zuerst einfache history implementierung machen. um folgenden aufbau zu
- realisieren:
- > ps2/ipcore <> scanner <> history_easy <> display <> vga/ipcore
- wenn dann quasi die eingabe bis zum vga durchgemappt werden kann schauts schon
- mal sehr gut aus...
-
- 2. parser einbauen
-
- 3. display-modul komplett fertig machen (vorerst reicht es ja wenn das history
- modul nur die aktuelle eingabe und ergebnis abspeichert -- die daten werden ja
- eh nicht mehr vom display angefordert)
-
-
- rs232/pc-kommunikation
1. schauen ob die eintraege der "einfachen" history gedumpt werden.
haben)
-- history testen: wie? ich stell mir das irgendwie seeehr muehsam vor das so
- automatisiert wie z.b. parser, scanner und alu zu testen.
- idee?
-
-
- alu postlayout noch an die neue alu anpassen (... wenn das projekt final is),
dass ma eine postlayoutsim bei der abgabe zum herzeigen haben
+- was passiert nach 50 berechnungen?
+
+
+- andere farbe als weiss fuer das ergebnis
+
+
+- "$ " oder sonst was fuer ergebnis zeile
+
+
+BUGS:
+- leere eingabe
+
+
== low prio ==
- mehr testfaelle fuer alu/scanner/parser
- parser refactor
add wave inst_disp/state_int
add wave inst_disp/istate_int
+add wave inst_parser/state_int
+
+add wave inst/p_sp_read_int
+add wave inst/p_sp_write_int
+
#rauszoomen
wave zoomout 500.0
signal free : std_logic;
signal command : std_logic_vector(COMMAND_SIZE - 1 downto 0);
signal command_data : std_logic_vector(3 * COLOR_SIZE + CHAR_SIZE -1 downto 0);
-
- -- tmp: history<>scanner
+ -- history/parser
+ signal p_rget : std_logic;
+ signal p_rdone : std_logic;
+ signal p_read : hbyte;
+ signal p_wtake : std_logic;
+ signal p_wdone : std_logic;
+ signal p_write : hbyte;
+ signal p_finished : std_logic;
+ -- parser/scanner
signal do_it, finished : std_logic;
signal stop : boolean := false;
d_get => d_get,
d_done => d_done,
d_char => d_char,
- -- TODO: tmp only!
- do_it => do_it,
- finished => finished
+ -- parser
+ p_rget => p_rget,
+ p_rdone => p_rdone,
+ p_read => p_read,
+ p_wtake => p_wtake,
+ p_wdone => p_wdone,
+ p_write => p_write,
+ p_finished => p_finished
);
-- display
free => free
);
+ -- parser
+ inst_parser : entity work.parser(beh)
+ port map (
+ sys_clk => sys_clk,
+ sys_res_n => sys_res_n,
+ -- history
+ p_rget => p_rget,
+ p_rdone => p_rdone,
+ p_read => p_read,
+ p_wtake => p_wtake,
+ p_wdone => p_wdone,
+ p_write => p_write,
+ p_finished => p_finished,
+ -- scanner
+ do_it => do_it,
+ finished => finished
+ );
+
-- scanner
inst_scan : entity work.scanner(beh)
port map (
sys_res_n <= '0';
new_data <= '0';
data <= (others => '0');
- s_done <= '0';
- finished <= '0';
icwait(sys_clk, 20);
sys_res_n <= '1';
-- system
signal sys_clk, sys_res_n : std_logic;
-- history
- signal p_rw, p_rget, p_rdone, p_wtake, p_wdone, p_finished : std_logic;
+ signal p_rget, p_rdone, p_wtake, p_wdone, p_finished : std_logic;
signal p_read, p_write : hbyte;
- signal p_spalte : hspalte;
--scanner
signal do_it : std_logic;
signal finished : std_logic;
(
sys_clk => sys_clk,
sys_res_n => sys_res_n,
- p_rw => p_rw,
- p_spalte => p_spalte,
+ -- history
p_rget => p_rget,
p_rdone => p_rdone,
p_read => p_read,
-- history/scanner
signal s_char : hbyte;
signal s_take, s_done, s_backspace : std_logic;
-
- -- tmp: history<>scanner
+ -- history/parser
+ signal p_rget : std_logic;
+ signal p_rdone : std_logic;
+ signal p_read : hbyte;
+ signal p_wtake : std_logic;
+ signal p_wdone : std_logic;
+ signal p_write : hbyte;
+ signal p_finished : std_logic;
+ -- parser/scanner
signal do_it, finished : std_logic;
begin
-- vga/ipcore
d_get => d_get,
d_done => d_done,
d_char => d_char,
- -- TODO: tmp only!
+ -- parser
+ p_rget => p_rget,
+ p_rdone => p_rdone,
+ p_read => p_read,
+ p_wtake => p_wtake,
+ p_wdone => p_wdone,
+ p_write => p_write,
+ p_finished => p_finished
+ );
+
+ -- parser
+ parser_inst : entity work.parser(beh)
+ port map (
+ sys_clk => sys_clk,
+ sys_res_n => sys_res_n,
+ -- history
+ p_rget => p_rget,
+ p_rdone => p_rdone,
+ p_read => p_read,
+ p_wtake => p_wtake,
+ p_wdone => p_wdone,
+ p_write => p_write,
+ p_finished => p_finished,
+ -- scanner
do_it => do_it,
finished => finished
);
s_take => s_take,
s_done => s_done,
s_backspace => s_backspace,
- -- TODO: parser. temporaer mit history verbunden
+ -- parser
do_it => do_it,
finished => finished
);
-- history/scanner
signal s_char : hbyte;
signal s_take, s_done, s_backspace : std_logic;
-
- -- tmp: history<>scanner
+ -- history/parser
+ signal p_rget : std_logic;
+ signal p_rdone : std_logic;
+ signal p_read : hbyte;
+ signal p_wtake : std_logic;
+ signal p_wdone : std_logic;
+ signal p_write : hbyte;
+ signal p_finished : std_logic;
+ -- parser/scanner
signal do_it, finished : std_logic;
begin
led0 <= '0';
d_get => d_get,
d_done => d_done,
d_char => d_char,
- -- TODO: tmp only!
+ -- parser
+ p_rget => p_rget,
+ p_rdone => p_rdone,
+ p_read => p_read,
+ p_wtake => p_wtake,
+ p_wdone => p_wdone,
+ p_write => p_write,
+ p_finished => p_finished
+ );
+
+ -- parser
+ parser_inst : entity work.parser(beh)
+ port map (
+ sys_clk => CLK_50MHZ,
+ sys_res_n => sys_res_n,
+ -- history
+ p_rget => p_rget,
+ p_rdone => p_rdone,
+ p_read => p_read,
+ p_wtake => p_wtake,
+ p_wdone => p_wdone,
+ p_write => p_write,
+ p_finished => p_finished,
+ -- scanner
do_it => do_it,
finished => finished
);
s_take => s_take,
s_done => s_done,
s_backspace => s_backspace,
- -- TODO: parser. temporaer mit history verbunden
+ -- parser
do_it => do_it,
finished => finished
);
d_done : out std_logic;
d_char : out hbyte;
-- Parser
- -- TODO: pins
-
- -- TODO: tmp only!
- do_it : in std_logic;
- finished : out std_logic
+ p_rget : in std_logic;
+ p_rdone : out std_logic;
+ p_read : out hbyte;
+ p_wtake : in std_logic;
+ p_wdone : out std_logic;
+ p_write : in hbyte;
+ p_finished : in std_logic
);
end entity history;
architecture beh of history is
type HISTORY_STATE is (SIDLE, S_S_INIT, S_S_WRITE, S_S_BS, S_S_DONE, S_S_FIN,
- S_D_INIT, S_D_READ, S_S_FIN_POSUP);
+ S_D_INIT, S_D_READ, S_S_FIN_POSUP, S_P_READ, S_P_READ_DONE, S_P_WRITE,
+ S_P_WRITE_DONE, S_P_DONE);
signal state_int, state_next : HISTORY_STATE;
signal was_bs_int, was_bs_next : std_logic;
signal pos_int, pos_next : std_logic_vector(H_RAM_WIDTH - 1 downto 0);
signal d_new_bs_int, d_new_bs_next: std_logic;
signal d_done_int, d_done_next : std_logic;
signal d_char_int, d_char_next : hbyte;
-
- signal finished_int, finished_next : std_logic;
+ signal p_rdone_int, p_rdone_next : std_logic;
+ signal p_wdone_int, p_wdone_next : std_logic;
+ signal p_read_int, p_read_next : hbyte;
+ signal p_sp_read_int, p_sp_read_next : hspalte;
+ signal p_sp_write_int, p_sp_write_next : hspalte;
-- ram
signal address_next, address_int : std_logic_vector(H_RAM_WIDTH - 1 downto 0);
d_new_bs <= d_new_bs_int;
d_done <= d_done_int;
d_char <= d_char_int;
-
- finished <= finished_int;
+ p_rdone <= p_rdone_int;
+ p_wdone <= p_wdone_int;
+ p_read <= p_read_int;
process(sys_clk, sys_res_n)
begin
d_new_bs_int <= '0';
d_done_int <= '0';
d_char_int <= (others => '0');
-
- finished_int <= '0';
+ p_rdone_int <= '0';
+ p_wdone_int <= '0';
+ p_read_int <= (others => '0');
+ p_sp_read_int <= (others => '0');
+ p_sp_write_int <= (others => '0');
address_int <= (0 => '1', others => '0');
data_in_int <= x"00";
d_new_bs_int <= d_new_bs_next;
d_done_int <= d_done_next;
d_char_int <= d_char_next;
-
- finished_int <= finished_next;
+ p_rdone_int <= p_rdone_next;
+ p_wdone_int <= p_wdone_next;
+ p_read_int <= p_read_next;
+ p_sp_read_int <= p_sp_read_next;
+ p_sp_write_int <= p_sp_write_next;
address_int <= address_next;
data_in_int <= data_in_next;
end process;
-- next state
- process(state_int, d_get, do_it, s_take, s_backspace, was_bs_int)
+ process(state_int, d_get, p_finished, s_take, s_backspace, was_bs_int,
+ p_rget, p_wtake)
begin
state_next <= state_int;
-- S_S_FIN: tmp..
if s_take = '1' then
state_next <= S_S_INIT;
- elsif do_it = '1' then
+ elsif p_rget = '1' then
+ state_next <= S_P_READ;
+ elsif p_wtake = '1' then
+ state_next <= S_P_WRITE;
+ elsif p_finished = '1' then
state_next <= S_S_FIN;
elsif d_get = '1' then
state_next <= S_D_INIT;
when S_S_BS =>
state_next <= S_S_DONE;
when S_S_FIN =>
- if do_it = '0' then
+ if p_finished = '0' then
state_next <= S_S_FIN_POSUP;
end if;
when S_S_FIN_POSUP =>
if d_get = '0' then
state_next <= SIDLE;
end if;
+
+ when S_P_READ =>
+ state_next <= S_P_READ_DONE;
+ when S_P_READ_DONE =>
+ if p_rget = '0' then
+ state_next <= S_P_DONE;
+ end if;
+ when S_P_WRITE =>
+ state_next <= S_P_WRITE_DONE;
+ when S_P_WRITE_DONE =>
+ if p_wtake = '0' then
+ state_next <= S_P_DONE;
+ end if;
+ when S_P_DONE =>
+ state_next <= SIDLE;
end case;
end process;
-- out
process(state_int, s_cnt_int, d_spalte, d_zeile, data_out, s_char, address_int,
- data_in_int, d_new_result_int, d_new_eingabe_int, d_new_bs_int,
- was_bs_int, s_take, pos_int)
+ data_in_int, d_new_result_int, d_new_eingabe_int, d_new_bs_int,
+ was_bs_int, s_take, pos_int, p_rdone_int, p_wdone_int, p_read_int,
+ p_write, p_sp_read_int, p_sp_write_int)
variable addr_tmp : std_logic_vector(H_RAM_WIDTH - 1 downto 0);
+ variable spalte_tmp : hspalte;
variable mul_tmp : std_logic_vector((H_RAM_WIDTH*2) -1 downto 0);
begin
s_done_next <= '0';
d_new_bs_next <= '0';
d_done_next <= '0';
d_char_next <= (others => '0');
- finished_next <= '0';
wr_next <= '0';
address_next <= address_int;
data_in_next <= data_in_int;
+ p_rdone_next <= p_rdone_int;
+ p_wdone_next <= p_wdone_int;
+ p_read_next <= p_read_int;
+ p_sp_read_next <= p_sp_read_int;
+ p_sp_write_next <= p_sp_write_int;
case state_int is
when SIDLE =>
data_in_next <= (others => '0');
was_bs_next <= '1';
when S_S_FIN =>
- finished_next <= '1';
s_cnt_next <= (0 => '1', others => '0');
d_new_result_next <= '1';
when S_S_FIN_POSUP =>
if s_take = '0' then
was_bs_next <= '0';
end if;
+ -- TODO: bessere stelle fuers reseten der parser signale?
+ p_sp_read_next <= (others => '0');
+ p_sp_write_next <= std_logic_vector(to_unsigned(71,p_sp_write_next'length));
when S_D_INIT =>
addr_tmp := (others => '0');
when S_D_READ =>
d_char_next <= data_out;
d_done_next <= '1';
+
+ when S_P_READ =>
+ wr_next <= '0';
+ spalte_tmp := std_logic_vector(unsigned(p_sp_read_int) + 1);
+ p_sp_read_next <= spalte_tmp;
+ address_next <= std_logic_vector(unsigned(pos_int) + unsigned(spalte_tmp));
+ when S_P_READ_DONE =>
+ p_rdone_next <= '1';
+ p_read_next <= data_out;
+
+ when S_P_WRITE =>
+ wr_next <= '1';
+ data_in_next <= p_write;
+ spalte_tmp := std_logic_vector(unsigned(p_sp_write_int) - 1);
+ p_sp_write_next <= spalte_tmp;
+ address_next <= std_logic_vector(unsigned(pos_int) + to_unsigned(71,H_RAM_WIDTH) + unsigned(spalte_tmp));
+ when S_P_WRITE_DONE =>
+ p_wdone_next <= '1';
+ when S_P_DONE =>
+ p_rdone_next <= '0';
+ p_wdone_next <= '0';
end case;
end process;
sys_clk : in std_logic;
sys_res_n : in std_logic;
-- History
- p_rw : out std_logic;
- p_spalte : out hspalte;
p_rget : out std_logic;
p_rdone : in std_logic;
p_read : in hbyte;
signal p_rget_int, p_rget_next : std_logic;
signal p_wtake_int, p_wtake_next : std_logic;
signal p_finished_int, p_finished_next : std_logic;
+ signal finished_int, finished_next : std_logic;
signal aktop_int, aktop_next : alu_ops;
signal opp_int, opp_next : alu_ops;
signal opcode_int, opcode_next : alu_ops;
p_rget <= p_rget_int;
p_wtake <= p_wtake_int;
p_finished <= p_finished_int;
+ finished <= finished_int;
opcode <= opcode_int;
op1 <= op1_int;
errc_tmp_int <= 0;
firstz_int <= true;
-- out ports
- p_rw <= '0';
- p_spalte <= (others => '0');
p_rget_int <= '0';
p_write_int <= (others => '0');
p_wtake_int <= '0';
p_finished_int <= '0';
+ finished_int <= '0';
opcode_int <= ALU_NOP;
op1_int <= (others => '0');
op2_int <= (others => '0');
do_calc_int <= '0';
- finished <= '0';
elsif rising_edge(sys_clk) then
-- internal
state_int <= state_next;
p_write_int <= p_write_next;
p_wtake_int <= p_wtake_next;
p_finished_int <= p_finished_next;
+ finished_int <= finished_next;
opcode_int <= opcode_next;
op1_int <= op1_next;
op2_int <= op2_next;
type errstrings is array (natural range 1 to 3) of hstring;
constant error_str : errstrings := (
- 1 => " Division durch Null" & nul,
- 2 => " Syntax" & nul,
- 3 => " Over- bzw. Underflow" & nul
+ 1 => " > Fehler: Division durch Null " & nul,
+ 2 => " > Fehler: Syntax " & nul,
+ 3 => " > Fehler: Over- bzw. Underflow " & nul
);
begin
-- internal
p_write_next <= p_write_int;
p_wtake_next <= '0';
p_finished_next <= '0';
+ finished_next <= '0';
opcode_next <= opcode_int;
op1_next <= op1_int;
op2_next <= op2_int;
err_next <= 0;
errc_next <= 71;
p_finished_next <= '1';
+ finished_next <= '1';
end case;
-- fehlerbehandlung
architecture beh of sp_ram is
subtype RAM_ENTRY_TYPE is hbyte;
type RAM_TYPE is array (1 to (2 ** ADDR_WIDTH)) of RAM_ENTRY_TYPE;
- signal ram : RAM_TYPE := (others => x"41");
+ signal ram : RAM_TYPE := (others => x"00");
begin
process(sys_clk)
begin
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