alu: postsim geht jetzt zwar, trotzdem haufweise warnings...

"** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es)."

5451mal...

diff --git a/src/Makefile b/src/Makefile
index 83c57f165bbce3b65e6a8a2aff698413633c3a23..10cc19e7c1f15138e5248027868b0f18a2d153bb 100644 (file)
--- a/src/Makefile
+++ b/src/Makefile
@@ -9,15 +9,15 @@ POST_SDO_INST := inst
 QUARTUS := $(MPWD)/../quartus/calc
 QUOPT := --read_settings_files=on --write_settings_files=off calc -c calc
 
+HN := $(shell hostname)
+TILABHOSTS := $(shell echo ti{1..9}) apps1
+
 ifeq ($(findstring $(HN), $(TILABHOSTS)),$(HN))
 QUMACRO := unset LS_COLORS; cd $(QUARTUS); export LD_LIBRARY_PATH=/opt/quartus/quartus/linux64; export LM_LICENSE_FILE=26888@quartus; 
 else
 QUMACRO := unset LS_COLORS; cd $(QUARTUS);
 endif
 
-HN := $(shell hostname)
-TILABHOSTS := $(shell echo ti{1..9}) apps1
-
 WORK := work
 
 # o source files der module

diff --git a/src/alu.vhd b/src/alu.vhd
index 15230498e147d9351fbbb35d70623bbbfe84e648..caff4958e91f011f31ee3def3a854fe3ad9f6db9 100644 (file)
--- a/src/alu.vhd
+++ b/src/alu.vhd
@@ -22,11 +22,11 @@ architecture beh of alu is
        type ALU_STATE is (SIDLE, SADD, SSUB, SMUL, SDIV, SDIV_CALC, SDIV_DONE, SDONE);
        signal state_int, state_next : ALU_STATE;
        signal done_intern, div_calc_done, div_go_calc : std_logic;
-       signal op3_int, op3_next : csigned;
+       signal op3_int, op3_next : csigned := (others => '0');
        signal calc_done_int, calc_done_next : std_logic;
        -- signale fuer division
        signal dividend_msb_int, dividend_msb_next, laengediv_int, laengediv_next : natural;
-       signal quo_int, quo_next, aktdiv, aktdiv_next, op1_int, op1_next, op2_int, op2_next : csigned;
+       signal quo_int, quo_next, aktdiv_int, aktdiv_int_next, op1_int, op1_next, op2_int, op2_next : csigned;
        signal sign_int, sign_next : std_logic;
 begin
        op3 <= op3_int;
@@ -43,7 +43,7 @@ begin
                        dividend_msb_int <= 0;
                        laengediv_int <= 0;
                        quo_int <= (others => '0');
-                       aktdiv <= (others => '0');
+                       aktdiv_int <= (others => '0');
                        op1_int <= (others => '0');
                        op2_int <= (others => '0');
                        sign_int <= '0';
@@ -55,7 +55,7 @@ begin
                        dividend_msb_int <= dividend_msb_next;
                        laengediv_int <= laengediv_next;
                        quo_int <= quo_next;
-                       aktdiv <= aktdiv_next;
+                       aktdiv_int <= aktdiv_int_next;
                        op1_int <= op1_next;
                        op2_int <= op2_next;
                        sign_int <= sign_next;
@@ -104,14 +104,12 @@ begin
        end process;
 
        -- output
-       process(state_int, op1, op2, dividend_msb_int, laengediv_int, quo_int, aktdiv, sign_int, op1_int, op2_int)
-               variable tmperg : csigned;
+       process(state_int, op1, op2, dividend_msb_int, laengediv_int, quo_int, aktdiv_int, sign_int, op1_int, op2_int, op3_int)
                variable multmp : signed(((2*CBITS)-1) downto 0);
                -- vars fuer div
                variable laengediv_var, dividend_msb_var : natural;
-               variable aktdiv_var, quo_var, op1_var, op2_var : csigned;
+               variable aktdiv_int_var, quo_var, op1_var, op2_var : csigned;
        begin
-               op3_next <= (others => '0');
                calc_done_next <= '0';
                div_calc_done <= '0';
                div_go_calc <= '0';
@@ -120,28 +118,28 @@ begin
                dividend_msb_next <= 0;
                laengediv_next <= 0;
                quo_next <= (others => '0');
-               aktdiv_next <= (others => '0');
+               aktdiv_int_next <= (others => '0');
                op1_next <= (others => '0');
                op2_next <= (others => '0');
                sign_next <= '0';
+               op3_next <= (others => '0');
 
                case state_int is
                        when SIDLE =>
-                               tmperg := (others => '0');
+                               null;
                        when SADD =>
-                               tmperg := op1 + op2;
+                               op3_next <= op1 + op2;
                                done_intern <= '1';
                        when SSUB =>
-                               tmperg := op1 - op2;
+                               op3_next <= op1 - op2;
                                done_intern <= '1';
                        when SMUL =>
                                multmp := op1 * op2;
-                               tmperg(CBITS-1) := multmp((2*CBITS)-1);
-                               tmperg((CBITS-2) downto 0) := multmp((CBITS-2) downto 0);
+                               op3_next(CBITS-1) <= multmp((2*CBITS)-1);
+                               op3_next((CBITS-2) downto 0) <= multmp((CBITS-2) downto 0);
                                done_intern <= '1';
                        when SDIV =>
                                -- division implementiert nach ~hwmod/doc/division.pdf
-                               tmperg := (others => '0');
                                if op2 = to_signed(0,CBITS) then
                                        -- TODO: err out signal
                                        done_intern <= '1';
@@ -159,7 +157,7 @@ begin
                                        dividend_msb_var := find_msb(op1_var)-1;
                                        laengediv_var := find_msb(op2_var)-1;
 
-                                       aktdiv_next <= op1_var srl (dividend_msb_var - laengediv_var + 1);
+                                       aktdiv_int_next <= op1_var srl (dividend_msb_var - laengediv_var + 1);
 
                                        div_go_calc <= '1';
                                        dividend_msb_next <= dividend_msb_var;
@@ -170,20 +168,18 @@ begin
                                        sign_next <= op1(CBITS-1) xor op2(CBITS-1);
                                end if;
                        when SDIV_CALC =>
-                               tmperg := (others => '0');
-
                                if (dividend_msb_int - laengediv_int + 1) > 0 then
-                                       aktdiv_var := aktdiv sll 1;
-                                       aktdiv_var(0) := op1_int(dividend_msb_int - laengediv_int);
+                                       aktdiv_int_var := aktdiv_int sll 1;
+                                       aktdiv_int_var(0) := op1_int(dividend_msb_int - laengediv_int);
 
                                        quo_var := quo_int sll 1;
-                                       if aktdiv_var >= op2_int then
+                                       if aktdiv_int_var >= op2_int then
                                                quo_var(0) := '1';
-                                               aktdiv_var := aktdiv_var - op2_int;
+                                               aktdiv_int_var := aktdiv_int_var - op2_int;
                                        end if;
 
                                        quo_next <= quo_var;
-                                       aktdiv_next <= aktdiv_var;
+                                       aktdiv_int_next <= aktdiv_int_var;
                                        dividend_msb_next <= dividend_msb_int;
                                        laengediv_next <= laengediv_int + 1;
                                        op1_next <= op1_int;
@@ -198,13 +194,11 @@ begin
                                        div_calc_done <= '1';
                                end if;
                        when SDIV_DONE =>
-                               tmperg := quo_int;
+                               op3_next <= quo_int;
                                done_intern <= '1';
                        when SDONE =>
-                               done_intern <= '1';
                                calc_done_next <= '1';
-                               op3_next <= tmperg;
-                               tmperg := (others => '0');
+                               op3_next <= op3_int;
                end case;
        end process;
 end architecture beh;

diff --git a/src/beh_alu_tb.do b/src/beh_alu_tb.do
index b6b9c47d19ff757f3c79838aeafb8fb05d870c04..27a93631bd731e6a3e73c5034bed4b0e6b373547 100644 (file)
--- a/src/beh_alu_tb.do
+++ b/src/beh_alu_tb.do
@@ -4,10 +4,10 @@ alias rr "restart -f"
 #signale hinzufuegen
 add wave sys_clk
 add wave sys_res_n
-add wave op1
+add wave -radix decimal op1
 add wave opcode
-add wave op2
-add wave op3
+add wave -radix decimal op2
+add wave -radix decimal op3
 add wave do_calc
 add wave calc_done
 

diff --git a/src/beh_alu_tb.vhd b/src/beh_alu_tb.vhd
index 0efdcc37ab719fa96c9b7bcc76dd233c22677c80..fb9382cbbc09667de2dcad15298c35e109c4989c 100644 (file)
--- a/src/beh_alu_tb.vhd
+++ b/src/beh_alu_tb.vhd
@@ -91,11 +91,11 @@ begin
                op1 <= (others => '0');
                op2 <= (others => '0');
 
-               wait for 300 ns;
+               icwait(sys_clk, 30);
                sys_res_n <= '1';
 
                for i in testmatrix'range loop
-                       wait for 100 ns;
+                       icwait(sys_clk, 10);
                        op1 <= to_signed(testmatrix(i).o1,CBITS);
                        opcode <= testmatrix(i).o;
                        op2 <= to_signed(testmatrix(i).o2,CBITS);
@@ -105,6 +105,7 @@ begin
 
                        -- warten auf die alu einheit
                        wait on calc_done;
+                       icwait(sys_clk, 1);
 
                        assert op3 = to_signed(testmatrix(i).expected,CBITS)
                                report "" & cinteger'image(testmatrix(i).o1) & 
@@ -113,7 +114,7 @@ begin
                                "/= " & integer'image(to_integer(op3)) &
                                " -- erwartet: " & cinteger'image(testmatrix(i).expected);
 
-                       wait for 5 ns;
+                       icwait(sys_clk, 2);
                        -- ack it!
                        do_calc <= '0';
                end loop;

diff --git a/src/gen_pkg.vhd b/src/gen_pkg.vhd
index e654a3b24d5597ce54230ae777d81a22325c6680..9eabeb0e177ae6b6b189119934fa8c1b3ef2eff7 100644 (file)
--- a/src/gen_pkg.vhd
+++ b/src/gen_pkg.vhd
@@ -16,6 +16,7 @@ package gen_pkg is
        --TODO: bei CBITS-1 gibts einen overflow :/
        subtype cinteger is integer range -(2**(CBITS-2)) to ((2**(CBITS-2))-1);
        function find_msb(a : csigned) return natural;
+       procedure icwait(signal clk_i : IN std_logic; cycles: Natural);
 end package gen_pkg;
 
 package body gen_pkg is
@@ -28,5 +29,12 @@ package body gen_pkg is
                end loop;
                return (CBITS - r);
        end function find_msb;
+
+       procedure icwait(signal clk_i : IN std_logic; cycles: Natural) is
+       begin
+               for i in 1 to cycles loop
+                       wait until clk_i= '0' and clk_i'event;
+               end loop;
+       end;
 end package body gen_pkg;
 

diff --git a/src/post_alu_tb.do b/src/post_alu_tb.do
index b6b9c47d19ff757f3c79838aeafb8fb05d870c04..27a93631bd731e6a3e73c5034bed4b0e6b373547 100644 (file)
--- a/src/post_alu_tb.do
+++ b/src/post_alu_tb.do
@@ -4,10 +4,10 @@ alias rr "restart -f"
 #signale hinzufuegen
 add wave sys_clk
 add wave sys_res_n
-add wave op1
+add wave -radix decimal op1
 add wave opcode
-add wave op2
-add wave op3
+add wave -radix decimal op2
+add wave -radix decimal op3
 add wave do_calc
 add wave calc_done
 

diff --git a/src/post_alu_tb.vhd b/src/post_alu_tb.vhd
index 7563f2004723d474a4884ca03845b13a5cad91b6..7a960787ac4ac5a4af685898ada14ce7d43d551b 100644 (file)
--- a/src/post_alu_tb.vhd
+++ b/src/post_alu_tb.vhd
@@ -91,11 +91,11 @@ begin
                op1 <= (others => '0');
                op2 <= (others => '0');
 
-               wait for 300 ns;
+               icwait(sys_clk, 30);
                sys_res_n <= '1';
 
                for i in testmatrix'range loop
-                       wait for 100 ns;
+                       icwait(sys_clk, 10);
                        op1 <= std_logic_vector(to_signed(testmatrix(i).o1,CBITS));
                        opcode <= testmatrix(i).o;
                        op2 <= std_logic_vector(to_signed(testmatrix(i).o2,CBITS));
@@ -105,7 +105,7 @@ begin
 
                        -- warten auf die alu einheit
                        wait on calc_done;
-                       wait for 80 ns;
+                       icwait(sys_clk, 1);
 
                        assert op3 = std_logic_vector(to_signed(testmatrix(i).expected,CBITS))
                                report "" & cinteger'image(testmatrix(i).o1) & 
@@ -114,7 +114,7 @@ begin
                                "/= " & integer'image(to_integer(signed(op3))) &
                                " -- erwartet: " & cinteger'image(testmatrix(i).expected);
 
-                       wait for 5 ns;
+                       icwait(sys_clk, 2);
                        -- ack it!
                        do_calc <= '0';
                end loop;