added pc_communication and uart_tx to beh_history

diff --git a/src/beh_history_tb.vhd b/src/beh_history_tb.vhd
index 45712266385ac9e74c85092135fa50b5fbd70063..abce49d9826eadf770228f27b85bbf478fd8859f 100644 (file)
--- a/src/beh_history_tb.vhd
+++ b/src/beh_history_tb.vhd
@@ -38,6 +38,17 @@ architecture sim of beh_history_tb is
        signal p_finished : std_logic;
        -- parser/scanner
        signal do_it, finished : std_logic;
+       --uart_tx
+       signal tx_data : std_logic_vector(7 downto 0);
+       signal tx_new, tx_done, txd : std_logic;
+       --pc_communication
+       signal pc_zeile : hzeile;
+       signal pc_spalte : hspalte;
+       signal pc_get, pc_done : std_logic;
+       signal pc_char : hbyte;
+       --dummy button
+       signal btn_a_int : std_logic;
+
 
        signal stop : boolean := false;
 begin
@@ -67,7 +78,13 @@ begin
                p_wtake => p_wtake,
                p_wdone => p_wdone,
                p_write => p_write,
-               p_finished => p_finished
+               p_finished => p_finished,
+               -- PC-komm
+               pc_get    => pc_get,
+               pc_spalte => pc_spalte,
+               pc_zeile  => pc_zeile,
+               pc_char   => pc_char,
+               pc_done   => pc_done
        );
 
        -- display
@@ -125,7 +142,38 @@ begin
                do_it => do_it,
                finished => finished
        );
+       --uart_tx
+       inst_uart : entity work.uart_tx(beh)
+       port map (
+               sys_clk => sys_clk,
+               sys_res_n => sys_res_n,
+               txd => txd,
+               tx_data =>tx_data,
+               tx_new => tx_new,
+               tx_done => tx_done
+       );
 
+       --pc_communication
+       inst_pc_com : entity work.pc_communication(beh)
+       port map(
+               sys_clk => sys_clk,
+               sys_res_n => sys_res_n,
+               --button
+               btn_a => btn_a_int,
+               --uart_tx
+               tx_data => tx_data,
+               tx_new => tx_new,
+               tx_done => tx_done,
+               --uart_rx
+               rx_data => (others => '0'),
+               rx_new => '0',
+               -- History
+                d_zeile  => pc_zeile,
+                d_spalte => pc_spalte,
+                d_get    => pc_get,
+                d_done   => pc_done,
+                d_char   => pc_char
+       );
 
        process
        begin
@@ -260,4 +308,16 @@ begin
                stop <= true;
                wait;
        end process;
+
+       btn_pressed : process is
+       begin
+               btn_a_int <= '0';
+               wait until sys_res_n = '1';
+               wait for 50000 * 15 ns;
+               wait until rising_edge(sys_clk);
+               btn_a_int <= '1';
+               wait for 30 ns;
+               btn_a_int <= '0';
+               wait;
+       end process btn_pressed;
 end architecture sim;