alu: fix fuer synthese

diff --git a/src/alu.vhd b/src/alu.vhd
index 2d9e4a7523ea95df162b0c83e6fd07bf4c385385..fad995e48a94dcdbbcb17065132137233f6a0fcc 100644 (file)
--- a/src/alu.vhd
+++ b/src/alu.vhd
@@ -21,7 +21,12 @@ architecture beh of alu is
        type ALU_STATE is (SIDLE, SADD, SSUB, SMUL, SDIV, SDONE);
        signal state, state_next : ALU_STATE;
        signal done_intern : std_logic;
+       signal op3_int, op3_next : csigned;
+       signal calc_done_int, calc_done_next : std_logic;
 begin
+       op3 <= op3_int;
+       calc_done <= calc_done_int;
+
        -- sync
        process(sys_clk, sys_res_n)
        begin
@@ -29,6 +34,8 @@ begin
                        state <= SIDLE;
                elsif rising_edge(sys_clk) then
                        state <= state_next;
+                       op3_int <= op3_next;
+                       calc_done_int <= calc_done_next;
                end if;
        end process;
 
@@ -78,15 +85,16 @@ begin
        end process;
 
        -- output
-       process(state)
+       process(state, op1, op2)
        variable tmperg : csigned;
        variable multmp : signed(((2*CBITS)-1) downto 0);
        begin
-               op3 <= (others => '0');
-               calc_done <= '0';
+               op3_next <= (others => '0');
+               calc_done_next <= '0';
 
                case state is
                        when SIDLE =>
+                               tmperg := (others => '0');
                                done_intern <= '0';
                        when SADD =>
                                tmperg := op1 + op2;
@@ -104,8 +112,9 @@ begin
                                done_intern <= '1';
                        when SDONE =>
                                done_intern <= '1';
-                               calc_done <= '1';
-                               op3 <= tmperg;
+                               calc_done_next <= '1';
+                               op3_next <= tmperg;
+                               tmperg := (others => '0');
                end case;
        end process;
 end architecture beh;