tx-test: transmit erfolgreich getestet :)

diff --git a/quartus/project_gen.tcl b/quartus/project_gen.tcl
index a6204ef19201b780ad5c2f84646529a5686cefd4..10c298e7980a2a36ba19874ae74e8f81a57e3489 100644 (file)
--- a/quartus/project_gen.tcl
+++ b/quartus/project_gen.tcl
@@ -122,7 +122,7 @@ if {$make_assignments} {
 
        #rs232
        set_location_assignment PIN_D22 -to txd
-       set_location_assignment PIN_D23 -to rxd
+       #set_location_assignment PIN_D23 -to rxd
 
        set_global_assignment -name FMAX_REQUIREMENT "33.33 MHz" -section_id sys_clk
        set_instance_assignment -name CLOCK_SETTINGS sys_clk -to sys_clk

diff --git a/src/calc.vhd b/src/calc.vhd
index bd4e903f80c51dd859479a9dd96270054c6309a0..3c9031798464eaea45e4b9dfd5384dc5d0a569ee 100644 (file)
--- a/src/calc.vhd
+++ b/src/calc.vhd
@@ -16,7 +16,7 @@ entity calc is
                -- btnA
                -- TODO: pins
                -- rs232
-               rxd : in std_logic;
+               --rxd : in std_logic;
                txd : out std_logic;
                -- vga
                vsync_n : out std_logic;
@@ -61,11 +61,10 @@ architecture top of calc is
        -- debouncing
        signal sys_res_n_sync : std_logic;
        -- rs232
-       signal rx_new, rxd_sync : std_logic;
-       signal rx_data : std_logic_vector (7 downto 0);
+       --signal rx_new, rxd_sync : std_logic;
+       --signal rx_data : std_logic_vector (7 downto 0);
        signal tx_new, tx_done : std_logic;
        signal tx_data : std_logic_vector (7 downto 0);
-       signal txd_out : std_logic;
 begin
        -- vga/ipcore
        textmode_vga_inst : entity work.textmode_vga(struct)
@@ -178,7 +177,10 @@ begin
                s_backspace => s_backspace,
                -- parser
                do_it => do_it,
-               finished => finished
+               finished => finished,
+               -- test: uart_tx
+               tx_data => tx_data,
+               tx_new => tx_new
        );
 
        -- ps/2
@@ -213,31 +215,31 @@ begin
        );
 
        -- synchronizer fuer rxd
-       sync_rxd_inst : entity work.sync(beh)
-       generic map (
-               SYNC_STAGES => 2,
-               RESET_VALUE => '1'
-       )
-       port map (
-               sys_clk => sys_clk,
-               sys_res_n => sys_res_n_sync,
-               data_in => rxd,
-               data_out => rxd_sync
-       );
+       --sync_rxd_inst : entity work.sync(beh)
+       --generic map (
+       --      SYNC_STAGES => 2,
+       --      RESET_VALUE => '1'
+--     )
+       --port map (
+       --      sys_clk => sys_clk,
+       --      sys_res_n => sys_res_n_sync,
+       --      data_in => rxd,
+       --      data_out => rxd_sync
+       --);
 
        -- rs232-rx
-       rs232rx_inst : entity work.uart_rx(beh)
-       generic map (
-               CLK_FREQ => 33330000,
-               BAUDRATE => 115200
-       )
-       port map (
-               sys_clk => sys_clk,
-               sys_res_n => sys_res_n_sync,
-               rxd => rxd_sync,
-               rx_data => rx_data,
-               rx_new => rx_new
-       );
+       --rs232rx_inst : entity work.uart_rx(beh)
+       --generic map (
+       --      CLK_FREQ => 33330000,
+       --      BAUDRATE => 115200
+       --)
+       --port map (
+       --      sys_clk => sys_clk,
+       --      sys_res_n => sys_res_n_sync,
+       --      rxd => rxd_sync,
+       --      rx_data => rx_data,
+       --      rx_new => rx_new
+       --);
 
        -- rs232-tx
        rs232tx_inst : entity work.uart_tx(beh)
@@ -248,7 +250,7 @@ begin
        port map (
                sys_clk => sys_clk,
                sys_res_n => sys_res_n,
-               txd => txd_out,
+               txd => txd,
                tx_data => tx_data,
                tx_new => tx_new,
                tx_done => tx_done

diff --git a/src/scanner.vhd b/src/scanner.vhd
index 1710dc437888bae405c9fe804fcf1827ae4f450d..fde57048fe8c8da0aea576b2be3425ffba88eafb 100644 (file)
--- a/src/scanner.vhd
+++ b/src/scanner.vhd
@@ -18,7 +18,10 @@ entity scanner is
                s_backspace : out std_logic;
                -- Parser
                do_it : out std_logic;
-               finished : in std_logic
+               finished : in std_logic;
+               -- test: uart-tx
+               tx_data : out std_logic_vector(7 downto 0);
+               tx_new : out std_logic
        );
 end entity scanner;
 
@@ -29,11 +32,15 @@ architecture beh of scanner is
        signal s_take_int, s_take_next : std_logic;
        signal s_backspace_int, s_backspace_next : std_logic;
        signal do_it_int, do_it_next : std_logic;
+       signal tx_data_int, tx_data_next : std_logic_vector(7 downto 0);
+       signal tx_new_int, tx_new_next : std_logic;
 begin
        s_char <= s_char_int;
        s_take <= s_take_int;
        s_backspace <= s_backspace_int;
        do_it <= do_it_int;
+       tx_new <= tx_new_int;
+       tx_data <= tx_data_int;
 
        process(sys_clk, sys_res_n)
        begin
@@ -45,6 +52,8 @@ begin
                        s_take_int <= '0';
                        s_backspace_int <= '0';
                        do_it_int <= '0';
+                       tx_new_int <= '0';
+                       tx_data_int <= (others => '0');
                elsif rising_edge(sys_clk) then
                        -- internal
                        state_int <= state_next;
@@ -53,13 +62,17 @@ begin
                        s_take_int <= s_take_next;
                        s_backspace_int <= s_backspace_next;
                        do_it_int <= do_it_next;
+                       tx_new_int <= tx_new_next;
+                       tx_data_int <= tx_data_next;
                end if;
        end process;
 
        -- next state
-       process(state_int, new_data, data, finished, s_done)
+       process(state_int, new_data, data, finished, s_done, tx_data_int)
        begin
                state_next <= state_int;
+               tx_new_next <= '0';
+               tx_data_next <= tx_data_int;
 
                case state_int is
                        when SIDLE =>
@@ -106,6 +119,8 @@ begin
                                end if;
                        when SENTER =>
                                if finished = '1' then
+                                       tx_new_next <= '1';
+                                       tx_data_next <= x"42";
                                        state_next <= SIDLE;
                                end if;
                end case;