uart_rx: ein prozessmodell. spart weitere 3 logic elements :P

[hwmod.git] / src / sp_ram.vhd

diff --git a/src/sp_ram.vhd b/src/sp_ram.vhd
index de0f66892b3981fe84b63504dfa80c485bee5558..66b23d289507da736ed0975d84071e791a4e8d18 100644 (file)
--- a/src/sp_ram.vhd
+++ b/src/sp_ram.vhd
@@ -19,9 +19,8 @@ end entity sp_ram;
 
 architecture beh of sp_ram is
        subtype RAM_ENTRY_TYPE is hbyte;
-       type RAM_TYPE is array (1 to (2 ** ADDR_WIDTH)) of RAM_ENTRY_TYPE;
-       signal ram : RAM_TYPE := (1 => x"41", 2 => x"42", 3 => x"43", 4 => x"44",
-       5 => x"45", 6 => x"46", 7 => x"47", 8 => x"48", 9 => x"49", 10 => x"50", others => x"00");
+       type RAM_TYPE is array (0 to (2 ** ADDR_WIDTH)-1) of RAM_ENTRY_TYPE;
+       signal ram : RAM_TYPE := (others => x"00");
 begin
        process(sys_clk)
        begin