library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.gen_pkg.all;

-- "synchronous single port RAM
entity sp_ram is
	generic (
		ADDR_WIDTH : integer range 1 to integer'high
	);
	port (
		sys_clk : in std_logic;
		address : in std_logic_vector(ADDR_WIDTH - 1 downto 0);
		data_out : out hbyte;
		wr : in std_logic;
		data_in : in hbyte
	);
end entity sp_ram;

architecture beh of sp_ram is
	subtype RAM_ENTRY_TYPE is hbyte;
	type RAM_TYPE is array (0 to (2 ** ADDR_WIDTH)-1) of RAM_ENTRY_TYPE;
	signal ram : RAM_TYPE := (others => x"00");
begin
	process(sys_clk)
	begin
		if rising_edge(sys_clk) then
			data_out <= ram(to_integer(unsigned(address)));
			if wr = '1' then
				ram(to_integer(unsigned(address))) <= data_in;
			end if;
		end if;
	end process;
end architecture beh;