uart_rx: ein prozessmodell. spart weitere 3 logic elements :P

[hwmod.git] / src / sp_ram.vhd

diff --git a/src/sp_ram.vhd b/src/sp_ram.vhd
index 5c9b66b2e15df2417e8c5e4e5dd1233a024968e8..66b23d289507da736ed0975d84071e791a4e8d18 100644 (file)
--- a/src/sp_ram.vhd
+++ b/src/sp_ram.vhd
@@ -19,8 +19,8 @@ end entity sp_ram;
 
 architecture beh of sp_ram is
        subtype RAM_ENTRY_TYPE is hbyte;
-       type RAM_TYPE is array (1 to (2 ** ADDR_WIDTH)) of RAM_ENTRY_TYPE;
-       signal ram : RAM_TYPE := (others => x"41");
+       type RAM_TYPE is array (0 to (2 ** ADDR_WIDTH)-1) of RAM_ENTRY_TYPE;
+       signal ram : RAM_TYPE := (others => x"00");
 begin
        process(sys_clk)
        begin