uart_rx: ein prozessmodell. spart weitere 3 logic elements :P

[hwmod.git] / src / sp_ram.vhd

diff --git a/src/sp_ram.vhd b/src/sp_ram.vhd
index 4d39020db802fbca901b720e72ba6143a3bb38f2..66b23d289507da736ed0975d84071e791a4e8d18 100644 (file)
--- a/src/sp_ram.vhd
+++ b/src/sp_ram.vhd
@@ -19,7 +19,7 @@ end entity sp_ram;
 
 architecture beh of sp_ram is
        subtype RAM_ENTRY_TYPE is hbyte;
-       type RAM_TYPE is array (1 to (2 ** ADDR_WIDTH)) of RAM_ENTRY_TYPE;
+       type RAM_TYPE is array (0 to (2 ** ADDR_WIDTH)-1) of RAM_ENTRY_TYPE;
        signal ram : RAM_TYPE := (others => x"00");
 begin
        process(sys_clk)