rx_new : in std_logic;
-- History
- d_zeile : out hzeile;
- d_spalte : out hspalte;
- d_get : out std_logic;
- d_done : in std_logic;
- d_char : in hbyte
+ pc_zeile : out hzeile;
+ pc_spalte : out hspalte;
+ pc_get : out std_logic;
+ pc_busy : in std_logic; --signals if the history module actually grants our request.
+ pc_done : in std_logic;
+ pc_char : in hbyte
);
end entity pc_communication;
architecture beh of pc_communication is
- signal spalte, spalte_next : integer range 1 to hspalte_max + 1;
- signal zeile , zeile_next : integer range 1 to hzeile_max + 1;
+ signal spalte, spalte_next : integer range 1 to HSPALTE_MAX + 1;
+ signal zeile , zeile_next : integer range 1 to HZEILE_MAX + 1;
signal get, get_next : std_logic;
signal new_i, new_i_next : std_logic;
signal tx_done_i, tx_done_i_next : std_logic;
begin
- d_zeile <= hzeile(std_logic_vector(to_unsigned(zeile,7)));
- d_spalte <= hspalte(std_logic_vector(to_unsigned(spalte,7)));
- d_get <= get;
+ pc_zeile <= hzeile(std_logic_vector(to_unsigned(zeile,7)));
+ pc_spalte <= hspalte(std_logic_vector(to_unsigned(spalte,7)));
+ pc_get <= get;
tx_new <= new_i;
tx_done_i_next <= tx_done;
tx_data <= tx_data_i;
end if;
end process sync;
- output_pc : process (state, zeile, spalte, tx_data_i, tx_done_i, d_char)
+ output_pc : process (state, zeile, spalte, tx_data_i, tx_done_i, pc_char)
begin
get_next <= '0';
new_i_next <= '0';
when FETCH =>
get_next <= '1';
when WAIT_HIST =>
- tx_data_i_next <= d_char;
+ tx_data_i_next <= pc_char;
when FORWARD =>
new_i_next <= '1';
when WAIT_UART =>
- null;
+ new_i_next <= '1';
when UART_DONE =>
- if tx_data_i = x"00" or spalte = hspalte_max then
+ if tx_data_i = x"00" or spalte = HSPALTE_MAX then
+ tx_data_i_next <= x"0a";
zeile_next <= zeile + 1;
spalte_next <= 1;
- if zeile = hzeile_max then
+ if zeile = HZEILE_MAX then
zeile_next <= 1;
end if;
else
end case;
end process output_pc;
- next_state_pc : process (btn_a, d_done, rx_new, rx_data, spalte, state, tx_data_i ,tx_done_i, zeile)
+ next_state_pc : process (btn_a, pc_busy, pc_done, rx_new, rx_data, spalte,
+ state, tx_data_i ,tx_done_i, zeile)
begin
state_next <= state;
case state is
when IDLE =>
- if (rx_new = '1' and rx_data = x"0a" ) or btn_a = '1' then
+-- if (rx_new = '1' and rx_data = x"0a") or btn_a = '0' then
+ if (rx_new = '1') or btn_a = '0' then
state_next <= FETCH;
end if;
when FETCH =>
- state_next <= WAIT_HIST;
+ if pc_busy = '1' then
+ state_next <= WAIT_HIST;
+ else
+ state_next <= FETCH;
+ end if;
when WAIT_HIST =>
- if (d_done = '1') then
+ if (pc_done = '1') then
state_next <= FORWARD;
end if;
when FORWARD =>
state_next <= UART_DONE;
end if;
when UART_DONE =>
- if (tx_data_i = x"00" or spalte = hspalte_max) and
- zeile = hzeile_max then
+ if (tx_data_i = x"00" or spalte = HSPALTE_MAX) and
+ zeile = HZEILE_MAX then
state_next <= IDLE;
else
state_next <= FETCH;