top-level: ansatz fuer minimales setup inkl. geruest fuer history- und displaymodul...

[hwmod.git] / src / calc.vhd

diff --git a/src/calc.vhd b/src/calc.vhd
index 7347002dcd823619e8d00e7ef18358d3f9a41645..922a2a6481d136a21d4a69424d92b93f28920334 100644 (file)
--- a/src/calc.vhd
+++ b/src/calc.vhd
@@ -1,63 +1,70 @@
--- TODO: dient im moment nur als "fake top entity"
 library ieee;
 use ieee.std_logic_1164.all;
 use ieee.numeric_std.all;
 use work.gen_pkg.all;
+use work.textmode_vga_component_pkg.all;
+use work.textmode_vga_pkg.all;
+use work.textmode_vga_platform_dependent_pkg.all;
+use work.ps2_keyboard_controller_pkg.all;
 
 entity calc is
-       port
-       (
+       port (
                sys_clk : in std_logic;
-               sys_res_n : in std_logic
+               sys_res_n : in std_logic;
+               -- btnA
+               -- TODO: pins
+               -- rs232
+               -- TODO: pins
+               -- vga
+               vsync_n : out std_logic;
+               hsync_n : out std_logic;
+               r : out std_logic_vector(RED_BITS - 1 downto 0);
+               g : out std_logic_vector(GREEN_BITS - 1 downto 0);
+               b : out std_logic_vector(BLUE_BITS - 1 downto 0);
+               -- ps/2
+               ps2_clk : inout std_logic;
+               ps2_data : inout std_logic
        );
 end entity calc;
 
 architecture top of calc is
-       component alu is
-               port
-               (
-                       sys_clk : in std_logic;
-                       sys_res_n : in std_logic;
-                       opcode : in alu_ops;
-                       op1 : in csigned;
-                       op2 : in csigned;
-                       op3 : out csigned;
-                       do_calc : in std_logic;
-                       calc_done : out std_logic
-               );
-       end component alu;
-
-       signal do_calc, calc_done : std_logic;
-       signal opcode : alu_ops;
-       signal op1, op2, op3 : csigned;
+       -- vga
+       signal vga_clk, free : std_logic;
+       signal command : std_logic_vector(COMMAND_SIZE - 1 downto 0);
+       signal command_data : std_logic_vector(3 * COLOR_SIZE + CHAR_SIZE -1 downto 0);
 begin
-       aluc : alu
-       port map
-       (
+       -- vga/ipcore
+       textmode_vga_inst : entity work.textmode_vga(struct)
+       generic map (
+               VGA_CLK_FREQ => 25000000,
+               BLINK_INTERVAL_MS => 500,
+               SYNC_STAGES => 2
+       )
+       port map (
                sys_clk => sys_clk,
                sys_res_n => sys_res_n,
-               do_calc => do_calc,
-               calc_done => calc_done,
-               op1 => op1,
-               op2 => op2,
-               op3 => op3,
-               opcode => opcode
+               command => command,
+               command_data => command_data,
+               free => free,
+               vga_clk => vga_clk,
+               vga_res_n => sys_res_n,
+               vsync_n => vsync_n,
+               hsync_n => hsync_n,
+               r => r,
+               g => g,
+               b => b
        );
 
-       process (sys_clk, sys_res_n)
-       begin
-               if sys_res_n = '0' then
-                       op1 <= (others => '0');
-                       opcode <= NOP;
-                       op2 <= (others => '0');
-                       do_calc <= '0';
-               elsif rising_edge(sys_clk) then
-                       op1 <= op3;
-                       opcode <= DIV;
-                       op2 <= to_signed(2,CBITS);
+       -- pll fuer vga
+       vpll_inst : entity work.vpll(syn)
+       port map (
+               inclk0 => sys_clk,
+               c0 => vga_clk
+       );
 
-                       do_calc <= calc_done;
-               end if;
-       end process;
+       -- TODO: display
+       -- TODO: history
+       -- TODO: scanner
+       -- TODO: ps/2
 end architecture top;