library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.gen_pkg.all;
use work.textmode_vga_component_pkg.all;
use work.textmode_vga_pkg.all;
use work.textmode_vga_platform_dependent_pkg.all;
use work.ps2_keyboard_controller_pkg.all;

entity calc is
	port (
		sys_clk : in std_logic;
		sys_res_n : in std_logic;
		-- btnA
		-- TODO: pins
		-- rs232
		-- TODO: pins
		-- vga
		vsync_n : out std_logic;
		hsync_n : out std_logic;
		r : out std_logic_vector(RED_BITS - 1 downto 0);
		g : out std_logic_vector(GREEN_BITS - 1 downto 0);
		b : out std_logic_vector(BLUE_BITS - 1 downto 0);
		-- ps/2
		ps2_clk : inout std_logic;
		ps2_data : inout std_logic
	);
end entity calc;

architecture top of calc is
	-- vga
	signal vga_clk, free : std_logic;
	signal command : std_logic_vector(COMMAND_SIZE - 1 downto 0);
	signal command_data : std_logic_vector(3 * COLOR_SIZE + CHAR_SIZE -1 downto 0);
begin
	-- vga/ipcore
	textmode_vga_inst : entity work.textmode_vga(struct)
	generic map (
		VGA_CLK_FREQ => 25000000,
		BLINK_INTERVAL_MS => 500,
		SYNC_STAGES => 2
	)
	port map (
		sys_clk => sys_clk,
		sys_res_n => sys_res_n,
		command => command,
		command_data => command_data,
		free => free,
		vga_clk => vga_clk,
		vga_res_n => sys_res_n,
		vsync_n => vsync_n,
		hsync_n => hsync_n,
		r => r,
		g => g,
		b => b
	);

	-- pll fuer vga
	vpll_inst : entity work.vpll(syn)
	port map (
		inclk0 => sys_clk,
		c0 => vga_clk
	);

	-- TODO: display
	-- TODO: history
	-- TODO: scanner
	-- TODO: ps/2
end architecture top;