cleanup pc communication

[hwmod.git] / src / beh_pc_communication_tb.vhd

diff --git a/src/beh_pc_communication_tb.vhd b/src/beh_pc_communication_tb.vhd
index 0775e5e28f8915c8a4b8286f23beaa7cc8663ae1..03d1d62cac108c8c6663047136bc9fb56a53b20a 100644 (file)
--- a/src/beh_pc_communication_tb.vhd
+++ b/src/beh_pc_communication_tb.vhd
@@ -29,7 +29,7 @@ architecture sim of beh_pc_communication_tb is
                signal d_spalte : hspalte;
                signal d_char : hbyte;
 begin
-       -- display
+       -- pc_communication
        inst : entity work.pc_communication(beh)
        port map (
                sys_clk => sys_clk,
@@ -74,18 +74,21 @@ begin
        begin
                --take control of the situation.
                d_char <= (others => '0');
+               d_done <= '0';
                wait until sys_res_n = '1';
 
                while not endfile (f) loop
                        readline(f, l);
+                       buf := l.all;
                        i := 1;
                        while i < l'length loop
-                               wait until rising_edge(d_get);
                                d_done <= '0';
+                               wait until rising_edge(d_get);
                                d_char <= (others => '0');
-                               wait for 90 ns;
+                               wait for 300 ns;
 
                                d_char <= hbyte(std_logic_vector(to_unsigned(character'pos(buf(i)),8)));
+                               i := i + 1;
                                d_done <= '1';
                                wait for 30 ns;
                                
@@ -98,11 +101,10 @@ begin
        stub_uart : process
        begin
                tx_done <= '0';
+               wait until sys_res_n = '1';
                while true loop
-                       wait until sys_res_n = '1';
-
-                       wait until rising_edge(tx_new);
                        tx_done <= '0';
+                       wait until rising_edge(tx_new);
                        wait for 300 ns;
                        tx_done <= '1';
                        wait for 30 ns;
@@ -115,17 +117,14 @@ begin
                -- we only simulate pressing of button a by now!
                sys_res_n <= '0';
                btn_a <= '0';
-               tx_data <= ( others => '0');
                rx_data <= ( others => '0');
-               d_zeile <= ( others => '0');
-               d_spalte <= ( others => '0');
                rx_new <= '0';
                
                wait for 90 ns;
                sys_res_n <= '1';
                wait for 30 ns;
                btn_a <= '1';
-               wait for 15 ns;
+               wait for 30 ns;
                btn_a <= '0';
                wait;
                --wait for 1000 ns;