library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.gen_pkg.all;
use work.textmode_vga_component_pkg.all;
use work.textmode_vga_pkg.all;
use work.textmode_vga_platform_dependent_pkg.all;

-- this is for test file io
use std.textio.all;

entity beh_pc_communication_tb is
end entity beh_pc_communication_tb;

architecture sim of beh_pc_communication_tb is
		type byte_file_type is file of hbyte;
		subtype my_string is string(1 to 720);
		signal sys_clk : std_logic;
		signal sys_res_n : std_logic;
		signal btn_a : std_logic;
		signal tx_new : std_logic;
		signal tx_done : std_logic;
		signal rx_new : std_logic;
		signal d_get : std_logic;
		signal d_done : std_logic;
		signal rx_data, tx_data : std_logic_vector(7 downto 0);

		signal d_zeile : hzeile;
		signal d_spalte : hspalte;
		signal d_char : hbyte;
begin
	-- pc_communication
	inst : entity work.pc_communication(beh)
	port map (
		sys_clk => sys_clk,
		sys_res_n => sys_res_n,

		--button
		btn_a => btn_a,

		--uart_tx
		tx_data => tx_data,
		tx_new => tx_new,
		tx_done => tx_done,

		--uart_rx
		rx_data => rx_data,
		rx_new => rx_new,

		-- History
		d_zeile => d_zeile,
		d_spalte => d_spalte,
		d_get => d_get,
		d_done => d_done,
		d_char => d_char
	);

	clk : process
	begin
		sys_clk <= '0';
		wait for 15 ns;
		sys_clk <= '1';
		wait for 15 ns;
	end process clk;

	stub_history : process
		file f : text open read_mode is "../../src/pc_communication.test";
		--variable rb : hbyte;
		variable rb : character;
		variable good : boolean;
		variable i : integer;
		variable buf : my_string;
		variable l : line;
	begin
		--take control of the situation.
		d_char <= (others => '0');
		d_done <= '0';
		wait until sys_res_n = '1';

		while not endfile (f) loop
			readline(f, l);
			buf := l.all;
			i := 1;
			while i < l'length loop
				d_done <= '0';
				wait until rising_edge(d_get);
				d_char <= (others => '0');
				wait for 300 ns;

				d_char <= hbyte(std_logic_vector(to_unsigned(character'pos(buf(i)),8)));
				i := i + 1;
				d_done <= '1';
				wait for 30 ns;
				
			end loop;
		end loop;

		assert not endfile(f) report "test beendet" severity failure;
	end process stub_history;

	stub_uart : process
	begin
		tx_done <= '0';
		wait until sys_res_n = '1';
		while true loop
			tx_done <= '0';
			wait until rising_edge(tx_new);
			wait for 300 ns;
			tx_done <= '1';
			wait for 30 ns;
		end loop;
	end process stub_uart;

	reset_and_button : process
	begin
		-- init & reset
		-- we only simulate pressing of button a by now!
		sys_res_n <= '0';
		btn_a <= '0';
		rx_data <= ( others => '0');
		rx_new <= '0';
		
		wait for 90 ns;
		sys_res_n <= '1';
		wait for 30 ns;
		btn_a <= '1';
		wait for 30 ns;
		btn_a <= '0';
		wait;
		--wait for 1000 ns;
		--assert false report "test beendet" severity failure;
	end process reset_and_button;

end architecture sim;