2 use ieee.std_logic_1164.all;
3 use ieee.numeric_std.all;
9 sys_clk : in std_logic;
10 sys_res_n : in std_logic;
12 new_data : in std_logic;
13 data : in std_logic_vector(7 downto 0);
16 s_take : out std_logic;
17 s_done : in std_logic;
18 s_backspace : out std_logic;
20 do_it : out std_logic;
21 finished : in std_logic
25 architecture beh of scanner is
26 type SCANNER_STATE is (SIDLE, SREAD, SMOD, STAKE, SDEL, SENTER);
27 signal state_int, state_next : SCANNER_STATE;
28 signal s_char_int, s_char_next : hbyte;
29 signal s_take_int, s_take_next : std_logic;
30 signal s_backspace_int, s_backspace_next : std_logic;
31 signal do_it_int, do_it_next : std_logic;
35 s_backspace <= s_backspace_int;
38 process(sys_clk, sys_res_n)
40 if sys_res_n = '0' then
44 s_char_int <= (others => '0');
46 s_backspace_int <= '0';
48 elsif rising_edge(sys_clk) then
50 state_int <= state_next;
52 s_char_int <= s_char_next;
53 s_take_int <= s_take_next;
54 s_backspace_int <= s_backspace_next;
55 do_it_int <= do_it_next;
60 process(state_int, new_data, data, finished, s_done)
61 function valid_char (x : std_logic_vector(7 downto 0)) return boolean is
66 when x"30" | x"31" | x"32" | x"33" | x"34" => y := true;
68 when x"35" | x"36" | x"37" | x"38" | x"39" => y := true;
70 when x"2a" | x"2b" | x"2d" | x"2f" => y := true;
71 when others => y := false;
76 state_next <= state_int;
80 if new_data = '1' and finished = '0' and s_done = '0' then
85 when x"e0" => state_next <= SMOD;
86 when x"0e" => state_next <= SDEL;
87 when x"1c" => state_next <= SENTER;
88 when x"20" => state_next <= STAKE;
89 when others => state_next <= SIDLE;
92 if new_data = '1' then
93 if valid_char(data) then
104 if finished = '1' then
111 process(state_int, data)
113 s_char_next <= (others => '0');
115 s_backspace_next <= '0';
127 s_char_next <= hbyte(data);
130 s_backspace_next <= '1';
135 end architecture beh;