2 use ieee.std_logic_1164.all;
3 use ieee.numeric_std.all;
6 entity pc_communication is
8 sys_clk : in std_logic;
9 sys_res_n : in std_logic;
15 tx_data : out std_logic_vector(7 downto 0);
16 tx_new : out std_logic;
17 tx_done : in std_logic;
20 rx_data : in std_logic_vector(7 downto 0); --not really required
21 rx_new : in std_logic;
25 d_spalte : out hspalte;
26 d_get : out std_logic;
27 d_done : in std_logic;
30 end entity pc_communication;
32 architecture beh of pc_communication is
33 signal push_history, push_history_next : std_logic;
35 signal spalte, spalte_next : integer range 1 to 73;
36 signal zeile , zeile_next : integer range 1 to 73;
37 signal spalte_up, spalte_up_next : std_logic;
38 signal get, get_next : std_logic;
39 signal new_i, new_i_next : std_logic;
40 signal tx_done_i, tx_done_i_next : std_logic;
41 signal d_done_i : std_logic;
42 signal s_done, s_done_next : std_logic;
44 signal char, char_next : hbyte;
45 signal char_en : std_logic;
46 type STATE_PC is (IDLE, FETCH, FORWARD, DONE);
47 signal state, state_next : STATE_PC ;
52 d_zeile <= hzeile(std_logic_vector(to_unsigned(zeile,7)));
53 d_spalte <= hspalte(std_logic_vector(to_unsigned(spalte,7)));
58 tx_done_i_next <= tx_done;
60 sync: process (sys_clk, sys_res_n)
62 if sys_res_n = '0' then
69 tx_data <= "00000000";
73 elsif rising_edge(sys_clk) then
74 push_history <= push_history_next;
75 spalte <= spalte_next;
80 tx_done_i <= tx_done_i_next;
81 spalte_up <= spalte_up_next;
82 s_done <= s_done_next;
83 if (char_en = '1') then
89 async_push_history : process (rx_new, rx_data, btn_a)
92 if rx_data = X"41" then
93 push_history_next <= '1';
95 push_history_next <= '0';
97 elsif btn_a = '1' then
98 push_history_next <= '1';
100 push_history_next <= '0';
102 end process async_push_history;
104 output_pc : process (state, zeile, spalte, char, tx_done_i, spalte_up, spalte, zeile)
109 spalte_up_next <= '0';
111 spalte_next <= spalte;
114 if (spalte_up = '1') then
115 if (spalte > 72) then
116 if zeile + 1 > 50 then
119 s_done_next <= '1'; --lets assume this false
120 --assert false severity failure;
123 zeile_next <= zeile + 1;
126 spalte_next <= spalte + 1; --overflow here!
141 if (tx_done_i = '1') then
142 spalte_up_next <= '1';
148 end process output_pc;
150 next_state_pc : process (rx_new, btn_a, d_done, tx_done_i, s_done)
154 if rx_new = '1' or btn_a = '1' then
158 if (d_done = '1') then
159 state_next <= FORWARD;
160 elsif (s_done = '1') then
164 if (tx_done_i = '1') then
170 end process next_state_pc;
172 end architecture beh;