Statemachine now returns to idle.

The state machine now is capable to stop dumping memory.

diff --git a/src/pc_communication.vhd b/src/pc_communication.vhd
index 44e43cdfc0ad6616cc52295ef3d1b299eb635348..4e2cc41a0de87b4291976f85c8b4da5b91d24d6f 100644 (file)
--- a/src/pc_communication.vhd
+++ b/src/pc_communication.vhd
@@ -39,6 +39,7 @@ architecture beh of pc_communication is
        signal new_i, new_i_next : std_logic;
        signal tx_done_i, tx_done_i_next : std_logic;
        signal d_done_i : std_logic;
+       signal s_done, s_done_next : std_logic;
 
        signal char, char_next : hbyte;
        signal char_en : std_logic;
@@ -68,6 +69,7 @@ begin
                        tx_data <= "00000000";
                        spalte_up <= '0';
                        tx_done_i <= '0';
+                       s_done <= '0';
                elsif rising_edge(sys_clk) then
                        push_history <= push_history_next;
                        spalte <= spalte_next;
@@ -77,35 +79,13 @@ begin
                        new_i <= new_i_next;
                        tx_done_i <= tx_done_i_next;
                        spalte_up <= spalte_up_next;
+                       s_done <= s_done_next;
                        if (char_en = '1') then
                                char <= char_next;
                        end if;
                end if;
        end process sync;
 
-       process (spalte_up, spalte, zeile)
-       begin
-               if (spalte_up = '1') then
-                       if (spalte > 72) then
-                               if zeile + 1 > 50 then 
-                                       spalte_next <= 1;
-                                       zeile_next <= 1;
-                                       --done <= '1'; lets assume this false
-                                       assert false severity failure;
-                               else
-                                       spalte_next <= 1;
-                                       zeile_next <= zeile + 1;
-                               end if;
-                       else
-                               spalte_next <= spalte + 1; --overflow here!
-                               zeile_next <= zeile;
-                       end if;
-               else
-                       spalte_next <= spalte;
-                       zeile_next <= zeile;
-               end if;
-       end process;
-
        async_push_history : process (rx_new, rx_data, btn_a)
        begin
                if rx_new = '1' then
@@ -121,11 +101,33 @@ begin
                end if;
        end process async_push_history;
 
-       output_pc : process (state, zeile, spalte, char, tx_done_i)
+       output_pc : process (state, zeile, spalte, char, tx_done_i, spalte_up, spalte, zeile)
        begin
                get_next <= '0';
                new_i_next <= '0';
+
                spalte_up_next <= '0';
+               s_done_next <= '0';
+               spalte_next <= spalte;
+               zeile_next <= zeile;
+
+               if (spalte_up = '1') then
+                       if (spalte > 72) then
+                               if zeile + 1 > 50 then 
+                                       spalte_next <= 1;
+                                       zeile_next <= 1;
+                                       s_done_next <= '1'; --lets assume this false
+                                       --assert false severity failure;
+                               else
+                                       spalte_next <= 1;
+                                       zeile_next <= zeile + 1;
+                               end if;
+                       else
+                               spalte_next <= spalte + 1; --overflow here!
+                               zeile_next <= zeile;
+                       end if;
+               end if;
+
                case state is
                        when IDLE =>
                                null;
@@ -139,22 +141,24 @@ begin
                                if (tx_done_i = '1') then
                                        spalte_up_next <= '1';
                                end if;
+
                        when DONE =>
                                null;
                end case;
        end process output_pc;
 
-       next_state_pc : process (rx_new, btn_a, d_done, tx_done_i)
+       next_state_pc : process (rx_new, btn_a, d_done, tx_done_i, s_done)
        begin
                case state is
                        when IDLE =>
                                if rx_new = '1' or btn_a = '1' then
                                        state_next <= FETCH;
-                                       
                                end if;
                        when FETCH =>
                                if (d_done = '1') then
                                        state_next <= FORWARD;
+                               elsif (s_done = '1') then
+                                       state_next <= IDLE;
                                end if;
                        when FORWARD =>
                                if (tx_done_i = '1') then