beautify
[hwmod.git] / src / history.vhd
1 library ieee;
2 use ieee.std_logic_1164.all;
3 use ieee.numeric_std.all;
4 use work.gen_pkg.all;
5
6 entity history is
7         port (
8                 sys_clk : in std_logic;
9                 sys_res_n : in std_logic;
10                 -- PC-komm
11                 pc_get :  in std_logic;
12                 pc_spalte : in hspalte;
13                 pc_zeile : in hzeile;
14                 pc_char : out hbyte;
15                 pc_done : out std_logic;
16                 pc_busy : out std_logic;
17                 -- Scanner
18                 s_char : in hbyte;
19                 s_take : in std_logic;
20                 s_done : out std_logic;
21                 s_backspace : in std_logic;
22                 -- Display
23                 d_new_eingabe : out std_logic;
24                 d_new_result : out std_logic;
25                 d_new_bs : out std_logic;
26                 d_zeile : in hzeile;
27                 d_spalte : in hspalte;
28                 d_get : in std_logic;
29                 d_done : out std_logic;
30                 d_char : out hbyte;
31                 -- Parser
32                 p_rget : in std_logic;
33                 p_rdone : out std_logic;
34                 p_read : out hbyte;
35                 p_wtake : in std_logic;
36                 p_wdone : out std_logic;
37                 p_write : in hbyte;
38                 p_finished : in std_logic
39         );
40 end entity history;
41
42 architecture beh of history is
43         type HISTORY_STATE is (SIDLE, S_S_INIT, S_S_WRITE, S_S_BS, S_S_DONE, S_S_FIN,
44                 S_D_INIT, S_D_READ, S_S_FIN_POSUP, S_P_READ, S_P_READ_DONE, S_P_WRITE,
45                 S_P_WRITE_DONE, S_P_DONE, S_INIT, S_S_CLEAR_NEXT0, S_S_CLEAR_NEXT1, S_PC_INIT, S_PC_READ);
46         signal state_int, state_next : HISTORY_STATE;
47         signal was_bs_int, was_bs_next : std_logic;
48         signal pos_int, pos_next : std_logic_vector(H_RAM_WIDTH - 1 downto 0);
49         signal s_done_int, s_done_next : std_logic;
50         signal s_cnt_int, s_cnt_next : hspalte;
51         signal d_new_eingabe_int, d_new_eingabe_next : std_logic;
52         signal d_new_result_int, d_new_result_next : std_logic;
53         signal d_new_bs_int, d_new_bs_next: std_logic;
54         signal d_done_int, d_done_next : std_logic;
55         signal d_char_int, d_char_next : hbyte;
56         signal p_rdone_int, p_rdone_next : std_logic;
57         signal p_wdone_int, p_wdone_next : std_logic;
58         signal p_read_int, p_read_next : hbyte;
59         signal p_sp_read_int, p_sp_read_next : hspalte;
60         signal p_sp_write_int, p_sp_write_next : hspalte;
61         signal pc_char_next ,pc_char_int : hbyte;
62         signal pc_done_next, pc_done_int : std_logic;
63         signal pc_busy_next, pc_busy_int : std_logic;
64
65         -- ram
66         signal address_next, address_int : std_logic_vector(H_RAM_WIDTH - 1 downto 0);
67         signal data_out, data_in_next, data_in_int : hbyte;
68         signal wr_next, wr_int : std_logic;
69 begin
70         s_done <= s_done_int;
71         d_new_eingabe <= d_new_eingabe_int;
72         d_new_result <= d_new_result_int;
73         d_new_bs <= d_new_bs_int;
74         d_done <= d_done_int;
75         d_char <= d_char_int;
76         p_rdone <= p_rdone_int;
77         p_wdone <= p_wdone_int;
78         p_read <= p_read_int;
79         pc_done <= pc_done_int;
80         pc_busy <= pc_busy_int;
81         pc_char <= pc_char_int;
82
83         process(sys_clk, sys_res_n)
84         begin
85                 if sys_res_n = '0' then
86                         -- internal
87                         state_int <= S_INIT;
88                         was_bs_int <= '0';
89                         pos_int <= (others => '0');
90                         -- out
91                         s_done_int <= '0';
92                         s_cnt_int <= (0 => '1', others => '0');
93                         d_new_result_int <= '0';
94                         d_new_eingabe_int <= '0';
95                         d_new_bs_int <= '0';
96                         d_done_int <= '0';
97                         d_char_int <= (others => '0');
98                         p_rdone_int <= '0';
99                         p_wdone_int <= '0';
100                         p_read_int <= (others => '0');
101                         p_sp_read_int <= (others => '0');
102                         p_sp_write_int <= std_logic_vector(to_unsigned(71,p_sp_write_int'length));
103
104                         pc_char_int  <= (others => '0');
105                         pc_done_int  <= '0';
106
107                         address_int <= (0 => '1', others => '0');
108                         data_in_int <= x"00";
109                         wr_int <= '0';
110                 elsif rising_edge(sys_clk) then
111                         -- internal
112                         state_int <= state_next;
113                         was_bs_int <= was_bs_next;
114                         pos_int <= pos_next;
115                         -- out
116                         s_done_int <= s_done_next;
117                         s_cnt_int <= s_cnt_next;
118                         d_new_result_int <= d_new_result_next;
119                         d_new_eingabe_int <= d_new_eingabe_next;
120                         d_new_bs_int <= d_new_bs_next;
121                         d_done_int <= d_done_next;
122                         d_char_int <= d_char_next;
123                         p_rdone_int <= p_rdone_next;
124                         p_wdone_int <= p_wdone_next;
125                         p_read_int <= p_read_next;
126                         p_sp_read_int <= p_sp_read_next;
127                         p_sp_write_int <= p_sp_write_next;
128
129                         pc_char_int <= pc_char_next;
130                         pc_done_int <= pc_done_next;
131
132                         address_int <= address_next;
133                         data_in_int <= data_in_next;
134                         wr_int <= wr_next;
135                 end if;
136         end process;
137
138         -- next state
139         process(state_int, d_get, pc_get, p_finished, s_take, s_backspace, was_bs_int,
140                 p_rget, p_wtake, pos_int, s_cnt_int)
141         begin
142                 state_next <= state_int;
143
144                 case state_int is
145                         when S_INIT =>
146                                 -- ganzen speicher clearen: fuer ausgabe am vga nicht umbedingt
147                                 -- noetig, aber spaetestens fuers dumpen per rs232
148                                 if pos_int = std_logic_vector(to_unsigned(H_RAM_SIZE,H_RAM_WIDTH)) then
149                                         state_next <= SIDLE;
150                                 end if;
151                         when SIDLE =>
152                                 -- S_S_FIN: tmp..
153                                 if s_take = '1' then
154                                         state_next <= S_S_INIT;
155                                 elsif p_rget = '1' then
156                                         state_next <= S_P_READ;
157                                 elsif p_wtake = '1' then
158                                         state_next <= S_P_WRITE;
159                                 elsif p_finished = '1' then
160                                         state_next <= S_S_FIN;
161                                 elsif d_get = '1' then
162                                         state_next <= S_D_INIT;
163                                 elsif pc_get = '1' then
164                                         state_next <= S_PC_INIT;
165                                 end if;
166                         when S_S_INIT =>
167                                 if s_backspace = '1' then
168                                         state_next <= S_S_BS;
169                                 else
170                                         state_next <= S_S_WRITE;
171                                 end if;
172                         when S_S_WRITE =>
173                                 state_next <= S_S_DONE;
174                         when S_S_BS =>
175                                 state_next <= S_S_DONE;
176                         when S_S_FIN =>
177                                 if p_finished = '0' then
178                                         state_next <= S_S_FIN_POSUP;
179                                 end if;
180                         when S_S_FIN_POSUP =>
181                                 state_next <= S_S_CLEAR_NEXT0;
182                         when S_S_CLEAR_NEXT0 =>
183                                 if s_cnt_int = hspalte(to_unsigned(71,hspalte'length)) then
184                                         state_next <= S_S_CLEAR_NEXT1;
185                                 end if;
186                         when S_S_CLEAR_NEXT1 =>
187                                 if s_cnt_int = hspalte(to_unsigned(71,hspalte'length)) then
188                                         state_next <= SIDLE;
189                                 end if;
190                         when S_S_DONE =>
191                                 if s_take = '0' then
192                                         state_next <= SIDLE;
193                                 end if;
194
195                         when S_D_INIT =>
196                                 state_next <= S_D_READ;
197                         when S_D_READ =>
198                                 if d_get = '0' then
199                                         state_next <= SIDLE;
200                                 end if;
201                         when S_PC_INIT =>
202                                 state_next <= S_PC_READ;
203                         when S_PC_READ =>
204                                 if d_get = '0' then
205                                         state_next <= SIDLE;
206                                 end if;
207                         when S_P_READ =>
208                                 state_next <= S_P_READ_DONE;
209                         when S_P_READ_DONE =>
210                                 if p_rget = '0' then
211                                         state_next <= S_P_DONE;
212                                 end if;
213                         when S_P_WRITE =>
214                                 state_next <= S_P_WRITE_DONE;
215                         when S_P_WRITE_DONE =>
216                                 if p_wtake = '0' then
217                                         state_next <= S_P_DONE;
218                                 end if;
219                         when S_P_DONE =>
220                                 state_next <= SIDLE;
221                 end case;
222         end process;
223
224         -- out
225         process(state_int, s_cnt_int, d_spalte, d_zeile, data_out, s_char, address_int,
226                         data_in_int, d_new_result_int, d_new_eingabe_int, d_new_bs_int,
227                         was_bs_int, s_take, pos_int, p_rdone_int, p_wdone_int, p_read_int,
228                         p_write, p_sp_read_int, p_sp_write_int, pc_char_int, pc_zeile, pc_spalte)
229                 variable addr_tmp : std_logic_vector(H_RAM_WIDTH - 1 downto 0);
230                 variable spalte_tmp : hspalte;
231                 variable mul_tmp : std_logic_vector((H_RAM_WIDTH*2) -1 downto 0);
232         begin
233                 s_done_next <= '0';
234                 s_cnt_next <= s_cnt_int;
235                 was_bs_next <= was_bs_int;
236                 pos_next <= pos_int;
237                 d_new_result_next <= d_new_result_int;
238                 d_new_eingabe_next <= d_new_eingabe_int;
239                 d_new_bs_next <= '0';
240                 d_done_next <= '0';
241                 d_char_next <= (others => '0');
242                 wr_next <= '0';
243                 address_next <= address_int;
244                 data_in_next <= data_in_int;
245                 pc_done_next <= '0';
246                 pc_char_next <= pc_char_int; --(others => '0');
247                 p_rdone_next <= p_rdone_int;
248                 p_wdone_next <= p_wdone_int;
249                 p_read_next <= p_read_int;
250                 p_sp_read_next <= p_sp_read_int;
251                 p_sp_write_next <= p_sp_write_int;
252
253                 case state_int is
254                         when S_INIT =>
255                                 wr_next <= '1';
256                                 address_next <= pos_int;
257                                 data_in_next <= (others => '0');
258                                 if pos_int = std_logic_vector(to_unsigned(H_RAM_SIZE,H_RAM_WIDTH)) then
259                                         pos_next <= (others => '0');
260                                 else
261                                         pos_next <= std_logic_vector(unsigned(pos_int) + to_unsigned(1,H_RAM_WIDTH));
262                                 end if;
263                         when SIDLE =>
264                                 d_new_result_next <= '0';
265                         when S_S_INIT =>
266                                 null;
267                         when S_S_WRITE =>
268                                 -- nur bei < 71 weiter machen
269                                 -- Hint: '/=' billiger als '<'
270                                 if unsigned(s_cnt_int) /= 71 then
271                                         wr_next <= '1';
272                                         address_next <= std_logic_vector(unsigned(pos_int) + unsigned(s_cnt_int));
273                                         data_in_next <= s_char;
274                                         s_cnt_next <= std_logic_vector(unsigned(s_cnt_int) + 1);
275                                 else
276                                         -- was_bs hier missbrauchen, um ein d_new_eingabe zu verhindern
277                                         was_bs_next <= '1';
278                                 end if;
279                         when S_S_BS =>
280                                 -- ab 1 darf nicht mehr dekrementiert werden
281                                 addr_tmp := (others => '0');
282                                 if unsigned(s_cnt_int) /= 1 then
283                                         addr_tmp(hspalte'length - 1 downto 0) := std_logic_vector(unsigned(s_cnt_int) - 1);
284                                         d_new_bs_next <= '1';
285                                 else
286                                         addr_tmp(hspalte'length - 1 downto 0) := s_cnt_int;
287                                 end if;
288                                 s_cnt_next <= addr_tmp(hspalte'length - 1 downto 0);
289                 
290                                 wr_next <= '1';
291                                 address_next <= std_logic_vector(unsigned(pos_int) + unsigned(addr_tmp));
292                                 data_in_next <= (others => '0');
293                                 was_bs_next <= '1';
294                         when S_S_FIN =>
295                                 s_cnt_next <= (0 => '1', others => '0');
296                                 d_new_result_next <= '1';
297                                 -- resetten der parser counter
298                                 p_sp_read_next <= (others => '0');
299                                 p_sp_write_next <= std_logic_vector(to_unsigned(71,p_sp_write_next'length));
300                         when S_S_FIN_POSUP =>
301                                 -- overflowcheck nach 50 berechnungen => wieder von vorne anfangen
302                                 if pos_int = std_logic_vector(to_unsigned(H_RAM_SIZE-142,H_RAM_WIDTH)) then
303                                         pos_next <= (others => '0');
304                                 else
305                                         pos_next <= std_logic_vector(unsigned(pos_int) + to_unsigned(142,H_RAM_WIDTH));
306                                 end if;
307                         when S_S_CLEAR_NEXT0 =>
308                                 -- die naechsten 142 bytes im speicher resetten
309                                 wr_next <= '1';
310                                 address_next <= std_logic_vector(unsigned(pos_int) + unsigned(s_cnt_int));
311                                 data_in_next <= (others => '0');
312                                 if s_cnt_int = hspalte(to_unsigned(71,hspalte'length)) then
313                                         s_cnt_next <= (0 => '1', others => '0');
314                                 else
315                                         s_cnt_next <= std_logic_vector(unsigned(s_cnt_int) + 1);
316                                 end if;
317                         when S_S_CLEAR_NEXT1 =>
318                                 -- die naechsten 142 bytes im speicher resetten
319                                 wr_next <= '1';
320                                 address_next <= std_logic_vector(unsigned(pos_int) + to_unsigned(71,H_RAM_WIDTH) + unsigned(s_cnt_int));
321                                 data_in_next <= (others => '0');
322                                 if s_cnt_int = hspalte(to_unsigned(71,hspalte'length)) then
323                                         s_cnt_next <= (0 => '1', others => '0');
324                                 else
325                                         s_cnt_next <= std_logic_vector(unsigned(s_cnt_int) + 1);
326                                 end if;
327                         when S_S_DONE =>
328                                 s_done_next <= '1';
329                                 if was_bs_int = '0' then
330                                         d_new_eingabe_next <= '1';
331                                 end if;
332                                 if s_take = '0' then
333                                         was_bs_next <= '0';
334                                 end if;
335
336                         when S_D_INIT =>
337                                 addr_tmp := (others => '0');
338                                 addr_tmp(hzeile'length - 1 downto 0) := d_zeile;
339                                 mul_tmp := std_logic_vector(unsigned(addr_tmp) * to_unsigned(71,H_RAM_WIDTH));
340                                 addr_tmp := mul_tmp((addr_tmp'length - 1) downto 0);
341                                 addr_tmp := std_logic_vector(unsigned(addr_tmp) + unsigned(d_spalte));
342                                 address_next <= addr_tmp;
343                                 d_new_eingabe_next <= '0';
344                                 d_new_result_next <= '0';
345                         when S_D_READ =>
346                                 d_char_next <= data_out;
347                                 d_done_next <= '1';
348
349                         when S_PC_INIT =>
350                                 addr_tmp := (others => '0');
351                                 addr_tmp(hzeile'length - 1 downto 0) := pc_zeile;
352                                 mul_tmp := std_logic_vector(unsigned(addr_tmp) * to_unsigned(71,H_RAM_WIDTH));
353                                 addr_tmp := mul_tmp((addr_tmp'length - 1) downto 0);
354                                 addr_tmp := std_logic_vector(unsigned(addr_tmp) + unsigned(pc_spalte));
355                                 address_next <= addr_tmp;
356                         when S_PC_READ =>
357                                 pc_char_next <= data_out;
358                                 pc_done_next <= '1';
359                         when S_P_READ =>
360                                 wr_next <= '0';
361                                 spalte_tmp := std_logic_vector(unsigned(p_sp_read_int) + 1);
362                                 p_sp_read_next <= spalte_tmp;
363                                 address_next <= std_logic_vector(unsigned(pos_int) + unsigned(spalte_tmp));
364                         when S_P_READ_DONE =>
365                                 p_rdone_next <= '1';
366                                 p_read_next <= data_out;
367
368                         when S_P_WRITE =>
369                                 wr_next <= '1';
370                                 data_in_next <= p_write;
371                                 spalte_tmp := std_logic_vector(unsigned(p_sp_write_int) - 1);
372                                 p_sp_write_next <= spalte_tmp;
373                                 address_next <= std_logic_vector(unsigned(pos_int) + to_unsigned(71,H_RAM_WIDTH) + unsigned(spalte_tmp));
374                         when S_P_WRITE_DONE =>
375                                 p_wdone_next <= '1';
376                         when S_P_DONE =>
377                                 p_rdone_next <= '0';
378                                 p_wdone_next <= '0';
379                 end case;
380         end process;
381
382         sp_ram_inst : entity work.sp_ram(beh)
383         generic map (
384                 ADDR_WIDTH => H_RAM_WIDTH
385         )
386         port map (
387                 sys_clk => sys_clk,
388                 address => address_int,
389                 data_out => data_out,
390                 wr => wr_int,
391                 data_in => data_in_int
392         );
393 end architecture beh;