src/history.vhd

   1 library ieee;
   2 use ieee.std_logic_1164.all;
   3 use ieee.numeric_std.all;
   4 use work.gen_pkg.all;
   5
   6 entity history is
   7         port (
   8                 sys_clk : in std_logic;
   9                 sys_res_n : in std_logic;
  10                 -- PC-komm
  11                 -- TODO: pins
  12                 -- Scanner
  13                 s_char : in hbyte;
  14                 s_take : in std_logic;
  15                 s_done : out std_logic;
  16                 s_backspace : in std_logic;
  17                 -- Display
  18                 d_new_eingabe : out std_logic;
  19                 d_new_result : out std_logic;
  20                 d_zeile : in hzeile;
  21                 d_spalte : in hspalte;
  22                 d_get : in std_logic;
  23                 d_done : out std_logic;
  24                 d_char : out hbyte;
  25                 -- Parser
  26                 -- TODO: pins
  27
  28                 -- TODO: tmp only!
  29                 do_it : in std_logic;
  30                 finished : out std_logic
  31         );
  32 end entity history;
  33
  34 architecture beh of history is
  35         type HISTORY_STATE is (SIDLE, S_S_INIT, S_S_WRITE, S_S_BS, S_S_DONE, S_S_FIN,
  36                 S_D_INIT, S_D_WRITE);
  37         signal state_int, state_next : HISTORY_STATE;
  38         signal s_done_int, s_done_next : std_logic;
  39         signal s_cnt_int, s_cnt_next : hspalte;
  40         signal d_new_eingabe_int, d_new_eingabe_next : std_logic;
  41         signal d_new_result_int, d_new_result_next : std_logic;
  42         signal d_done_int, d_done_next : std_logic;
  43         signal d_char_int, d_char_next : hbyte;
  44
  45         signal finished_int, finished_next : std_logic;
  46
  47         -- ram
  48         signal address_next, address_int : std_logic_vector(H_RAM_WIDTH - 1 downto 0);
  49         signal data_out, data_in_next, data_in_int : hbyte;
  50         signal wr_next, wr_int : std_logic;
  51 begin
  52         s_done <= s_done_int;
  53         d_new_eingabe <= d_new_eingabe_int;
  54         d_new_result <= d_new_result_int;
  55         d_done <= d_done_int;
  56         d_char <= d_char_int;
  57
  58         finished <= finished_int;
  59
  60         process(sys_clk, sys_res_n)
  61         begin
  62                 if sys_res_n = '0' then
  63                         -- internal
  64                         state_int <= SIDLE;
  65                         -- out
  66                         s_done_int <= '0';
  67                         s_cnt_int <= (0 => '1', others => '0');
  68                         d_new_result_int <= '0';
  69                         d_new_eingabe_int <= '0';
  70                         d_done_int <= '0';
  71                         d_char_int <= (others => '0');
  72
  73                         finished_int <= '0';
  74
  75                         address_int <= (0 => '1', others => '0');
  76                         data_in_int <= x"00";
  77                         wr_int <= '0';
  78                 elsif rising_edge(sys_clk) then
  79                         -- internal
  80                         state_int <= state_next;
  81                         -- out
  82                         s_done_int <= s_done_next;
  83                         s_cnt_int <= s_cnt_next;
  84                         d_new_result_int <= d_new_result_next;
  85                         d_new_eingabe_int <= d_new_eingabe_next;
  86                         d_done_int <= d_done_next;
  87                         d_char_int <= d_char_next;
  88
  89                         finished_int <= finished_next;
  90
  91                         address_int <= address_next;
  92                         data_in_int <= data_in_next;
  93                         wr_int <= wr_next;
  94                 end if;
  95         end process;
  96
  97         -- next state
  98         process(state_int, d_get, do_it, s_take, s_backspace)
  99         begin
 100                 state_next <= state_int;
 101
 102                 case state_int is
 103                         when SIDLE =>
 104                                 -- S_S_FIN: tmp..
 105                                 if s_take = '1' then
 106                                         state_next <= S_S_INIT;
 107                                 elsif do_it = '1' then
 108                                         state_next <= S_S_FIN;
 109                                 elsif d_get = '1' then
 110                                         state_next <= S_D_INIT;
 111                                 end if;
 112                         when S_S_INIT =>
 113                                 if s_backspace = '1' then
 114                                         state_next <= S_S_BS;
 115                                 else
 116                                         state_next <= S_S_WRITE;
 117                                 end if;
 118                         when S_S_WRITE | S_S_BS =>
 119                                 state_next <= S_S_DONE;
 120                         when S_S_FIN =>
 121                                 if do_it = '0' then
 122                                         state_next <= SIDLE;
 123                                 end if;
 124                         when S_S_DONE =>
 125                                 if s_take = '0' then
 126                                         state_next <= SIDLE;
 127                                 end if;
 128
 129                         when S_D_INIT =>
 130                                 state_next <= S_D_WRITE;
 131                         when S_D_WRITE =>
 132                                 if d_get = '0' then
 133                                         state_next <= SIDLE;
 134                                 end if;
 135                 end case;
 136         end process;
 137
 138         -- out
 139         process(state_int, s_cnt_int, d_spalte, data_out, s_char, address_int,
 140                 data_in_int, d_new_result_int, d_new_eingabe_int)
 141         begin
 142                 s_done_next <= '0';
 143                 s_cnt_next <= s_cnt_int;
 144                 d_new_result_next <= d_new_result_int;
 145                 d_new_eingabe_next <= d_new_eingabe_int;
 146                 d_done_next <= '0';
 147                 d_char_next <= (others => '0');
 148                 finished_next <= '0';
 149                 wr_next <= '0';
 150                 address_next <= address_int;
 151                 data_in_next <= data_in_int;
 152
 153                 case state_int is
 154                         when S_S_INIT =>
 155                                 null;
 156                         when SIDLE =>
 157                                 -- TODO: tmp fix
 158                                 d_new_result_next <= '0';
 159                         when S_S_WRITE =>
 160                                 wr_next <= '1';
 161                                 address_next <= s_cnt_int;
 162                                 data_in_next <= s_char;
 163                                 s_cnt_next <= std_logic_vector(unsigned(s_cnt_int) + 1);
 164                         when S_S_BS =>
 165                                 wr_next <= '1';
 166                                 address_next <= std_logic_vector(unsigned(s_cnt_int) - 1);
 167                                 data_in_next <= (others => '0');
 168                                 if unsigned(s_cnt_int) /= 0 then
 169                                         s_cnt_next <= std_logic_vector(unsigned(s_cnt_int) - 1);
 170                                 end if;
 171                         when S_S_FIN =>
 172                                 finished_next <= '1';
 173                                 s_cnt_next <= (0 => '1', others => '0');
 174                                 d_new_result_next <= '1';
 175                         when S_S_DONE =>
 176                                 s_done_next <= '1';
 177                                 d_new_eingabe_next <= '1';
 178
 179                         when S_D_INIT =>
 180                                 address_next <= d_spalte;
 181                                 d_new_eingabe_next <= '0';
 182                                 d_new_result_next <= '0';
 183                         when S_D_WRITE =>
 184                                 d_char_next <= data_out;
 185                                 d_done_next <= '1';
 186                 end case;
 187         end process;
 188
 189         sp_ram_inst : entity work.sp_ram(beh)
 190         generic map (
 191                 ADDR_WIDTH => H_RAM_WIDTH
 192         )
 193         port map (
 194                 sys_clk => sys_clk,
 195                 address => address_int,
 196                 data_out => data_out,
 197                 wr => wr_int,
 198                 data_in => data_in_int
 199         );
 200 end architecture beh;