end entity display;
architecture beh of display is
- type DISPLAY_STATE is (S_INIT, SIDLE, S_NEW_RESULT, S_NEW_INPUT, S_COUNTUP, S_GETCH,
+ type DISPLAY_STATE is (SIDLE, S_NEW_RESULT, S_NEW_INPUT, S_COUNTUP, S_GETCH,
S_CR1, S_NL1, S_PUTCH1, S_PUTCH2, S_WAIT, S_NOP1);
signal state_int, state_next : DISPLAY_STATE;
signal d_zeile_int, d_zeile_next : hzeile;
begin
if sys_res_n = '0' then
-- internal
- state_int <= S_INIT;
+ state_int <= SIDLE;
istate_int <= (others => '0');
-- out
d_zeile_int <= (others => '0');
istate_next <= istate_int;
case state_int is
- when S_INIT =>
- state_next <= SIDLE;
when SIDLE =>
+ istate_next <= b"111"; -- default: immer wieder ins SIDLE;
if d_new_eingabe = '1' then
state_next <= S_NEW_INPUT;
end if;
when S_NL1 =>
if free = '0' then
state_next <= S_WAIT;
- istate_next <= b"111";
+ istate_next <= b"111"; -- => wieder nach SIDLE
end if;
when S_COUNTUP =>
state_next <= S_GETCH;
when S_PUTCH2 =>
if free = '0' or (free = '1' and d_char = x"00") then
state_next <= S_WAIT;
- istate_next <= b"111";
end if;
when S_WAIT =>
if free = '1' and d_done = '0' then
command_data_next <= command_data_int;
case state_int is
- when S_INIT =>
- d_spalte_next <= (others => '0');
- d_zeile_next <= (others => '0');
when SIDLE =>
null;
when S_NEW_INPUT =>
architecture beh of history is
type HISTORY_STATE is (SIDLE, S_S_INIT, S_S_WRITE, S_S_BS, S_S_DONE, S_S_FIN,
- S_D_INIT, S_D_WAIT, S_D_WRITE);
+ S_D_INIT, S_D_WRITE);
signal state_int, state_next : HISTORY_STATE;
signal s_done_int, s_done_next : std_logic;
signal s_cnt_int, s_cnt_next : hspalte;
end if;
when S_D_INIT =>
- state_next <= S_D_WAIT;
- when S_D_WAIT =>
state_next <= S_D_WRITE;
when S_D_WRITE =>
if d_get = '0' then
address_next <= d_spalte;
d_new_eingabe_next <= '0';
d_new_result_next <= '0';
- when S_D_WAIT =>
- null;
when S_D_WRITE =>
d_char_next <= data_out;
d_done_next <= '1';