2 use ieee.std_logic_1164.all;
3 use ieee.numeric_std.all;
7 subtype alu_ops is std_logic_vector(2 downto 0);
8 constant ALU_NOP : alu_ops := "000";
9 constant ALU_SUB : alu_ops := "001";
10 constant ALU_ADD : alu_ops := "010";
11 constant ALU_MUL : alu_ops := "011";
12 constant ALU_DIV : alu_ops := "100";
13 constant ALU_DONE : alu_ops := "101";
15 constant CBITS : integer := 32;
16 subtype csigned is signed((CBITS-1) downto 0);
17 subtype divinteger is integer range -33 to 33;
18 -- integer ist 32bit (31bit + sign)
19 subtype cinteger is integer;
22 constant H_RAM_SIZE : integer := 142;
23 -- danach: 50 * 71 * 2 = 7100
24 -- constant H_RAM_SIZE : integer := 7100;
25 constant H_RAM_WIDTH : integer := log2c(H_RAM_SIZE);
26 subtype hspalte is std_logic_vector(6 downto 0);
27 subtype hzeile is std_logic_vector(4 downto 0);
28 subtype hbyte is std_logic_vector(7 downto 0);
29 subtype hstring is string(1 to 71);
30 subtype hstr_int is integer range 0 to 72;
32 function find_msb(a : csigned) return divinteger;
33 procedure icwait(signal clk_i : IN std_logic; cycles: natural);
36 package body gen_pkg is
37 function find_msb(a : csigned) return divinteger is
38 variable r : divinteger := 0;
40 for i in (CBITS-1) downto 0 loop
45 end function find_msb;
47 procedure icwait(signal clk_i : IN std_logic; cycles: Natural) is
49 for i in 1 to cycles loop
50 wait until clk_i= '0' and clk_i'event;
53 end package body gen_pkg;