2 use ieee.std_logic_1164.all;
3 use ieee.numeric_std.all;
5 use work.textmode_vga_component_pkg.all;
6 use work.textmode_vga_pkg.all;
7 use work.textmode_vga_platform_dependent_pkg.all;
8 use work.ps2_keyboard_controller_pkg.all;
13 CLK_50MHZ : in std_logic;
14 sys_res : in std_logic;
15 -- btnA (here: "btn west")
21 vsync_n : out std_logic;
22 hsync_n : out std_logic;
23 r : out std_logic_vector(RED_BITS - 1 downto 0);
24 g : out std_logic_vector(GREEN_BITS - 1 downto 0);
25 b : out std_logic_vector(BLUE_BITS - 1 downto 0);
27 ps2_clk : inout std_logic;
28 ps2_data : inout std_logic
32 architecture top of calc is
33 constant CLK_FREQ : integer := 50000000;
34 constant BAUDRATE : integer := 115200;
36 signal sys_res_n : std_logic;
38 signal new_data : std_logic;
39 signal data : std_logic_vector(7 downto 0);
41 signal vga_clk, free : std_logic;
43 signal command : std_logic_vector(COMMAND_SIZE - 1 downto 0);
44 signal command_data : std_logic_vector(3 * COLOR_SIZE + CHAR_SIZE -1 downto 0);
46 signal d_new_eingabe, d_new_result, d_new_bs : std_logic;
47 signal d_zeile : hzeile;
48 signal d_spalte : hspalte;
49 signal d_get, d_done : std_logic;
50 signal d_char : hbyte;
52 signal s_char : hbyte;
53 signal s_take, s_done, s_backspace : std_logic;
55 signal p_rget : std_logic;
56 signal p_rdone : std_logic;
57 signal p_read : hbyte;
58 signal p_wtake : std_logic;
59 signal p_wdone : std_logic;
60 signal p_write : hbyte;
61 signal p_finished : std_logic;
63 signal pc_get : std_logic;
64 signal pc_spalte : hspalte;
65 signal pc_zeile : hzeile;
66 signal pc_char : hbyte;
67 signal pc_done : std_logic;
69 signal do_it, finished : std_logic;
71 signal rx_new, rxd_sync : std_logic;
72 signal rx_data : std_logic_vector (7 downto 0);
73 signal tx_new, tx_done : std_logic;
74 signal tx_data : std_logic_vector (7 downto 0);
76 sys_res_n <= not sys_res;
79 textmode_vga_inst : textmode_vga
81 VGA_CLK_FREQ => 25000000,
82 BLINK_INTERVAL_MS => 500,
87 sys_res_n => sys_res_n,
89 command_data => command_data,
92 vga_res_n => sys_res_n,
101 clk_vga_s3e_inst : clk_vga_s3e
108 display_inst : display
110 sys_clk => CLK_50MHZ,
111 sys_res_n => sys_res_n,
113 d_new_eingabe => d_new_eingabe,
114 d_new_result => d_new_result,
115 d_new_bs => d_new_bs,
117 d_spalte => d_spalte,
123 command_data => command_data,
128 history_inst : history
130 sys_clk => CLK_50MHZ,
131 sys_res_n => sys_res_n,
136 s_backspace => s_backspace,
138 d_new_eingabe => d_new_eingabe,
139 d_new_result => d_new_result,
140 d_new_bs => d_new_bs,
142 d_spalte => d_spalte,
153 p_finished => p_finished,
156 pc_spalte => pc_spalte,
157 pc_zeile => pc_zeile,
165 sys_clk => CLK_50MHZ,
166 sys_res_n => sys_res_n,
174 p_finished => p_finished,
181 scanner_inst : scanner
183 sys_clk => CLK_50MHZ,
184 sys_res_n => sys_res_n,
186 new_data => new_data,
192 s_backspace => s_backspace,
199 ps2_inst : ps2_keyboard_controller
201 CLK_FREQ => CLK_FREQ,
205 sys_clk => CLK_50MHZ,
206 sys_res_n => sys_res_n,
208 new_data => new_data,
214 -- synchronizer fuer rxd
221 sys_clk => CLK_50MHZ,
222 sys_res_n => sys_res_n,
228 rs232rx_inst : uart_rx
230 CLK_FREQ => CLK_FREQ,
234 sys_clk => CLK_50MHZ,
235 sys_res_n => sys_res_n,
242 rs232tx_inst : uart_tx
244 CLK_FREQ => CLK_FREQ,
248 sys_clk => CLK_50MHZ,
249 sys_res_n => sys_res_n,
257 pc_com_inst : pc_communication
259 sys_clk => CLK_50MHZ,
260 sys_res_n => sys_res_n,
271 pc_zeile => pc_zeile,
272 pc_spalte => pc_spalte,
277 end architecture top;