library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.gen_pkg.all;
use work.textmode_vga_component_pkg.all;
use work.textmode_vga_pkg.all;
use work.textmode_vga_platform_dependent_pkg.all;
use work.ps2_keyboard_controller_pkg.all;
use work.sync_pkg.all;

entity calc is
	port (
		CLK_50MHZ : in std_logic;
		sys_res : in std_logic;
		-- btnA (here: "btn west")
		btn_a : in std_logic;
		-- rs232
		rxd : in std_logic;
		txd : out std_logic;
		-- vga
		vsync_n : out std_logic;
		hsync_n : out std_logic;
		r : out std_logic_vector(RED_BITS - 1 downto 0);
		g : out std_logic_vector(GREEN_BITS - 1 downto 0);
		b : out std_logic_vector(BLUE_BITS - 1 downto 0);
		-- ps/2
		ps2_clk : inout std_logic;
		ps2_data : inout std_logic
	);
end entity calc;

architecture top of calc is
	constant CLK_FREQ : integer := 50000000;
	constant BAUDRATE : integer := 115200;
	-- reset
	signal sys_res_n : std_logic;
	-- ps/2
	signal new_data : std_logic;
	signal data : std_logic_vector(7 downto 0);
	-- vga
	signal vga_clk, free : std_logic;
	-- vga/display
	signal command : std_logic_vector(COMMAND_SIZE - 1 downto 0);
	signal command_data : std_logic_vector(3 * COLOR_SIZE + CHAR_SIZE -1 downto 0);
	-- history/display
	signal d_new_eingabe, d_new_result, d_new_bs : std_logic;
	signal d_zeile : hzeile;
	signal d_spalte : hspalte;
	signal d_get, d_done : std_logic;
	signal d_char : hbyte;
	-- history/scanner
	signal s_char : hbyte;
	signal s_take, s_done, s_backspace : std_logic;
	-- history/parser
	signal p_rget : std_logic;
	signal p_rdone : std_logic;
	signal p_read : hbyte;
	signal p_wtake : std_logic;
	signal p_wdone : std_logic;
	signal p_write : hbyte;
	signal p_finished : std_logic;
	--history/pc_com
	signal pc_get : std_logic;
	signal pc_spalte : hspalte;
	signal pc_zeile : hzeile;
	signal pc_char : hbyte;
	signal pc_done : std_logic;
	-- parser/scanner
	signal do_it, finished : std_logic;
	-- rs232
	signal rx_new, rxd_sync : std_logic;
	signal rx_data : std_logic_vector (7 downto 0);
	signal tx_new, tx_done : std_logic;
	signal tx_data : std_logic_vector (7 downto 0);
begin
	sys_res_n <= not sys_res;

	-- vga/ipcore
	textmode_vga_inst : textmode_vga
	generic map (
		VGA_CLK_FREQ => 25000000,
		BLINK_INTERVAL_MS => 500,
		SYNC_STAGES => 2
	)
	port map (
		sys_clk => CLK_50MHZ,
		sys_res_n => sys_res_n,
		command => command,
		command_data => command_data,
		free => free,
		vga_clk => vga_clk,
		vga_res_n => sys_res_n,
		vsync_n => vsync_n,
		hsync_n => hsync_n,
		r => r,
		g => g,
		b => b
	);

	-- pll fuer vga
	clk_vga_s3e_inst : clk_vga_s3e
	port map (
		clk50 => CLK_50MHZ,
		clk25 => vga_clk
	);

	-- display
	display_inst : display
	port map (
		sys_clk => CLK_50MHZ,
		sys_res_n => sys_res_n,
		-- history
		d_new_eingabe => d_new_eingabe,
		d_new_result => d_new_result,
		d_new_bs => d_new_bs,
		d_zeile => d_zeile,
		d_spalte => d_spalte,
		d_get => d_get,
		d_done => d_done,
		d_char => d_char,
		-- vga
		command => command,
		command_data => command_data,
		free => free
	);

	-- history
	history_inst : history
	port map (
		sys_clk => CLK_50MHZ,
		sys_res_n => sys_res_n,
		-- scanner
		s_char => s_char,
		s_take => s_take,
		s_done => s_done,
		s_backspace => s_backspace,
		-- display
		d_new_eingabe => d_new_eingabe,
		d_new_result => d_new_result,
		d_new_bs => d_new_bs,
		d_zeile => d_zeile,
		d_spalte => d_spalte,
		d_get => d_get,
		d_done => d_done,
		d_char => d_char,
		-- parser
		p_rget => p_rget,
		p_rdone => p_rdone,
		p_read => p_read,
		p_wtake => p_wtake,
		p_wdone => p_wdone,
		p_write => p_write,
		p_finished => p_finished,
		-- pc communication
		pc_get =>  pc_get,
		pc_spalte => pc_spalte,
		pc_zeile => pc_zeile,
		pc_char => pc_char,
		pc_done => pc_done
	);

	-- parser
	parser_inst : parser
	port map (
		sys_clk => CLK_50MHZ,
		sys_res_n => sys_res_n,
		-- history
		p_rget => p_rget,
		p_rdone => p_rdone,
		p_read => p_read,
		p_wtake => p_wtake,
		p_wdone => p_wdone,
		p_write => p_write,
		p_finished => p_finished,
		-- scanner
		do_it => do_it,
		finished => finished
	);

	-- scanner
	scanner_inst : scanner
	port map (
		sys_clk => CLK_50MHZ,
		sys_res_n => sys_res_n,
		-- ps/2
		new_data => new_data,
		data => data,
		-- history
		s_char => s_char,
		s_take => s_take,
		s_done => s_done,
		s_backspace => s_backspace,
		-- parser
		do_it => do_it,
		finished => finished
	);

	-- ps/2
	ps2_inst : ps2_keyboard_controller
	generic map (
		CLK_FREQ => CLK_FREQ,
		SYNC_STAGES => 2
	)
	port map (
		sys_clk => CLK_50MHZ,
		sys_res_n => sys_res_n,
		-- scanner
		new_data => new_data,
		data => data,
		ps2_clk => ps2_clk,
		ps2_data => ps2_data
	);

	-- synchronizer fuer rxd
	sync_rxd_inst : sync
	generic map (
		SYNC_STAGES => 2,
		RESET_VALUE => '1'
	)
	port map (
		sys_clk => CLK_50MHZ,
		sys_res_n => sys_res_n,
		data_in => rxd,
		data_out => rxd_sync
	);

	-- rs232-rx
	rs232rx_inst : uart_rx
	generic map (
		CLK_FREQ => CLK_FREQ,
		BAUDRATE => BAUDRATE
	)
	port map (
		sys_clk => CLK_50MHZ,
		sys_res_n => sys_res_n,
		rxd => rxd_sync,
		rx_data => rx_data,
		rx_new => rx_new
	);

	-- rs232-tx
	rs232tx_inst : uart_tx
	generic map (
		CLK_FREQ => CLK_FREQ,
		BAUDRATE => BAUDRATE
	)
	port map (
		sys_clk => CLK_50MHZ,
		sys_res_n => sys_res_n,
		txd => txd,
		tx_data => tx_data,
		tx_new => tx_new,
		tx_done => tx_done
	);

	-- pc-com
	pc_com_inst : pc_communication
	port map (
		sys_clk => CLK_50MHZ,
		sys_res_n => sys_res_n,
		--button
		btn_a => not btn_a,
		--uart_tx
		tx_data => tx_data,
		tx_new => tx_new,
		tx_done => tx_done,
		--uart_rx
		rx_data => rx_data,
		rx_new => rx_new,
		-- History
		pc_zeile => pc_zeile,
		pc_spalte => pc_spalte,
		pc_get => pc_get,
		pc_done => pc_done,
		pc_char => pc_char
	);
end architecture top;