src/alu.vhd

   1 library ieee;
   2 use ieee.std_logic_1164.all;
   3 use ieee.numeric_std.all;
   4 use work.gen_pkg.all;
   5
   6 entity alu is
   7         port
   8         (
   9                 sys_clk : in std_logic;
  10                 sys_res_n : in std_logic;
  11                 opcode : in alu_ops;
  12                 op1 : in csigned;
  13                 op2 : in csigned;
  14                 op3 : out csigned;
  15                 do_calc : in std_logic;
  16                 calc_done : out std_logic
  17         );
  18 end entity alu;
  19
  20 architecture beh of alu is
  21         type ALU_STATE is (SIDLE, SADD, SSUB, SMUL, SDIV, SDIV_CALC, SDIV_DONE, SDONE);
  22         signal state, state_next : ALU_STATE;
  23         signal done_intern, div_calc_done, div_go_calc : std_logic;
  24         signal op3_int, op3_next : csigned;
  25         signal calc_done_int, calc_done_next : std_logic;
  26         -- signale fuer division
  27         signal dividend_msb, dividend_msb_next, laengediv, laengediv_next : natural;
  28         signal quo, quo_next, aktdiv, aktdiv_next, op1_int, op1_next, op2_int, op2_next : csigned;
  29         signal sign, sign_next : std_logic;
  30 begin
  31         op3 <= op3_int;
  32         calc_done <= calc_done_int;
  33
  34         -- sync
  35         process(sys_clk, sys_res_n)
  36         begin
  37                 if sys_res_n = '0' then
  38                         state <= SIDLE;
  39                 elsif rising_edge(sys_clk) then
  40                         state <= state_next;
  41                         op3_int <= op3_next;
  42                         calc_done_int <= calc_done_next;
  43                         -- div
  44                         dividend_msb <= dividend_msb_next;
  45                         laengediv <= laengediv_next;
  46                         quo <= quo_next;
  47                         aktdiv <= aktdiv_next;
  48                         op1_int <= op1_next;
  49                         op2_int <= op2_next;
  50                         sign <= sign_next;
  51                 end if;
  52         end process;
  53
  54         -- next state
  55         process(state, opcode, done_intern, do_calc, div_calc_done, div_go_calc)
  56         begin
  57                 -- set a default value for next state
  58                 state_next <= state;
  59                 -- next state berechnen
  60                 case state is
  61                         when SIDLE =>
  62                                 if do_calc = '1' then
  63                                         case opcode is
  64                                                 when ADD =>
  65                                                         state_next <= SADD;
  66                                                 when SUB =>
  67                                                         state_next <= SSUB;
  68                                                 when MUL =>
  69                                                         state_next <= SMUL;
  70                                                 when DIV =>
  71                                                         state_next <= SDIV;
  72                                                 when others =>
  73                                                         state_next <= SIDLE;
  74                                         end case;
  75                                 end if;
  76                         when SADD =>
  77                                 if done_intern = '1' then
  78                                         state_next <= SDONE;
  79                                 end if;
  80                         when SSUB =>
  81                                 if done_intern = '1' then
  82                                         state_next <= SDONE;
  83                                 end if;
  84                         when SMUL =>
  85                                 if done_intern = '1' then
  86                                         state_next <= SDONE;
  87                                 end if;
  88                         when SDIV =>
  89                                 if div_go_calc = '1' then
  90                                         state_next <= SDIV_CALC;
  91                                 end if;
  92                         when SDIV_CALC =>
  93                                 if div_calc_done = '1' then
  94                                         state_next <= SDIV_DONE;
  95                                 end if;
  96                         when SDIV_DONE =>
  97                                 if done_intern = '1' then
  98                                         state_next <= SDONE;
  99                                 end if;
 100                         when SDONE =>
 101                                 if do_calc = '0' then
 102                                         state_next <= SIDLE;
 103                                 end if;
 104                 end case;
 105         end process;
 106
 107         -- output
 108         process(state, op1, op2, dividend_msb, laengediv, quo, aktdiv, sign, op1_int, op2_int)
 109                 variable tmperg : csigned;
 110                 variable multmp : signed(((2*CBITS)-1) downto 0);
 111                 -- vars fuer div
 112                 variable laengediv_var, dividend_msb_var : natural;
 113                 variable aktdiv_var, quo_var, op1_var, op2_var : csigned;
 114         begin
 115                 op3_next <= (others => '0');
 116                 calc_done_next <= '0';
 117                 div_calc_done <= '0';
 118                 div_go_calc <= '0';
 119                 done_intern <= '0';
 120                 -- default fuer div
 121                 dividend_msb_next <= 0;
 122                 laengediv_next <= 0;
 123                 quo_next <= (others => '0');
 124                 aktdiv_next <= (others => '0');
 125                 op1_next <= (others => '0');
 126                 op2_next <= (others => '0');
 127                 sign_next <= '0';
 128
 129                 case state is
 130                         when SIDLE =>
 131                                 tmperg := (others => '0');
 132                         when SADD =>
 133                                 tmperg := op1 + op2;
 134                                 done_intern <= '1';
 135                         when SSUB =>
 136                                 tmperg := op1 - op2;
 137                                 done_intern <= '1';
 138                         when SMUL =>
 139                                 multmp := op1 * op2;
 140                                 tmperg(CBITS-1) := multmp((2*CBITS)-1);
 141                                 tmperg((CBITS-2) downto 0) := multmp((CBITS-2) downto 0);
 142                                 done_intern <= '1';
 143                         when SDIV =>
 144                                 -- division implementiert nach ~hwmod/doc/division.pdf
 145                                 tmperg := (others => '0');
 146                                 if op2 = to_signed(0,CBITS) then
 147                                         -- TODO: err out signal
 148                                         done_intern <= '1';
 149                                 else
 150                                         -- sign check
 151                                         op1_var := op1;
 152                                         op2_var := op2;
 153                                         if op1(CBITS-1) = '1' then
 154                                                 op1_var := not (op1_var + 1);
 155                                         end if;
 156                                         if op2(CBITS-1) = '1' then
 157                                                 op2_var := not (op2_var + 1);
 158                                         end if;
 159
 160                                         dividend_msb_var := find_msb(op1_var)-1;
 161                                         laengediv_var := find_msb(op2_var)-1;
 162
 163                                         aktdiv_next <= op1_var srl (dividend_msb_var - laengediv_var + 1);
 164
 165                                         div_go_calc <= '1';
 166                                         dividend_msb_next <= dividend_msb_var;
 167                                         laengediv_next <= laengediv_var;
 168                                         quo_next <= (others => '0');
 169                                         op1_next <= op1_var;
 170                                         op2_next <= op2_var;
 171                                         sign_next <= op1(CBITS-1) xor op2(CBITS-1);
 172                                 end if;
 173                         when SDIV_CALC =>
 174                                 tmperg := (others => '0');
 175
 176                                 if (dividend_msb - laengediv + 1) > 0 then
 177                                         aktdiv_var := aktdiv sll 1;
 178                                         aktdiv_var(0) := op1_int(dividend_msb - laengediv);
 179
 180                                         quo_var := quo sll 1;
 181                                         if aktdiv_var >= op2_int then
 182                                                 quo_var(0) := '1';
 183                                                 aktdiv_var := aktdiv_var - op2_int;
 184                                         end if;
 185
 186                                         quo_next <= quo_var;
 187                                         aktdiv_next <= aktdiv_var;
 188                                         dividend_msb_next <= dividend_msb;
 189                                         laengediv_next <= laengediv + 1;
 190                                         op1_next <= op1_int;
 191                                         op2_next <= op2_int;
 192                                         sign_next <= sign;
 193                                 else
 194                                         if sign = '1' then
 195                                                 quo_next <= (not quo) + 1;
 196                                         else
 197                                                 quo_next <= quo;
 198                                         end if;
 199                                         div_calc_done <= '1';
 200                                 end if;
 201                         when SDIV_DONE =>
 202                                 tmperg := quo;
 203                                 done_intern <= '1';
 204                         when SDONE =>
 205                                 done_intern <= '1';
 206                                 calc_done_next <= '1';
 207                                 op3_next <= tmperg;
 208                                 tmperg := (others => '0');
 209                 end case;
 210         end process;
 211 end architecture beh;
 212