1 ; Copyright 1991-2009 Mentor Graphics Corporation
5 ; THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION WHICH IS THE PROPERTY OF
6 ; MENTOR GRAPHICS CORPORATION OR ITS LICENSORS AND IS SUBJECT TO LICENSE TERMS.
10 others = $MODEL_TECH/../modelsim.ini
11 ;vhdl_psl_checkers = $MODEL_TECH/../vhdl_psl_checkers // Source files only for this release
12 ;verilog_psl_checkers = $MODEL_TECH/../verilog_psl_checkers // Source files only for this release
13 ;mvc_lib = $MODEL_TECH/../mvc_lib
17 ; VHDL93 variable selects language version as the default.
18 ; Default is VHDL-2002.
19 ; Value of 0 or 1987 for VHDL-1987.
20 ; Value of 1 or 1993 for VHDL-1993.
21 ; Default or value of 2 or 2002 for VHDL-2002.
22 ; Value of 3 or 2008 for VHDL-2008
25 ; Show source line containing error. Default is off.
28 ; Turn off unbound-component warnings. Default is on.
31 ; Turn off process-without-a-wait-statement warnings. Default is on.
34 ; Turn off null-range warnings. Default is on.
37 ; Turn off no-space-in-time-literal warnings. Default is on.
40 ; Turn off multiple-drivers-on-unresolved-signal warnings. Default is on.
43 ; Turn off optimization for IEEE std_logic_1164 package. Default is on.
46 ; Turn on resolving of ambiguous function overloading in favor of the
47 ; "explicit" function declaration (not the one automatically created by
48 ; the compiler for each type declaration). Default is off.
49 ; The .ini file has Explicit enabled so that std_logic_signed/unsigned
50 ; will match the behavior of synthesis tools.
53 ; Turn off acceleration of the VITAL packages. Default is to accelerate.
56 ; Turn off VITAL compliance checking. Default is checking on.
59 ; Ignore VITAL compliance checking errors. Default is to not ignore.
60 ; IgnoreVitalErrors = 1
62 ; Turn off VITAL compliance checking warnings. Default is to show warnings.
63 ; Show_VitalChecksWarnings = 0
65 ; Turn off PSL assertion warning messages. Default is to show warnings.
66 ; Show_PslChecksWarnings = 0
68 ; Enable parsing of embedded PSL assertions. Default is enabled.
71 ; Keep silent about case statement static warnings.
72 ; Default is to give a warning.
73 ; NoCaseStaticError = 1
75 ; Keep silent about warnings caused by aggregates that are not locally static.
76 ; Default is to give a warning.
77 ; NoOthersStaticError = 1
80 ; case statement static warnings
81 ; warnings caused by aggregates that are not locally static
82 ; Overrides NoCaseStaticError, NoOthersStaticError settings.
85 ; Turn off inclusion of debugging info within design units.
86 ; Default is to include debugging info.
89 ; Turn off "Loading..." messages. Default is messages on.
92 ; Turn on some limited synthesis rule compliance checking. Checks only:
93 ; -- signals used (read) by a process must be in the sensitivity list
96 ; Activate optimizations on expressions that do not involve signals,
97 ; waits, or function/procedure/task invocations. Default is off.
100 ; Turns on lint-style checking.
103 ; Require the user to specify a configuration for all bindings,
104 ; and do not generate a compile time default binding for the
105 ; component. This will result in an elaboration error of
106 ; 'component not bound' if the user fails to do so. Avoids the rare
107 ; issue of a false dependency upon the unused default binding.
108 ; RequireConfigForAllDefaultBinding = 1
110 ; Perform default binding at compile time.
111 ; Default is to do default binding at load time.
114 ; Inhibit range checking on subscripts of arrays. Range checking on
115 ; scalars defined with subtypes is inhibited by default.
118 ; Inhibit range checks on all (implicit and explicit) assignments to
119 ; scalar objects defined with subtypes.
122 ; Run the 0-in compiler on the VHDL source files
126 ; Set the options to be passed to the 0-in compiler.
130 ; Turn on code coverage in VHDL design units. Default is off.
133 ; Turn off code coverage in VHDL subprograms. Default is on.
136 ; Automatically exclude VHDL case statement default branches.
137 ; Default is to not exclude.
138 ; CoverExcludeDefault = 1
140 ; Control compiler and VOPT optimizations that are allowed when
141 ; code coverage is on. Refer to the comment for this in the [vlog] area.
144 ; Inform code coverage optimizations to respect VHDL 'H' and 'L'
145 ; values on signals in conditions and expressions, and to not automatically
146 ; convert them to '1' and '0'. Default is to not convert.
147 ; CoverRespectHandL = 0
149 ; Increase or decrease the maximum number of rows allowed in a UDP table
150 ; implementing a VHDL condition coverage or expression coverage expression.
151 ; More rows leads to a longer compile time, but more expressions covered.
152 ; CoverMaxUDPRows = 192
154 ; Increase or decrease the maximum number of input patterns that are present
155 ; in FEC table. This leads to a longer compile time with more expressions
156 ; covered with FEC metric.
157 ; CoverMaxFECRows = 192
159 ; Enable or disable Focused Expression Coverage analysis for conditions and
160 ; expressions. Focused Expression Coverage data is provided by default when
161 ; expression and/or condition coverage is active.
164 ; Enable or disable short circuit evaluation of conditions and expressions when
165 ; condition or expression coverage is active. Short circuit evaluation is enabled
167 ; CoverShortCircuit = 0
169 ; Use this directory for compiler temporary files instead of "work/_temp"
170 ; CompilerTempDir = /tmp
172 ; Add VHDL-AMS declarations to package STANDARD
173 ; Default is not to add
176 ; Range and length checking will be performed on array indices and discrete
177 ; ranges, and when violations are found within subprograms, errors will be
178 ; reported. Default is to issue warnings for violations, because subprograms
179 ; may not be invoked.
180 ; NoDeferSubpgmCheck = 0
182 ; Turn off detection of FSMs having single bit current state variable.
185 ; Turn off reset state transitions in FSM.
188 ; Do not show immediate assertions with constant expressions in
189 ; GUI/report/UCDB etc. By default immediate assertions with constant
190 ; expressions are shown in GUI/report/UCDB etc. This does not affect ;
191 ; evaluation of immediate assertions.
192 ; ShowConstantImmediateAsserts = 0
195 ; Turn off inclusion of debugging info within design units.
196 ; Default is to include debugging info.
199 ; Turn on `protect compiler directive processing.
200 ; Default is to ignore `protect directives.
203 ; Turn off "Loading..." messages. Default is messages on.
206 ; Turn on Verilog hazard checking (order-dependent accessing of global vars).
210 ; Turn on converting regular Verilog identifiers to uppercase. Allows case
211 ; insensitivity for module names. Default is no conversion.
214 ; Activate optimizations on expressions that do not involve signals,
215 ; waits, or function/procedure/task invocations. Default is off.
218 ; Turns on lint-style checking.
221 ; Show source line containing error. Default is off.
224 ; Turn on bad option warning. Default is off.
225 ; Show_BadOptionWarning = 1
227 ; Revert back to IEEE 1364-1995 syntax, default is 0 (off).
230 ; Turn off PSL warning messages. Default is to show warnings.
231 ; Show_PslChecksWarnings = 0
233 ; Enable parsing of embedded PSL assertions. Default is enabled.
236 ; Set the threshold for automatically identifying sparse Verilog memories.
237 ; A memory with depth equal to or more than the sparse memory threshold gets
238 ; marked as sparse automatically, unless specified otherwise in source code
239 ; or by +nosparse commandline option of vlog or vopt.
240 ; The default is 1M. (i.e. memories with depth equal
241 ; to or greater than 1M are marked as sparse)
242 ; SparseMemThreshold = 1048576
244 ; Set the maximum number of iterations permitted for a generate loop.
245 ; Restricting this permits the implementation to recognize infinite
247 ; GenerateLoopIterationMax = 100000
249 ; Set the maximum depth permitted for a recursive generate instantiation.
250 ; Restricting this permits the implementation to recognize infinite
252 ; GenerateRecursionDepthMax = 200
254 ; Run the 0-in compiler on the Verilog source files
258 ; Set the options to be passed to the 0-in compiler.
262 ; Set the option to treat all files specified in a vlog invocation as a
263 ; single compilation unit. The default value is set to 0 which will treat
264 ; each file as a separate compilation unit as specified in the P1800 draft standard.
265 ; MultiFileCompilationUnit = 1
267 ; Turn on code coverage in Verilog design units. Default is off.
270 ; Automatically exclude Verilog case statement default branches.
271 ; Default is to not automatically exclude defaults.
272 ; CoverExcludeDefault = 1
274 ; Increase or decrease the maximum number of rows allowed in a UDP table
275 ; implementing a Verilog condition coverage or expression coverage expression.
276 ; More rows leads to a longer compile time, but more expressions covered.
277 ; CoverMaxUDPRows = 192
279 ; Increase or decrease the maximum number of input patterns that are present
280 ; in FEC table. This leads to a longer compile time with more expressions
281 ; covered with FEC metric.
282 ; CoverMaxFECRows = 192
284 ; Enable or disable Focused Expression Coverage analysis for conditions and
285 ; expressions. Focused Expression Coverage data is provided by default when
286 ; expression and/or condition coverage is active.
289 ; Enable or disable short circuit evaluation of conditions and expressions when
290 ; condition or expression coverage is active. Short circuit evaluation is enabled
292 ; CoverShortCircuit = 0
295 ; Turn on code coverage in VLOG `celldefine modules and modules included
296 ; using vlog -v and -y. Default is off.
299 ; Control compiler and VOPT optimizations that are allowed when
300 ; code coverage is on. This is a number from 1 to 4, with the following
301 ; meanings (the default is 3):
302 ; 1 -- Turn off all optimizations that affect coverage reports.
303 ; 2 -- Allow optimizations that allow large performance improvements
304 ; by invoking sequential processes only when the data changes.
305 ; This may make major reductions in coverage counts.
306 ; 3 -- In addition, allow optimizations that may change expressions or
307 ; remove some statements. Allow constant propagation. Allow VHDL
308 ; subprogram inlining and VHDL FF recognition.
309 ; 4 -- In addition, allow optimizations that may remove major regions of
310 ; code by changing assignments to built-ins or removing unused
311 ; signals. Change Verilog gates to continuous assignments.
314 ; Specify the override for the default value of "cross_num_print_missing"
315 ; option for the Cross in Covergroups. If not specified then LRM default
316 ; value of 0 (zero) is used. This is a compile time option.
317 ; SVCrossNumPrintMissingDefault = 0
319 ; Setting following to 1 would cause creation of variables which
320 ; would represent the value of Coverpoint expressions. This is used
321 ; in conjunction with "SVCoverpointExprVariablePrefix" option
322 ; in the modelsim.ini
323 ; EnableSVCoverpointExprVariable = 0
325 ; Specify the override for the prefix used in forming the variable names
326 ; which represent the Coverpoint expressions. This is used in conjunction with
327 ; "EnableSVCoverpointExprVariable" option of the modelsim.ini
328 ; The default prefix is "expr".
329 ; The variable name is
330 ; variable name => <prefix>_<coverpoint name>
331 ; SVCoverpointExprVariablePrefix = expr
333 ; Override for the default value of the SystemVerilog covergroup,
334 ; coverpoint, and cross option.goal (defined to be 100 in the LRM).
335 ; NOTE: It does not override specific assignments in SystemVerilog
336 ; source code. NOTE: The modelsim.ini variable "SVCovergroupGoal"
337 ; in the [vsim] section can override this value.
338 ; SVCovergroupGoalDefault = 100
340 ; Override for the default value of the SystemVerilog covergroup,
341 ; coverpoint, and cross type_option.goal (defined to be 100 in the LRM)
342 ; NOTE: It does not override specific assignments in SystemVerilog
343 ; source code. NOTE: The modelsim.ini variable "SVCovergroupTypeGoal"
344 ; in the [vsim] section can override this value.
345 ; SVCovergroupTypeGoalDefault = 100
347 ; Specify the override for the default value of "strobe" option for the
348 ; Covergroup Type. This is a compile time option which forces "strobe" to
349 ; a user specified default value and supersedes SystemVerilog specified
350 ; default value of '0'(zero). NOTE: This can be overriden by a runtime
351 ; modelsim.ini variable "SVCovergroupStrobe" in the [vsim] section.
352 ; SVCovergroupStrobeDefault = 0
354 ; Specify the override for the default value of "merge_instances" option for
355 ; the Covergroup Type. This is a compile time option which forces
356 ; "merge_instances" to a user specified default value and supersedes
357 ; SystemVerilog specified default value of '0'(zero).
358 ; SVCovergroupMergeInstancesDefault = 0
360 ; Specify the override for the default value of "per_instance" option for the
361 ; Covergroup variables. This is a compile time option which forces "per_instance"
362 ; to a user specified default value and supersedes SystemVerilog specified
363 ; default value of '0'(zero).
364 ; SVCovergroupPerInstanceDefault = 0
366 ; Specify the override for the default value of "get_inst_coverage" option for the
367 ; Covergroup variables. This is a compile time option which forces
368 ; "get_inst_coverage" to a user specified default value and supersedes
369 ; SystemVerilog specified default value of '0'(zero).
370 ; SVCovergroupGetInstCoverageDefault = 0
373 ; A space separated list of resource libraries that contain precompiled
374 ; packages. The behavior is identical to using the "-L" switch.
376 ; LibrarySearchPath = <path/lib> [<path/lib> ...]
377 LibrarySearchPath = mtiAvm mtiOvm mtiUPF
379 ; The behavior is identical to the "-mixedansiports" switch. Default is off.
382 ; Enable SystemVerilog 3.1a $typeof() function. Default is off.
385 ; Only allow lower case pragmas. Default is disabled.
386 ; AcceptLowerCasePragmaOnly = 1
388 ; Set the maximum depth permitted for a recursive include file nesting.
389 ; IncludeRecursionDepthMax = 5
391 ; Turn off detection of FSMs having single bit current state variable.
394 ; Turn off reset state transitions in FSM.
397 ; Turn off detections of FSMs having x-assignment.
400 ; List of file suffixes which will be read as SystemVerilog. White space
401 ; in extensions can be specified with a back-slash: "\ ". Back-slashes
402 ; can be specified with two consecutive back-slashes: "\\";
403 ; SVFileExtensions = sv svp svh
405 ; This setting is the same as the vlog -sv command line switch.
406 ; Enables SystemVerilog features and keywords when true (1).
407 ; When false (0), the rules of IEEE Std 1364-2001 are followed and
408 ; SystemVerilog keywords are ignored.
411 ; Prints attribute placed upon SV packages during package import
412 ; when true (1). The attribute will be ignored when this
413 ; entry is false (0). The attribute name is "package_load_message".
414 ; The value of this attribute is a string literal.
415 ; Default is true (1).
416 ; PrintSVPackageLoadingAttribute = 1
418 ; Do not show immediate assertions with constant expressions in
419 ; GUI/reports/UCDB etc. By default immediate assertions with constant
420 ; expressions are shown in GUI/reports/UCDB etc. This does not affect
421 ; evaluation of immediate assertions.
422 ; ShowConstantImmediateAsserts = 0
425 ; Enable use of SCV include files and library. Default is off.
428 ; Add C++ compiler options to the sccom command line by using this variable.
431 ; Use custom C++ compiler located at this path rather than the default path.
432 ; The path should point directly at a compiler executable.
433 ; CppPath = /usr/bin/g++
435 ; Enable verbose messages from sccom. Default is off.
438 ; sccom logfile. Default is no logfile.
439 ; SccomLogfile = sccom.log
441 ; Enable use of SC_MS include files and library. Default is off.
445 ; Turn on code coverage in vopt. Default is off.
448 ; Control compiler optimizations that are allowed when
449 ; code coverage is on. Refer to the comment for this in the [vlog] area.
452 ; Increase or decrease the maximum number of rows allowed in a UDP table
453 ; implementing a vopt condition coverage or expression coverage expression.
454 ; More rows leads to a longer compile time, but more expressions covered.
455 ; CoverMaxUDPRows = 192
457 ; Increase or decrease the maximum number of input patterns that are present
458 ; in FEC table. This leads to a longer compile time with more expressions
459 ; covered with FEC metric.
460 ; CoverMaxFECRows = 192
462 ; Do not show immediate assertions with constant expressions in
463 ; GUI/reports/UCDB etc. By default immediate assertions with constant
464 ; expressions are shown in GUI/reports/UCDB etc. This does not affect
465 ; evaluation of immediate assertions.
466 ; ShowConstantImmediateAsserts = 0
470 ; Set to turn on automatic optimization of a design.
475 ; If automatic design optimization is on, enables automatic compilation
477 ; Default is on, uncomment to turn off.
478 ; VoptAutoSDFCompile = 0
480 ; Automatic SDF compilation
481 ; Disables automatic compilation of SDF files in flows that support it.
482 ; Default is on, uncomment to turn off.
483 ; NoAutoSDFCompile = 1
485 ; Simulator resolution
486 ; Set to fs, ps, ns, us, ms, or sec with optional prefix of 1, 10, or 100.
489 ; Disable certain code coverage exclusions automatically.
490 ; Assertions and FSM are exluded from the code coverage by default
491 ; Set AutoExclusionsDisable = fsm to enable code coverage for fsm
492 ; Set AutoExclusionsDisable = assertions to enable code coverage for assertions
493 ; Set AutoExclusionsDisable = all to enable code coverage for all the automatic exclusions
494 ; Or specify comma or space separated list
495 ;AutoExclusionsDisable = fsm,assertions
497 ; User time unit for run commands
498 ; Set to default, fs, ps, ns, us, ms, or sec. The default is to use the
499 ; unit specified for Resolution. For example, if Resolution is 100ps,
500 ; then UserTimeUnit defaults to ps.
501 ; Should generally be set to default.
502 UserTimeUnit = default
507 ; Maximum iterations that can be run without advancing simulation time
508 IterationLimit = 5000
510 ; Control PSL and Verilog Assume directives during simulation
511 ; Set SimulateAssumeDirectives = 0 to disable assume being simulated as asserts
512 ; Set SimulateAssumeDirectives = 1 to enable assume simulation as asserts
513 ; SimulateAssumeDirectives = 1
515 ; Control the simulation of PSL and SVA
516 ; These switches can be overridden by the vsim command line switches:
517 ; -psl, -nopsl, -sva, -nosva.
518 ; Set SimulatePSL = 0 to disable PSL simulation
519 ; Set SimulatePSL = 1 to enable PSL simulation (default)
521 ; Set SimulateSVA = 0 to disable SVA simulation
522 ; Set SimulateSVA = 1 to enable concurrent SVA simulation (default)
525 ; Directives to license manager can be set either as single value or as
526 ; space separated multi-values:
527 ; vhdl Immediately reserve a VHDL license
528 ; vlog Immediately reserve a Verilog license
529 ; plus Immediately reserve a VHDL and Verilog license
530 ; nomgc Do not look for Mentor Graphics Licenses
531 ; nomti Do not look for Model Technology Licenses
532 ; noqueue Do not wait in the license queue when a license is not available
533 ; viewsim Try for viewer license but accept simulator license(s) instead
534 ; of queuing for viewer license (PE ONLY)
535 ; noviewer Disable checkout of msimviewer and vsim-viewer license
537 ; noslvhdl Disable checkout of qhsimvh and vsim license features
538 ; noslvlog Disable checkout of qhsimvl and vsimvlog license features
539 ; nomix Disable checkout of msimhdlmix and hdlmix license features
540 ; nolnl Disable checkout of msimhdlsim and hdlsim license features
541 ; mixedonly Disable checkout of qhsimvh,qhsimvl,vsim,vsimvlog license
543 ; lnlonly Disable checkout of qhsimvh,qhsimvl,vsim,vsimvlog,msimhdlmix,
544 ; hdlmix license features
548 ; License = noqueue plus
550 ; Stop the simulator after a VHDL/Verilog immediate assertion message
551 ; 0 = Note 1 = Warning 2 = Error 3 = Failure 4 = Fatal
554 ; VHDL assertion Message Format
555 ; %S - Severity Level
556 ; %R - Report Message
557 ; %T - Time of assertion
559 ; %I - Instance or Region pathname (if available)
560 ; %i - Instance pathname with process
562 ; %K - Kind of object path is to return: Instance, Signal, Process or Unknown
563 ; %P - Instance or Region path without leaf process
565 ; %L - Line number of assertion or, if assertion is in a subprogram, line
566 ; from which the call is made
567 ; %% - Print '%' character
568 ; If specific format for assertion level is defined, use its format.
569 ; If specific format is not defined for assertion level:
570 ; - and if failure occurs during elaboration, use MessageFormatBreakLine;
571 ; - and if assertion triggers a breakpoint (controlled by BreakOnAssertion
572 ; level), use MessageFormatBreak;
573 ; - otherwise, use MessageFormat.
574 ; MessageFormatBreakLine = "** %S: %R\n Time: %T Iteration: %D %K: %i File: %F Line: %L\n"
575 ; MessageFormatBreak = "** %S: %R\n Time: %T Iteration: %D %K: %i File: %F\n"
576 ; MessageFormat = "** %S: %R\n Time: %T Iteration: %D%I\n"
577 ; MessageFormatNote = "** %S: %R\n Time: %T Iteration: %D%I\n"
578 ; MessageFormatWarning = "** %S: %R\n Time: %T Iteration: %D%I\n"
579 ; MessageFormatError = "** %S: %R\n Time: %T Iteration: %D %K: %i File: %F\n"
580 ; MessageFormatFail = "** %S: %R\n Time: %T Iteration: %D %K: %i File: %F\n"
581 ; MessageFormatFatal = "** %S: %R\n Time: %T Iteration: %D %K: %i File: %F\n"
583 ; Error File - alternate file for storing error messages
584 ; ErrorFile = error.log
587 ; Simulation Breakpoint messages
588 ; This flag controls the display of function names when reporting the location
589 ; where the simulator stops do to a breakpoint or fatal error.
590 ; Example w/function name: # Break in Process ctr at counter.vhd line 44
591 ; Example wo/function name: # Break at counter.vhd line 44
594 ; Default radix for all windows and commands.
595 ; Set to symbolic, ascii, binary, octal, decimal, hex, unsigned
596 DefaultRadix = symbolic
598 ; VSIM Startup command
599 ; Startup = do startup.do
602 ; Filename to save u/i formats and configurations.
603 ; ShutdownFile = restart.do
604 ; To explicitly disable auto save:
605 ; ShutdownFile = --disable-auto-save
607 ; File for saving command transcript
608 TranscriptFile = transcript
610 ; File for saving command history
611 ; CommandHistory = cmdhist.log
613 ; Specify whether paths in simulator commands should be described
614 ; in VHDL or Verilog format.
615 ; For VHDL, PathSeparator = /
616 ; For Verilog, PathSeparator = .
617 ; Must not be the same character as DatasetSeparator.
620 ; Specify the dataset separator for fully rooted contexts.
621 ; The default is ':'. For example: sim:/top
622 ; Must not be the same character as PathSeparator.
625 ; Specify a unique path separator for the Signal Spy set of functions.
626 ; The default will be to use the PathSeparator variable.
627 ; Must not be the same character as DatasetSeparator.
628 ; SignalSpyPathSeparator = /
630 ; Used to control parsing of HDL identifiers input to the tool.
631 ; This includes CLI commands, vsim/vopt/vlog/vcom options,
632 ; string arguments to FLI/VPI/DPI calls, etc.
633 ; If set to 1, accept either Verilog escaped Id syntax or
634 ; VHDL extended id syntax, regardless of source language.
635 ; If set to 0, the syntax of the source language must be used.
636 ; Each identifier in a hierarchical name may need different syntax,
637 ; e.g. "/top/\vhdl*ext*id\/middle/\vlog*ext*id /bottom" or
638 ; "top.\vhdl*ext*id\.middle.\vlog*ext*id .bottom"
639 ; GenerousIdentifierParsing = 1
641 ; Disable VHDL assertion messages
647 ; Disable System Verilog assertion messages
649 ; IgnoreSVAWarning = 1
653 ; Do not print any additional information from Severity System tasks.
654 ; Only the message provided by the user is printed along with severity
656 ; SVAPrintOnlyUserMessage = 1;
658 ; Default force kind. May be freeze, drive, deposit, or default
659 ; or in other terms, fixed, wired, or charged.
660 ; A value of "default" will use the signal kind to determine the
661 ; force kind, drive for resolved signals, freeze for unresolved signals
662 ; DefaultForceKind = freeze
664 ; If zero, open files when elaborated; otherwise, open files on
665 ; first read or write. Default is 0.
668 ; Control VHDL files opened for write.
669 ; 0 = Buffered, 1 = Unbuffered
672 ; Control the number of VHDL files open concurrently.
673 ; This number should always be less than the current ulimit
674 ; setting for max file descriptors.
676 ConcurrentFileLimit = 40
678 ; Control the number of hierarchical regions displayed as
679 ; part of a signal name shown in the Wave window.
680 ; A value of zero tells VSIM to display the full name.
682 ; WaveSignalNameWidth = 0
684 ; Turn off warnings when changing VHDL constants and generics
685 ; Default is 1 to generate warning messages
686 ; WarnConstantChange = 0
688 ; Turn off warnings from the std_logic_arith, std_logic_unsigned
689 ; and std_logic_signed packages.
690 ; StdArithNoWarnings = 1
692 ; Turn off warnings from the IEEE numeric_std and numeric_bit packages.
693 ; NumericStdNoWarnings = 1
695 ; Control the format of the (VHDL) FOR generate statement label
696 ; for each iteration. Do not quote it.
697 ; The format string here must contain the conversion codes %s and %d,
698 ; in that order, and no other conversion codes. The %s represents
699 ; the generate_label; the %d represents the generate parameter value
700 ; at a particular generate iteration (this is the position number if
701 ; the generate parameter is of an enumeration type). Embedded whitespace
702 ; is allowed (but discouraged); leading and trailing whitespace is ignored.
703 ; Application of the format must result in a unique scope name over all
704 ; such names in the design so that name lookup can function properly.
705 ; GenerateFormat = %s__%d
707 ; Specify whether checkpoint files should be compressed.
708 ; The default is 1 (compressed).
709 ; CheckpointCompressMode = 0
711 ; Specify whether to enable SystemVerilog DPI "out-of-the-blue" calls.
712 ; The term "out-of-the-blue" refers to SystemVerilog export function calls
713 ; made from C functions that don't have the proper context setup
714 ; (as is the case when running under "DPI-C" import functions).
715 ; When this is enabled, one can call a DPI export function
716 ; (but not task) from any C code.
717 ; the setting of this variable can be one of the following values:
718 ; 0 : dpioutoftheblue call is disabled (default)
719 ; 1 : dpioutoftheblue call is enabled, but export call debug support is not available.
720 ; 2 : dpioutoftheblue call is enabled, and limited export call debug support is available.
721 ; DpiOutOfTheBlue = 1
723 ; Specify whether continuous assignments are run before other normal priority
724 ; processes scheduled in the same iteration. This event ordering minimizes race
725 ; differences between optimized and non-optimized designs, and is the default
726 ; behavior beginning with the 6.5 release. For pre-6.5 event ordering, set
727 ; ImmediateContinuousAssign to 0.
728 ; The default is 1 (enabled).
729 ; ImmediateContinuousAssign = 0
731 ; List of dynamically loaded objects for Verilog PLI applications
732 ; Veriuser = veriuser.sl
734 ; Which default VPI object model should the tool conform to?
735 ; The 1364 modes are Verilog-only, for backwards compatibility with older
736 ; libraries, and SystemVerilog objects are not available in these modes.
738 ; In the absence of a user-specified default, the tool default is the
739 ; latest available LRM behavior.
740 ; Options for PliCompatDefault are:
741 ; VPI_COMPATIBILITY_VERSION_1364v1995
742 ; VPI_COMPATIBILITY_VERSION_1364v2001
743 ; VPI_COMPATIBILITY_VERSION_1364v2005
744 ; VPI_COMPATIBILITY_VERSION_1800v2005
745 ; VPI_COMPATIBILITY_VERSION_1800v2008
747 ; Synonyms for each string are also recognized:
748 ; VPI_COMPATIBILITY_VERSION_1364v1995 (1995, 95, 1364v1995, 1364V1995, VL1995)
749 ; VPI_COMPATIBILITY_VERSION_1364v2001 (2001, 01, 1364v2001, 1364V2001, VL2001)
750 ; VPI_COMPATIBILITY_VERSION_1364v2005 (1364v2005, 1364V2005, VL2005)
751 ; VPI_COMPATIBILITY_VERSION_1800v2005 (2005, 05, 1800v2005, 1800V2005, SV2005)
752 ; VPI_COMPATIBILITY_VERSION_1800v2008 (2008, 08, 1800v2008, 1800V2008, SV2008)
755 ; PliCompatDefault = VPI_COMPATIBILITY_VERSION_1800v2005
757 ; Specify default options for the restart command. Options can be one
758 ; or more of: -force -nobreakpoint -nolist -nolog -nowave -noassertions
759 ; DefaultRestartOptions = -force
761 ; Turn on (1) or off (0) WLF file compression.
762 ; The default is 1 (compress WLF file).
765 ; Specify whether to save all design hierarchy (1) in the WLF file
766 ; or only regions containing logged signals (0).
767 ; The default is 0 (save only regions with logged signals).
768 ; WLFSaveAllRegions = 1
770 ; WLF file time limit. Limit WLF file by time, as closely as possible,
771 ; to the specified amount of simulation time. When the limit is exceeded
772 ; the earliest times get truncated from the file.
773 ; If both time and size limits are specified the most restrictive is used.
774 ; UserTimeUnits are used if time units are not specified.
775 ; The default is 0 (no limit). Example: WLFTimeLimit = {100 ms}
778 ; WLF file size limit. Limit WLF file size, as closely as possible,
779 ; to the specified number of megabytes. If both time and size limits
780 ; are specified then the most restrictive is used.
781 ; The default is 0 (no limit).
782 ; WLFSizeLimit = 1000
784 ; Specify whether or not a WLF file should be deleted when the
785 ; simulation ends. A value of 1 will cause the WLF file to be deleted.
786 ; The default is 0 (do not delete WLF file when simulation ends).
787 ; WLFDeleteOnQuit = 1
789 ; Specify whether or not a WLF file should be indexed during
790 ; simulation. If set to 0, the WLF file will not be indexed.
791 ; The default is 1, indexed the WLF file.
794 ; Specify whether or not a WLF file should be optimized during
795 ; simulation. If set to 0, the WLF file will not be optimized.
796 ; The default is 1, optimize the WLF file.
799 ; Specify the name of the WLF file.
800 ; The default is vsim.wlf
801 ; WLFFilename = vsim.wlf
803 ; Specify the WLF reader cache size limit for each open WLF file.
804 ; The size is giving in megabytes. A value of 0 turns off the
806 ; WLFSimCacheSize allows a different cache size to be set for
807 ; simulation WLF file independent of post-simulation WLF file
808 ; viewing. If WLFSimCacheSize is not set it defaults to the
809 ; WLFCacheSize setting.
810 ; The default WLFCacheSize setting is enabled to 256M per open WLF file.
811 ; WLFCacheSize = 2000
812 ; WLFSimCacheSize = 500
814 ; Specify the WLF file event collapse mode.
815 ; 0 = Preserve all events and event order. (same as -wlfnocollapse)
816 ; 1 = Only record values of logged objects at the end of a simulator iteration.
817 ; (same as -wlfcollapsedelta)
818 ; 2 = Only record values of logged objects at the end of a simulator time step.
819 ; (same as -wlfcollapsetime)
821 ; WLFCollapseMode = 0
823 ; Specify whether WLF file logging can use threads on multi-processor machines
824 ; if 0, no threads will be used, if 1, threads will be used if the system has
825 ; more than one processor
828 ; Turn on/off undebuggable SystemC type warnings. Default is on.
829 ; ShowUndebuggableScTypeWarning = 0
831 ; Turn on/off unassociated SystemC name warnings. Default is off.
832 ; ShowUnassociatedScNameWarning = 1
834 ; Turn on/off SystemC IEEE 1666 deprecation warnings. Default is off.
835 ; ScShowIeeeDeprecationWarnings = 1
837 ; Turn on/off the check for multiple drivers on a SystemC sc_signal. Default is off.
838 ; ScEnableScSignalWriteCheck = 1
840 ; Set SystemC default time unit.
841 ; Set to fs, ps, ns, us, ms, or sec with optional
842 ; prefix of 1, 10, or 100. The default is 1 ns.
843 ; The ScTimeUnit value is honored if it is coarser than Resolution.
844 ; If ScTimeUnit is finer than Resolution, it is set to the value
845 ; of Resolution. For example, if Resolution is 100ps and ScTimeUnit is ns,
846 ; then the default time unit will be 1 ns. However if Resolution
847 ; is 10 ns and ScTimeUnit is ns, then the default time unit will be 10 ns.
850 ; Set SystemC sc_main stack size. The stack size is set as an integer
851 ; number followed by the unit which can be Kb(Kilo-byte), Mb(Mega-byte) or
852 ; Gb(Giga-byte). Default is 10 Mb. The stack size for sc_main depends
853 ; on the amount of data on the sc_main() stack and the memory required
854 ; to succesfully execute the longest function call chain of sc_main().
855 ScMainStackSize = 10 Mb
857 ; Turn on/off execution of remainder of sc_main upon quitting the current
858 ; simulation session. If the cumulative length of sc_main() in terms of
859 ; simulation time units is less than the length of the current simulation
860 ; run upon quit or restart, sc_main() will be in the middle of execution.
861 ; This switch gives the option to execute the remainder of sc_main upon
862 ; quitting simulation. The drawback of not running sc_main till the end
863 ; is memory leaks for objects created by sc_main. If on, the remainder of
864 ; sc_main will be executed ignoring all delays. This may cause the simulator
865 ; to crash if the code in sc_main is dependent on some simulation state.
867 ScMainFinishOnQuit = 1
869 ; Set the SCV relationship name that will be used to identify phase
870 ; relations. If the name given to a transactor relation matches this
871 ; name, the transactions involved will be treated as phase transactions
872 ScvPhaseRelationName = mti_phase
874 ; Customize the vsim kernel shutdown behavior at the end of the simulation.
875 ; Some common causes of the end of simulation are $finish (implicit or explicit),
876 ; sc_stop(), tf_dofinish(), and assertion failures.
877 ; This should be set to "ask", "exit", or "stop". The default is "ask".
878 ; "ask" -- In batch mode, the vsim kernel will abruptly exit.
879 ; In GUI mode, a dialog box will pop up and ask for user confirmation
880 ; whether or not to quit the simulation.
881 ; "stop" -- Cause the simulation to stay loaded in memory. This can make some
882 ; post-simulation tasks easier.
883 ; "exit" -- The simulation will abruptly exit without asking for any confirmation.
884 ; "final" -- Run SystemVerilog final blocks then behave as "stop".
885 ; Note: these ini variables can be overriden by the vsim command
886 ; line switch "-onfinish <ask|stop|exit>".
889 ; Print pending deferred assertion messages.
890 ; Deferred assertion messages may be scheduled after the $finish in the same
891 ; time step. Deferred assertions scheduled to print after the $finish are
892 ; printed before exiting with severity level NOTE since it's not known whether
893 ; the assertion is still valid due to being printed in the active region
894 ; instead of the reactive region where they are normally printed.
895 ; OnFinishPendingAssert = 1;
897 ; Print "simstats" result at the end of simulation before shutdown.
898 ; If this is enabled, the simstats result will be printed out before shutdown.
899 ; The default is off.
902 ; Assertion File - alternate file for storing VHDL/PSL/Verilog assertion messages
903 ; AssertFile = assert.log
905 ; Run simulator in assertion debug mode. Default is off.
908 ; Turn on/off PSL/SVA concurrent assertion pass enable.
909 ; For SVA, Default is on when the assertion has a pass action block, or
910 ; the vsim -assertdebug option is used and the vopt "+acc=a" flag is active.
911 ; For PSL, Default is on only when vsim switch "-assertdebug" is used
912 ; and the vopt "+acc=a" flag is active.
913 ; AssertionPassEnable = 0
915 ; Turn on/off PSL/SVA concurrent assertion fail enable. Default is on.
916 ; AssertionFailEnable = 0
918 ; Set PSL/SVA concurrent assertion pass limit. Default is -1.
919 ; Any positive integer, -1 for infinity.
920 ; AssertionPassLimit = 1
922 ; Set PSL/SVA concurrent assertion fail limit. Default is -1.
923 ; Any positive integer, -1 for infinity.
924 ; AssertionFailLimit = 1
926 ; Turn on/off PSL concurrent assertion pass log. Default is off.
927 ; The flag does not affect SVA
928 ; AssertionPassLog = 1
930 ; Turn on/off PSL concurrent assertion fail log. Default is on.
931 ; The flag does not affect SVA
932 ; AssertionFailLog = 0
934 ; Turn on/off SVA concurrent assertion local var printing in -assertdebug mode. Default is on.
935 ; AssertionFailLocalVarLog = 0
937 ; Set action type for PSL/SVA concurrent assertion fail action. Default is continue.
938 ; 0 = Continue 1 = Break 2 = Exit
939 ; AssertionFailAction = 1
941 ; Enable the active thread monitor in the waveform display when assertion debug is enabled.
942 ; AssertionActiveThreadMonitor = 1
944 ; Control how many waveform rows will be used for displaying the active threads. Default is 5.
945 ; AssertionActiveThreadMonitorLimit = 5
948 ; As per strict 1850-2005 PSL LRM, an always property can either pass
949 ; or fail. However, by default, Questa reports multiple passes and
950 ; multiple fails on top always/never property (always/never operator
951 ; is the top operator under Verification Directive). The reason
952 ; being that Questa reports passes and fails on per attempt of the
953 ; top always/never property. Use the following flag to instruct
954 ; Questa to strictly follow LRM. With this flag, all assert/never
955 ; directives will start an attempt once at start of simulation.
956 ; The attempt can either fail, match or match vacuously.
957 ; For e.g. if always is the top operator under assert, the always will
958 ; keep on checking the property at every clock. If the property under
959 ; always fails, the directive will be considered failed and no more
960 ; checking will be done for that directive. A top always property,
961 ; if it does not fail, will show a pass at end of simulation.
962 ; The default value is '0' (i.e. zero is off). For example:
965 ; Specify the number of clock ticks to represent infinite clock ticks.
966 ; This affects eventually!, until! and until_!. If at End of Simulation
967 ; (EOS) an active strong-property has not clocked this number of
968 ; clock ticks then neither pass or fail (vacuous match) is returned
969 ; else respective fail/pass is returned. The default value is '0' (zero)
970 ; which effectively does not check for clock tick condition. For example:
971 ; PslInfinityThreshold = 5000
973 ; Control how many thread start times will be preserved for ATV viewing for a given assertion
974 ; instance. Default is -1 (ALL).
975 ; ATVStartTimeKeepCount = -1
977 ; Turn on/off code coverage
980 ; Count all code coverage condition and expression truth table rows that match.
983 ; Turn off automatic inclusion of VHDL integers in toggle coverage. Default
984 ; is to include them.
985 ; ToggleNoIntegers = 1
987 ; Set the maximum number of values that are collected for toggle coverage of
988 ; VHDL integers. Default is 100;
989 ; ToggleMaxIntValues = 100
991 ; Set the maximum number of values that are collected for toggle coverage of
992 ; Verilog real. Default is 100;
993 ; ToggleMaxRealValues = 100
995 ; Turn on automatic inclusion of Verilog integers in toggle coverage, except
996 ; for enumeration types. Default is to include them.
997 ; ToggleVlogIntegers = 0
999 ; Turn on automatic inclusion of Verilog real type in toggle coverage, except
1000 ; for shortreal types. Default is to not include them.
1001 ; ToggleVlogReal = 1
1003 ; Turn on automatic inclusion of Verilog fixed-size unpacked arrays in toggle coverage.
1004 ; Default is to not include them.
1005 ; ToggleFixedSizeArray = 1
1007 ; Increase or decrease the maximum size of Verilog unpacked fixed-size arrays that
1008 ; are included for toggle coverage. This leads to a longer simulation time with bigger
1009 ; arrays covered with toggle coverage. Default is 1024.
1010 ; ToggleMaxFixedSizeArray = 1024
1012 ; Treat packed vectors and structures as reg-vectors in toggle coverage. Default is 0.
1013 ; TogglePackedAsVec = 0
1015 ; Treat Verilog enumerated types as reg-vectors in toggle coverage. Default is 0.
1016 ; ToggleVlogEnumBits = 0
1018 ; Limit the widths of registers automatically tracked for toggle coverage. Default is 128.
1019 ; For unlimited width, set to 0.
1020 ; ToggleWidthLimit = 128
1022 ; Limit the counts that are tracked for toggle coverage. When all edges for a bit have
1023 ; reached this count, further activity on the bit is ignored. Default is 1.
1024 ; For unlimited counts, set to 0.
1025 ; ToggleCountLimit = 1
1027 ; Turn on/off all PSL/SVA cover directive enables. Default is on.
1030 ; Turn on/off PSL/SVA cover log. Default is off "0".
1033 ; Set "at_least" value for all PSL/SVA cover directives. Default is 1.
1036 ; Set "limit" value for all PSL/SVA cover directives. Default is -1.
1037 ; Any positive integer, -1 for infinity.
1040 ; Specify the coverage database filename.
1041 ; Default is "" (i.e. database is NOT automatically saved on close).
1042 ; UCDBFilename = vsim.ucdb
1044 ; Specify the maximum limit for the number of Cross (bin) products reported
1045 ; in XML and UCDB report against a Cross. A warning is issued if the limit
1047 ; MaxReportRhsSVCrossProducts = 1000
1049 ; Specify the override for the "auto_bin_max" option for the Covergroups.
1050 ; If not specified then value from Covergroup "option" is used.
1051 ; SVCoverpointAutoBinMax = 64
1053 ; Specify the override for the value of "cross_num_print_missing"
1054 ; option for the Cross in Covergroups. If not specified then value
1055 ; specified in the "option.cross_num_print_missing" is used. This
1056 ; is a runtime option. NOTE: This overrides any "cross_num_print_missing"
1057 ; value specified by user in source file and any SVCrossNumPrintMissingDefault
1058 ; specified in modelsim.ini.
1059 ; SVCrossNumPrintMissing = 0
1061 ; Specify whether to use the value of "cross_num_print_missing"
1062 ; option in report and GUI for the Cross in Covergroups. If not specified then
1063 ; cross_num_print_missing is ignored for creating reports and displaying
1064 ; covergroups in GUI. Default is 0, which means ignore "cross_num_print_missing".
1065 ; UseSVCrossNumPrintMissing = 0
1067 ; Specify the override for the value of "strobe" option for the
1068 ; Covergroup Type. If not specified then value in "type_option.strobe"
1069 ; will be used. This is runtime option which forces "strobe" to
1070 ; user specified value and supersedes user specified values in the
1071 ; SystemVerilog Code. NOTE: This also overrides the compile time
1072 ; default value override specified using "SVCovergroupStrobeDefault"
1073 ; SVCovergroupStrobe = 0
1075 ; Override for explicit assignments in source code to "option.goal" of
1076 ; SystemVerilog covergroup, coverpoint, and cross. It also overrides the
1077 ; default value of "option.goal" (defined to be 100 in the SystemVerilog
1078 ; LRM) and the value of modelsim.ini variable "SVCovergroupGoalDefault".
1079 ; SVCovergroupGoal = 100
1081 ; Override for explicit assignments in source code to "type_option.goal" of
1082 ; SystemVerilog covergroup, coverpoint, and cross. It also overrides the
1083 ; default value of "type_option.goal" (defined to be 100 in the SystemVerilog
1084 ; LRM) and the value of modelsim.ini variable "SVCovergroupTypeGoalDefault".
1085 ; SVCovergroupTypeGoal = 100
1087 ; Enforce the 6.3 behavior of covergroup get_coverage() and get_inst_coverage()
1088 ; builtin functions, and report. This setting changes the default values of
1089 ; option.get_inst_coverage and type_option.merge_instances to ensure the 6.3
1090 ; behavior if explicit assignments are not made on option.get_inst_coverage and
1091 ; type_option.merge_instances by the user. There are two vsim command line
1092 ; options, -cvg63 and -nocvg63 to override this setting from vsim command line.
1093 ; The default value of this variable is 1
1094 ; SVCovergroup63Compatibility = 1
1096 ; Enable or disable generation of more detailed information about the sampling
1097 ; of covergroup, cross, and coverpoints. It provides the details of the number
1098 ; of times the covergroup instance and type were sampled, as well as details
1099 ; about why covergroup, cross and coverpoint were not covered. A non-zero value
1100 ; is to enable this feature. 0 is to disable this feature. Default is 0
1101 ; SVCovergroupSampleInfo = 0
1103 ; Specify the maximum number of Coverpoint bins in whole design for
1105 ; MaxSVCoverpointBinsDesign = 2147483648
1107 ; Specify maximum number of Coverpoint bins in any instance of a Covergroup
1108 ; MaxSVCoverpointBinsInst = 2147483648
1110 ; Specify the maximum number of Cross bins in whole design for
1112 ; MaxSVCrossBinsDesign = 2147483648
1114 ; Specify maximum number of Cross bins in any instance of a Covergroup
1115 ; MaxSVCrossBinsInst = 2147483648
1117 ; Set weight for all PSL/SVA cover directives. Default is 1.
1120 ; Check vsim plusargs. Default is 0 (off).
1121 ; 0 = Don't check plusargs
1122 ; 1 = Warning on unrecognized plusarg
1123 ; 2 = Error and exit on unrecognized plusarg
1126 ; Load the specified shared objects with the RTLD_GLOBAL flag.
1127 ; This gives global visibility to all symbols in the shared objects,
1128 ; meaning that subsequently loaded shared objects can bind to symbols
1129 ; in the global shared objects. The list of shared objects should
1130 ; be whitespace delimited. This option is not supported on the
1131 ; Windows or AIX platforms.
1132 ; GlobalSharedObjectList = example1.so example2.so example3.so
1134 ; Run the 0in tools from within the simulator.
1138 ; Set the options to be passed to the 0in runtime tool.
1139 ; Default value set to "".
1140 ; ZeroInOptions = ""
1142 ; Initial seed for the Random Number Generator (RNG) of the root thread (SystemVerilog).
1145 ; Maximum size of dynamic arrays that are resized during randomize().
1146 ; The default is 1000. A value of 0 indicates no limit.
1147 ; SolveArrayResizeMax = 1000
1149 ; Error message severity when randomize() failure is detected (SystemVerilog).
1150 ; The default is 0 (no error).
1151 ; 0 = No error 1 = Warning 2 = Error 3 = Failure 4 = Fatal
1152 ; SolveFailSeverity = 0
1154 ; Enable/disable debug information for randomize() failures (SystemVerilog).
1155 ; The default is 0 (disabled). Set to 1 to enable.
1156 ; SolveFailDebug = 0
1158 ; When SolveFailDebug is enabled, this value specifies the algorithm used to
1159 ; discover conflicts between constraints for randomize() failures.
1160 ; The default is "many".
1162 ; Valid schemes are:
1163 ; "many" = best for determining conflicts due to many related constraints
1164 ; "few" = best for determining conflicts due to few related constraints
1166 ; SolveFailDebugScheme = many
1168 ; When SolveFailDebug is enabled and SolveFailDebugScheme is "few", this value
1169 ; specifies the maximum number of constraint subsets that will be tested for
1171 ; The default is 0 (no limit).
1172 ; SolveFailDebugLimit = 0
1174 ; When SolveFailDebug is enabled and SolveFailDebugScheme is "few", this value
1175 ; specifies the maximum size of constraint subsets that will be tested for
1177 ; The default value is 0 (no limit).
1178 ; SolveFailDebugMaxSet = 0
1180 ; Maximum size of the solution graph that may be generated during randomize().
1181 ; This value can be used to force randomize() to abort if the memory
1182 ; requirements of the constraint scenario exceeds the specified limit. This
1183 ; value is specified in 1000s of nodes.
1184 ; The default is 10000. A value of 0 indicates no limit.
1185 ; SolveGraphMaxSize = 10000
1187 ; Maximum number of evaluations that may be performed on the solution graph
1188 ; generated during randomize(). This value can be used to force randomize() to
1189 ; abort if the complexity of the constraint scenario (in time) exceeds the
1190 ; specified limit. This value is specified in 10000s of evaluations.
1191 ; The default is 10000. A value of 0 indicates no limit.
1192 ; SolveGraphMaxEval = 10000
1194 ; Use SolveFlags to specify options that will guide the behavior of the
1195 ; constraint solver. These options may improve the performance of the
1196 ; constraint solver for some testcases, and decrease the performance of
1197 ; the constraint solver for others.
1198 ; The default value is "" (no options).
1201 ; i = disable bit interleaving for >, >=, <, <= constraints
1202 ; n = disable bit interleaving for all constraints
1203 ; r = reverse bit interleaving
1207 ; Specify random sequence compatiblity with a prior letter release. This
1208 ; option is used to get the same random sequences during simulation as
1209 ; as a prior letter release. Only prior letter releases (of the current
1210 ; number release) are allowed.
1211 ; Note: To achieve the same random sequences, solver optimizations and/or
1212 ; bug fixes introduced since the specified release may be disabled -
1213 ; yielding the performance / behavior of the prior release.
1214 ; Default value set to "" (random compatibility not required).
1217 ; Environment variable expansion of command line arguments has been depricated
1218 ; in favor shell level expansion. Universal environment variable expansion
1219 ; inside -f files is support and continued support for MGC Location Maps provide
1220 ; alternative methods for handling flexible pathnames.
1221 ; The following line may be uncommented and the value set to 1 to re-enable this
1222 ; deprecated behavior. The default value is 0.
1223 ; DeprecatedEnvironmentVariableExpansion = 0
1225 ; Turn on/off collapsing of bus ports in VCD dumpports output
1226 DumpportsCollapse = 1
1228 ; Location of Multi-Level Verification Component (MVC) installation.
1229 ; The default location is the product installation directory.
1230 ; MvcHome = $MODEL_TECH/...
1233 ; The simulator's interface to Logic Modeling's SmartModel SWIFT software
1234 libsm = $MODEL_TECH/libsm.sl
1235 ; The simulator's interface to Logic Modeling's SmartModel SWIFT software (Windows NT)
1236 ; libsm = $MODEL_TECH/libsm.dll
1237 ; Logic Modeling's SmartModel SWIFT software (HP 9000 Series 700)
1238 ; libswift = $LMC_HOME/lib/hp700.lib/libswift.sl
1239 ; Logic Modeling's SmartModel SWIFT software (IBM RISC System/6000)
1240 ; libswift = $LMC_HOME/lib/ibmrs.lib/swift.o
1241 ; Logic Modeling's SmartModel SWIFT software (Sun4 Solaris)
1242 ; libswift = $LMC_HOME/lib/sun4Solaris.lib/libswift.so
1243 ; Logic Modeling's SmartModel SWIFT software (Windows NT)
1244 ; libswift = $LMC_HOME/lib/pcnt.lib/libswift.dll
1245 ; Logic Modeling's SmartModel SWIFT software (non-Enterprise versions of Linux)
1246 ; libswift = $LMC_HOME/lib/x86_linux.lib/libswift.so
1247 ; Logic Modeling's SmartModel SWIFT software (Enterprise versions of Linux)
1248 ; libswift = $LMC_HOME/lib/linux.lib/libswift.so
1250 ; The simulator's interface to Logic Modeling's hardware modeler SFI software
1251 libhm = $MODEL_TECH/libhm.sl
1252 ; The simulator's interface to Logic Modeling's hardware modeler SFI software (Windows NT)
1253 ; libhm = $MODEL_TECH/libhm.dll
1254 ; Logic Modeling's hardware modeler SFI software (HP 9000 Series 700)
1255 ; libsfi = <sfi_dir>/lib/hp700/libsfi.sl
1256 ; Logic Modeling's hardware modeler SFI software (IBM RISC System/6000)
1257 ; libsfi = <sfi_dir>/lib/rs6000/libsfi.a
1258 ; Logic Modeling's hardware modeler SFI software (Sun4 Solaris)
1259 ; libsfi = <sfi_dir>/lib/sun4.solaris/libsfi.so
1260 ; Logic Modeling's hardware modeler SFI software (Windows NT)
1261 ; libsfi = <sfi_dir>/lib/pcnt/lm_sfi.dll
1262 ; Logic Modeling's hardware modeler SFI software (Linux)
1263 ; libsfi = <sfi_dir>/lib/linux/libsfi.so
1266 ; Change a message severity or suppress a message.
1267 ; The format is: <msg directive> = <msg number>[,<msg number>...]
1268 ; suppress can be used to achieve +nowarn<CODE> functionality
1269 ; The format is: suppress = <CODE>,<msg number>,[<CODE>,<msg number>,...]
1275 ; suppress = 3009,3016,3043
1276 ; suppress = 3009,CNNODP,3043,TFMPC
1277 ; The command verror <msg number> can be used to get the complete
1278 ; description of a message.
1280 ; Control transcripting of Verilog display system task messages and
1281 ; PLI/FLI print function call messages. The system tasks include
1282 ; $display[bho], $strobe[bho], Smonitor{bho], and $write[bho]. They
1283 ; also include the analogous file I/O tasks that write to STDOUT
1284 ; (i.e. $fwrite or $fdisplay). The PLI/FLI calls include io_printf,
1285 ; vpi_printf, mti_PrintMessage, and mti_PrintFormatted. The default
1286 ; is to have messages appear only in the transcript. The other
1287 ; settings are to send messages to the wlf file only (messages that
1288 ; are recorded in the wlf file can be viewed in the MsgViewer) or
1289 ; to both the transcript and the wlf file. The valid values are
1290 ; tran {transcript only (default)}
1291 ; wlf {wlf file only}
1292 ; both {transcript and wlf file}
1293 ; displaymsgmode = tran
1295 ; Control transcripting of elaboration/runtime messages not
1296 ; addressed by the displaymsgmode setting. The default is to
1297 ; have messages appear in the transcript and recorded in the wlf
1298 ; file (messages that are recorded in the wlf file can be viewed
1299 ; in the MsgViewer). The other settings are to send messages
1300 ; only to the transcript or only to the wlf file. The valid
1303 ; tran {transcript only}
1304 ; wlf {wlf file only}