wurms gitweb - coreboot.git/search

2011-08-04	Keith Hui	cpu/intel/slot_1: Init L2 cache on SECC(2) CPUs. Signed-off-by: Keith Hui <buurin@gmail.com>	commit \| commitdiff \| tree
2010-12-23	Keith Hui	Fix build with CONFIG_DEBUG_RAM_SETUP on Intel 440BX... Signed-off-by: Keith Hui <buurin@gmail.com>	commit \| commitdiff \| tree
2010-10-17	Keith Hui	Removes model_65x CPUIDs from model_6xx code. Signed-off-by: Keith Hui <buurin@gmail.com>	commit \| commitdiff \| tree
2010-10-16	Keith Hui	Move support for Deschutes Slot 1 CPUs (model_65x)... Signed-off-by: Keith Hui <buurin@gmail.com>	commit \| commitdiff \| tree
2010-10-13	Keith Hui	Move out Katmai Slot 1 CPUs (model_67x) from model_6xx... Signed-off-by: Keith Hui <buurin@gmail.com>	commit \| commitdiff \| tree
2010-10-12	Keith Hui	Add missing include of model_6bx for slot_1. Signed-off-by: Keith Hui <buurin@gmail.com>	commit \| commitdiff \| tree
2010-09-20	Keith Hui	A number of cleanups for 440BX raminit code. Signed-off-by: Keith Hui <buurin@gmail.com>	commit \| commitdiff \| tree
2010-03-17	Keith Hui	From Keith Hui: From Keith Hui: Signed-off-by: Keith Hui <buurin@gmail.com>	commit \| commitdiff \| tree
2010-03-13	Keith Hui	Add SDRAMPWR_4DIMM Kconfig option (not user-visible... Signed-off-by: Keith Hui <buurin@gmail.com>	commit \| commitdiff \| tree
2010-03-06	Keith Hui	440BX: Do not hardcode DIMM number + size anymore. Signed-off-by: Keith Hui <buurin@gmail.com>	commit \| commitdiff \| tree
2010-03-06	Keith Hui	Add support for the 0x06B1 CPU ID for Celeron (Tualatin). Signed-off-by: Keith Hui <buurin@gmail.com>	commit \| commitdiff \| tree
2010-03-05	Keith Hui	Add support for the ASUS P2B-LS mainboard. Signed-off-by: Keith Hui <buurin@gmail.com>	commit \| commitdiff \| tree
2010-03-05	Keith Hui	Add proper Slot 1 CPU support code/infrastructure. Signed-off-by: Keith Hui <buurin@gmail.com>	commit \| commitdiff \| tree

my coreboot WIP stuff (asus m5a99x-evo board)

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