Mart Raudsepp [Tue, 25 Nov 2008 16:41:21 +0000 (16:41 +0000)]
libpayload: Fix immediate rebuild after a clean
After running make clean, most of build/ directory gets deleted.
It is (re)created in the "prepare" make target, but that was libpayload.a
dependency after the $OBJS, while OBJS building already needs to dump its
created object files there.
Simply rearrange the make target dependencies to get at least "make clean;make" working.
Signed-off-by: Mart Raudsepp <mart.raudsepp@artecdesign.ee>
Acked-by: Jordan Crouse <jordan@cosmicpenguin.net>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3771
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Peter Stuge [Tue, 25 Nov 2008 02:03:16 +0000 (02:03 +0000)]
msrtool: Use libpci to let system and target probes find PCI devices.
And some more notes in TODO.
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3770
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Tero O Peippola [Mon, 24 Nov 2008 20:23:23 +0000 (20:23 +0000)]
Add support for 32Mbit SPI flash SST25VF032B. Tested on gigabyte m57sli.
File util/flashrom/flash.h already had correct ID for that part.
Signed-off-by: Tero O Peippola <xeropp@gmail.com>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3769
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Jordan Crouse [Mon, 24 Nov 2008 17:54:46 +0000 (17:54 +0000)]
[PATCH] libpayload: rename config.h to libpayload-config.h
Rename the generated config file to libpayload-config.h to differenciate
it from other config.h files. Move the default location of the file to
$(src)/include so that LIBPAYLOAD_PREFIX= users can access the file
without staging it.
Signed-off-by: Jordan Crouse <jordan@cosmicpenguin.net>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3768
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Peter Stuge [Sat, 22 Nov 2008 18:29:44 +0000 (18:29 +0000)]
msrtool: Very small fixes I made after sending out the rc1 tarball.
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3767
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Peter Stuge [Sat, 22 Nov 2008 17:13:36 +0000 (17:13 +0000)]
msrtool: Release Candidate 1
msrtool can decode MSRs and print the value of every field in human
readable form. It can also be used to save a set of MSRs to a file,
and at a later time compare the saved values with current values in
hardware.
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3766
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Elia Yehuda [Fri, 21 Nov 2008 17:14:40 +0000 (17:14 +0000)]
i810: Add support for multiple DIMMs, both single-sided and double-sided,
as well as most (all?) combinations thereof.
Drop some unused code, the unused row_offset variable, and obsolete comments.
Also, fix a typo (thanks to Stefan Reinauer for noticing).
This is tested on the MSI MS-6178 with a number of different DIMM
combinations and so far all of them worked fine.
Signed-off-by: Elia Yehuda <z4ziggy@gmail.com>
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3765
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Uwe Hermann [Thu, 20 Nov 2008 23:18:10 +0000 (23:18 +0000)]
Get rid of the unnecessary indirection by 'struct mem_controller' for the
Intel 810 chipset (and all boards using it). This isn't required for this
chipset as there's only one memory controller.
This also helps a lot with romcc register usage, you should see the dreaded
"too few registers" less often.
Build-tested with all three boards using the Intel 810 chipset.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Corey Osgood <corey.osgood@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3764
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Stefan Reinauer [Thu, 20 Nov 2008 20:07:38 +0000 (20:07 +0000)]
fix Config-abuild.lb for all targets that need a failover image and
don't have one (by fixing it for amd/serengeti_cheetah and copying the
same file to all other broken targets)
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3763
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Stefan Reinauer [Thu, 20 Nov 2008 19:26:16 +0000 (19:26 +0000)]
OK, people, watch this.
This is a school book example of why trivial indent patches just suck
big time.
This error was introduced by a trivial self-acked indent patch and was
never detected (because of a missing Config-abuild.lb)
So, indenting the code for no reason can make it a lot worse (read:
break it) instead of improving it.
I ask everyone to keep this in mind when going on indent-frenzy again.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3762
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Uwe Hermann [Wed, 19 Nov 2008 13:42:14 +0000 (13:42 +0000)]
Coding-style and whitespace fixes (also to make the code more similar
the Lippert Cool SpaceRunner LX which is already in svn).
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3761
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Jens Rottmann [Wed, 19 Nov 2008 12:19:09 +0000 (12:19 +0000)]
Add support for the LiPPERT Cool RoadRunner-LX embedded PC board:
- PC/104+ form factor
- AMD Geode-LX CPU/northbridge
- AMD CS5536 southbridge
- ITE IT8712F superio
http://www.lippert-at.com/index.php?id=408
Signed-off-by: Jens Rottmann <JRottmann@LiPPERTEmbedded.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3760
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Uwe Hermann [Tue, 18 Nov 2008 12:02:03 +0000 (12:02 +0000)]
i810: Add some more comments, and especially add a list of tested BUFF_SC
values for different DIMM configurations. This should be converted to a
table or code later on and actually be used for BUFF_SC.
Many thanks to Elia Yehuda <z4ziggy@gmail.com> for testing and collecting
the table entries.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3759
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Carl-Daniel Hailfinger [Tue, 18 Nov 2008 00:43:14 +0000 (00:43 +0000)]
Currently flashrom assumes every vendor BIOS shares our view about which
SPI opcodes should be placed in which location. Move to a less
optimistic implementation and actually use the generic SPI read
functions. They're useful for abstracting exactly this stuff and that
makes them the preferred choice.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3758
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Carl-Daniel Hailfinger [Tue, 18 Nov 2008 00:41:02 +0000 (00:41 +0000)]
Check for failed SPI command execution in flashrom. Although SPI itself
does not have a mechanism to signal command failure, the SPI host may be
unable to send a given command over the wire due to security or hardware
limitations. The current code ignores these mechanisms completely and
simply assumes almost every command succeeds. Complain if SPI command
execution fails.
Since locked down Intel chipsets (like the one we had problems with
earlier) only allow a small subset of commands, find the common subset
of commands between the chipset and the ROM in the chip erase case. That
is accomplished by the new spi_chip_erase_60_c7() which can be used for
chips supporting both 0x60 and 0xc7 chip erase commands.
Both parts of the patch address problems seen in the real world. The
increased verbosity for the error case will help us diagnose and address
problems better.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Otherwise: Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3757
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Carl-Daniel Hailfinger [Tue, 18 Nov 2008 00:36:26 +0000 (00:36 +0000)]
Implement read support for the following Atmel chips:
AT25DF021
AT25DF041A
AT25DF081
AT25DF161
AT25DF321A
AT25DF641
AT25F512B
AT25FS010
AT25FS040
AT26DF041
AT26DF081A
AT26DF161
AT26DF161A
AT26DF321
AT26F004
I double-checked the data sheets and am confident this will work.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3756
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Mart Raudsepp [Mon, 17 Nov 2008 15:31:56 +0000 (15:31 +0000)]
flashrom: SST39VF020 TEST_OK_ PROBE READ ERASE WRITE
Tested fully on a ThinCan DBE61A
Signed-off-by: Mart Raudsepp <mart.raudsepp@artecdesign.ee>
Acked-by: Mart Raudsepp <mart.raudsepp@artecdesign.ee>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3755
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Carl-Daniel Hailfinger [Sat, 15 Nov 2008 13:55:43 +0000 (13:55 +0000)]
The AT25 and AT26 series SPI chips from Atmel are plain EEPROMs.
The AT45 series SPI chips are DataFlash EEPROMs which means they have
odd (non-power-of-two) sector sizes, but some of the DataFlash chips can
be configured or ordered with power-of-two sector sizes.
Add probe support for the following Atmel SPI chips:
AT25DF021
AT25DF041A
AT25DF081
AT25DF161
AT25DF321A
AT25DF641
AT25F512B
AT25FS010
AT25FS040
AT26DF041
AT26DF081A
AT26DF161
AT26DF161A
AT26DF321
AT26F004
AT45CS1282
AT45DB011D
AT45DB021D
AT45DB041D
AT45DB081D
AT45DB161D
AT45DB321C
AT45DB321D
AT45DB642D
Add an explanation why the following chips can't be probed:
AT45BR3214B
AT45D011
AT45D021A
AT45D041A
AT45D081A
AT45D161
AT45DB011
AT45DB011B
AT45DB021A
AT45DB021B
AT45DB041A
AT45DB081A
AT45DB161
AT45DB161B
AT45DB321
AT45DB321B
AT45DB642
Add the ID, but no probing function for this chip:
AT25F512A
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Tested-by: Jesse Brandeburg <jesse.brandeburg@intel.com>
Tested-by: Andriy Gapon <avg@icyb.net.ua>
Acked-by: Myles Watson <mylesgw@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3754
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Uwe Hermann [Fri, 14 Nov 2008 19:25:37 +0000 (19:25 +0000)]
Rename LinuxBIOS strings and filenames to coreboot.
Also, use the more generic and buildrom-friendly '../payload.elf' as
the default payload location.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3753
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Stefan Reinauer [Fri, 14 Nov 2008 13:43:26 +0000 (13:43 +0000)]
drop dead code in sb600 hda
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Myles Watson <mylesgw@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3752
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Marc Jones [Wed, 12 Nov 2008 20:38:51 +0000 (20:38 +0000)]
Add another AM2 cpuid to the name string. Also, colapse the cases for duplicate strings to save some space.
Signed-off-by: Marc Jones <marcj303@yahoo.com>
Acked-by: Chris Lingard <chris@stockwith.co.uk>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3751
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Uwe Hermann [Wed, 12 Nov 2008 19:08:58 +0000 (19:08 +0000)]
Add detection support for ITE IT8228E, IT8711F, IT8722F, IT8761E,
IT8780F, and Fintek F71863FG.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3750
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Robert Millan [Tue, 11 Nov 2008 23:41:08 +0000 (23:41 +0000)]
Signed-off-by: Robert Millan <rmh@aybabtu.com>
Acked-by: Jordan Crouse <jordan@cosmicpenguin.net>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3749
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Robert Millan [Tue, 11 Nov 2008 23:36:12 +0000 (23:36 +0000)]
Signed-off-by: Robert Millan <rmh@aybabtu.com>
Acked-by: Jordan Crouse <jordan@cosmicpenguin.net>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3748
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Stefan Reinauer [Tue, 11 Nov 2008 21:57:20 +0000 (21:57 +0000)]
Thanks to Uwe Hermann for spotting this typo.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3747
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Uwe Hermann [Tue, 11 Nov 2008 21:10:07 +0000 (21:10 +0000)]
Add support for the Winbond W83627DHG Super I/O.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Corey Osgood <corey.osgood@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3746
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Robert Millan [Tue, 11 Nov 2008 20:20:54 +0000 (20:20 +0000)]
[PATCH] coreboot-v2: Add multiboot support
Signed-off-by: Robert Millan <rmh@aybabtu.com>
Acked-by: Jordan Crouse <jordan@cosmicpneguin.net>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3745
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Jordan Crouse [Tue, 11 Nov 2008 19:53:42 +0000 (19:53 +0000)]
[PATCH] coreinfo: Add multiboot parsing support
Rename the "coreboot" menu "firmware", and add a module to parse
the multiboot table. For now, just parse memory, but it can be
expanded as needed.
Signed-off-by: Jordan Crouse <jordan@cosmicpenguin.net>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3744
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Jordan Crouse [Tue, 11 Nov 2008 19:51:14 +0000 (19:51 +0000)]
[PATCH] Add sysinfo_have_multiboot function
Add a new infrastructure for returning system information to payloads.
First up - a pointer to the multiboot table.
Signed-off-by: Jordan Crouse <jordan@cosmicpenguin.net>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3743
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Uwe Hermann [Tue, 11 Nov 2008 14:26:03 +0000 (14:26 +0000)]
Always enable serial before SMBus (or as early as possible), as the SMBus
enable may do printk()s which result in a 2 minute delay on some boards.
Fix this on all boards which currently do smbus_enable() before enabling
the serial console.
Thanks to Elia Yehuda <z4ziggy@gmail.com> for tracking this bug down.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Peter Stuge <peter@stuge.se>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3742
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Stefan Reinauer [Mon, 10 Nov 2008 15:43:37 +0000 (15:43 +0000)]
Merge some parts of the i945 review (trivial):
* fix \r\n occurence in i945 code
* drop early TOLUD write
* fix 16bit BCTRL1 access
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3741
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Stefan Reinauer [Mon, 10 Nov 2008 13:52:14 +0000 (13:52 +0000)]
cosmetic update for getpir.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3740
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Uwe Hermann [Sun, 9 Nov 2008 10:57:26 +0000 (10:57 +0000)]
i945.h: Add some more comments, align data for better readability (trivial).
Also, add missing C1DRA2 #define (as per public datasheet).
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3738
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Carl-Daniel Hailfinger [Sat, 8 Nov 2008 01:51:32 +0000 (01:51 +0000)]
The POST_CODE macro had the outb() argument order backwards.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3737
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Peter Stuge [Sat, 8 Nov 2008 01:39:12 +0000 (01:39 +0000)]
flashrom: SST39SF040 TEST_OK_ PROBE READ ERASE WRITE
Per report from Mario Rogen. Thanks!
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3736
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Ulf Jordan [Sat, 8 Nov 2008 00:58:16 +0000 (00:58 +0000)]
Update bayou to use ACS_ macros for line drawing characters.
Signed-off-by: Ulf Jordan <jordan@chalmers.se>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3735
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Uwe Hermann [Thu, 6 Nov 2008 22:38:31 +0000 (22:38 +0000)]
Re-add "based on" lines.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Jens Rottmann <JRottmann@LiPPERTEmbedded.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3734
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Uwe Hermann [Thu, 6 Nov 2008 22:24:05 +0000 (22:24 +0000)]
Drop #defines for registers that are not existant on the ICH7.
Also, fix BIOS_CNTL, which is 0xdc on ICH7.
Build-tested with kontron/986lcd-m.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3733
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Uwe Hermann [Thu, 6 Nov 2008 22:23:05 +0000 (22:23 +0000)]
The enable_hpet() code in intel/i82801gx will not work with the
ICH7 southbridge (but it might work with ICH4/ICH5 or so).
The ICH7 needs a different init code. Drop the non-working code for now.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3732
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Carl-Daniel Hailfinger [Wed, 5 Nov 2008 22:54:36 +0000 (22:54 +0000)]
The ST M25P16 chip has been confirmed to work fine for probe, read,
erase and write by Stéphan Guilloux.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3731
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Carl-Daniel Hailfinger [Tue, 4 Nov 2008 12:11:12 +0000 (12:11 +0000)]
Add support for 8 new chips to flashrom and fix up 2 existing chips
as well.
Replace age-old TODO comments with real explanations.
Fixed chips:
Fujitsu MBM29F400TC (ID definition)
Macronix MX29F002T (chip name)
New chips:
Fujitsu MBM29F004BC
Fujitsu MBM29F004TC
Fujitsu MBM29F400BC
Macronix MX25L512
Macronix MX25L1005
Macronix MX25L2005
Macronix MX25L6405
Macronix MX29F002B
Straight from the data sheets, compile tested only.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3730
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Jens Rottmann [Mon, 3 Nov 2008 23:16:00 +0000 (23:16 +0000)]
Fix compile errors if CONFIG_FS_PAYLOAD=1:
Compile error in filo.c if AUTOBOOT_DELAY=0. Replace
#ifndef AUTOBOOT_DELAY
with
#if !AUTOBOOT_DELAY
which should work for both the #undef and the =0 case.
In ext2fs.c, fat.c
#if ARCH == 'i386'
results in a compile warning: "multi-character character constant" and
the condition ARCH == 'i386' is mis-evaluated as FALSE, eventually
choking the assembler on a PPC instruction. Change it to
#ifdef __i386
Signed-off-by: Jens Rottmann <JRottmann@LiPPERTEmbedded.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3729
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Jens Rottmann [Mon, 3 Nov 2008 22:58:56 +0000 (22:58 +0000)]
Add the missing I/O resources for IT8712F GPIOs. (E.g. some LiPPERT
boards need them to switch the com ports from RS232 to RS485.) The PnP
resources should prevent other devices from being mapped at the same
spot, even if no OS driver actively uses them.
The IT8712F manual makes it look like PNP_IO1 had a size/granularity of
1 byte, but that must be a mistake. The Simple-I/O resource has a size
of 5 bytes (1 for each GPIO set 1-5) and trying different addresses
reveals a granularity of 8.
Signed-off-by: Jens Rottmann <JRottmann@LiPPERTEmbedded.de>
Acked-by: Marc Jones <marc.jones@amd.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3728
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Marc Jones [Mon, 3 Nov 2008 22:46:27 +0000 (22:46 +0000)]
Set asus/a8v-3_se to use printk in CAR. (trivial)
Signed-off-by: Marc Jones <marc.jones@amd.com>
Acked-by: Marc Jones <marc.jones@amd.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3727
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Marc Jones [Mon, 3 Nov 2008 21:39:03 +0000 (21:39 +0000)]
Update K8 FID/VID setup. Add support for 100MHz FIDs (revG).
Signed-off-by: Marc Jones <marc.jones@amd.com>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3726
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Jordan Crouse [Mon, 3 Nov 2008 16:55:22 +0000 (16:55 +0000)]
Move the default payload to be more buildrom friendly.
Signed-off-by: Jordan Crouse <jordan.crouse@amd.com>
Acked-by: Jordan Crouse <jordan.crouse@amd.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3725
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Ronald G. Minnich [Mon, 3 Nov 2008 04:08:35 +0000 (04:08 +0000)]
modify pirq tables for epia-cn.
Not tested, builds, derived from getpir. Definitely better than what was there.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Bari Ari <bari@onelabs.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3724
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Carl-Daniel Hailfinger [Mon, 3 Nov 2008 00:20:22 +0000 (00:20 +0000)]
Dump ICH8/ICH9/ICH10 SPI registers in flashrom.
This helps a lot if we have to track down configuration weirdnesses.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3723
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Carl-Daniel Hailfinger [Mon, 3 Nov 2008 00:02:11 +0000 (00:02 +0000)]
Add additional SPI sector erase and chip erase command functions to
flashrom. Not all chips support all commands, so allow the implementer
to select the matching function.
Fix a layering violation in ICH SPI code to be less bad. Still not
perfect, but the new code is shorter, more generic and
architecturally
more sound.
TODO (in a separate patch):
- move the generic sector erase code to spi.c
- decide which erase command to use based on info about the chip
- create a generic spi_erase_all_sectors function which calls the
generic sector erase function
Thanks to Stefan for reviewing and commenting.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3722
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Stefan Reinauer [Sun, 2 Nov 2008 19:51:50 +0000 (19:51 +0000)]
Drop nr/opcode_index parameter from run_opcode and search the opmenu for the opcode instead.
This is slightly slower (ha, ha), but works on boards with a locked opmenu. Tested on ICH7 and works.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3721
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Uwe Hermann [Sun, 2 Nov 2008 17:48:20 +0000 (17:48 +0000)]
Get the lzma/ directory from v3 via svn:externals, for use with Bayou.
Also, fix a few Makefiles regarding lzma stuff and 'make clean' behaviour.
Add bayou.xml.example which users can use as a starting point.
Bayou does compile fine now (if you build ../libpayload) before.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3720
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Uwe Hermann [Sun, 2 Nov 2008 17:01:06 +0000 (17:01 +0000)]
Import a slightly modified Bayou version into svn. This is based
on the last snapshot posted by Jordan Crouse. This commit is long
overdue.
Changes by me include:
- Rename 'utils' to 'util' for consistency with our other projects.
- Move the main code out of src/* into the top-level directory.
- Add missing license headers to the following files:
Makefile, pbuilder/liblar/Makefile, util/pbuilder/Makefile.
- Dropped the util/pbuilder/lzma completely. I'm working on reusing
the lzma/ dir from v3 via svn:externals. Alas, this also means
that Bayou won't yet compile out of the box.
- Coding-style and white-space fixes (indent) for all files.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3719
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Uwe Hermann [Sun, 2 Nov 2008 14:33:51 +0000 (14:33 +0000)]
Trim down the list of southbridges supported by the i82801xx driver
to only a set of reasonably similar ones, namely (for now) ICH0* - ICH6*,
and C-ICH.
All later ICH* southbridges (ICH7-ICH10) are _very_ different and were surely
not working with this driver anyway (and there's no chance to support
them reasonably with this driver without ending up in #ifdef hell).
ICH7 now has an extra driver in svn, whether ICH8-ICH10 are similar
enough to be supported by that ICH7 driver remains to be seen.
This patch was informally acked by Stefan Reinauer
<stepan@coresystems.de> on IRC.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3718
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Carl-Daniel Hailfinger [Sun, 2 Nov 2008 14:25:11 +0000 (14:25 +0000)]
Add support for the ST M50FW002 chip to flashrom. Identification only,
erase/write are not implemented.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
tested and
Acked-by: Elia Yehuda <z4ziggy@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3717
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Stefan Reinauer [Sun, 2 Nov 2008 11:11:40 +0000 (11:11 +0000)]
inteltool 82945G/GZ/P/PL Support (trivial)
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3716
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Uwe Hermann [Fri, 31 Oct 2008 18:41:09 +0000 (18:41 +0000)]
Revert i945/ICH7 PCI IDs to be hard-coded numbers instead of #defines.
Build-tested on kontron_986lcd_m.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3715
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Uwe Hermann [Fri, 31 Oct 2008 05:40:04 +0000 (05:40 +0000)]
Move the nvramtool manpage to section 8 (as it's only really usable as root),
as we've done with the superiotool and flashrom manpages, too (trivial).
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3714
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Marc Jones [Thu, 30 Oct 2008 22:13:51 +0000 (22:13 +0000)]
Leave room for ROM growth and for the payload. (trivial)
Signed-off-by: Marc Jones <marc.jones@amd.com>
Acked-by: Marc Jones <marc.jones@amd.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3713
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Marc Jones [Thu, 30 Oct 2008 21:31:54 +0000 (21:31 +0000)]
Increased the size of the failover and normal ROM_IMAGE_SIZE so abuild will
pass with toolsets that compile larger images. (trivial)
Signed-off-by: Marc Jones <marc.jones@amd.com>
Acked-by: Marc Jones <marc.jones@amd.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3712
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Arne Georg Gleditsch [Thu, 30 Oct 2008 20:17:11 +0000 (20:17 +0000)]
Here's a patch towards r3690 upping the ROM size for the S2912 Fam10 target to 1M.
Both regular and abuild images have been boot tested successfully.
Signed-off-by: Arne Georg Gleditsch <arne.gleditsch@numascale.com>
Acked-by: Marc Jones <marc.jones@amd.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3711
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Jens Rottmann [Thu, 30 Oct 2008 19:34:44 +0000 (19:34 +0000)]
Add support for the LiPPERT Cool SpaceRunner-LX embedded PC board:
- PC/104+ form factor
- AMD Geode-LX CPU/northbridge
- AMD CS5536 southbridge
- ITE IT8712F Super I/O
Signed-off-by: Jens Rottmann <JRottmann@LiPPERTEmbedded.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3710
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Andriy Gapon [Thu, 30 Oct 2008 15:41:39 +0000 (15:41 +0000)]
Allow nvramtool to build and work on FreeBSD. Tested on FreeBSD 7.
Signed-off-by: Andriy Gapon <avg@icyb.net.ua>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3709
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Uwe Hermann [Thu, 30 Oct 2008 03:10:17 +0000 (03:10 +0000)]
Mark two more chips as fully tested (trivial).
- SST SST39SF010A
- Winbond W29C011
Tested by me on actual hardware, all operations.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3708
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Stefan Reinauer [Wed, 29 Oct 2008 22:13:20 +0000 (22:13 +0000)]
Flashrom support for some Numonyx parts (M25PE)
using block erase d8 as discussed with Peter Stuge
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3707
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Ed Swierk [Wed, 29 Oct 2008 14:54:36 +0000 (14:54 +0000)]
Enable SPI boot flash support on EP80579, which has the ICH7 register set
(trivial).
Signed-off-by: Ed Swierk <eswierk@aristanetworks.com>
Acked-by: Ed Swierk <eswierk@aristanetworks.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3706
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Uwe Hermann [Wed, 29 Oct 2008 13:51:31 +0000 (13:51 +0000)]
i945/ICH7: Use #defines from pci_ids.h (trivial).
Build-tested with the kontron/986lcd-m target.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3705
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Stefan Reinauer [Wed, 29 Oct 2008 04:52:57 +0000 (04:52 +0000)]
Support for the Kontron 986LCD-M mainboard series.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3704
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Stefan Reinauer [Wed, 29 Oct 2008 04:51:07 +0000 (04:51 +0000)]
Support for the Intel 945 northbridge.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3703
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Stefan Reinauer [Wed, 29 Oct 2008 04:48:44 +0000 (04:48 +0000)]
Support for Intel Core Duo and Core 2 Duo (tm) CPUs.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3702
2b7e53f0-3cfb-0310-b3e9-
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Stefan Reinauer [Wed, 29 Oct 2008 04:46:52 +0000 (04:46 +0000)]
Support for the Intel ICH7 southbridge.
This includes an early SMI handler.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3701
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Stefan Reinauer [Wed, 29 Oct 2008 04:45:28 +0000 (04:45 +0000)]
Implement support for the Winbond W83627THG.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3700
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Stefan Reinauer [Wed, 29 Oct 2008 03:15:42 +0000 (03:15 +0000)]
Changes required to the device allocator:
- leave a hole for mmapped PCIe config space if CONFIG_PCIE_CONFIGSPACE_HOLE
is set.
- Mask moving bits to 32bit when resources are not supposed above 4G. Linux
does not like this, even though the resource is disabled.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Myles Watson <mylesgw@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3699
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Andriy Gapon [Tue, 28 Oct 2008 22:13:38 +0000 (22:13 +0000)]
Allow superiotool to compile and work on FreeBSD. Tested on FreeBSD 7.
Signed-off-by: Andriy Gapon <avg@icyb.net.ua>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3698
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Uwe Hermann [Tue, 28 Oct 2008 12:00:59 +0000 (12:00 +0000)]
Mark Winbond W39V040FA" (512 KB) as fully supported, tested by
Martin Stecklum <stecky@gmx.net> (both write and erase).
The tests were done on an MSI MS-7065 board, so that's supported now
too (wiki page will be updated).
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3697
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Uwe Hermann [Tue, 28 Oct 2008 11:50:05 +0000 (11:50 +0000)]
Add support for the Intel 82371MX (MPIIX) southbridge (trivial).
Untested, but should work just as well as the other *PIIX* southbridges
according to the datasheets.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3696
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Mats Erik Andersson [Mon, 27 Oct 2008 13:44:07 +0000 (13:44 +0000)]
Add initial support for the MSI MS-6147 mainboard.
Signed-off-by: Mats Erik Andersson <mats.andersson@gisladisker.org>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3695
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Uwe Hermann [Sun, 26 Oct 2008 18:40:42 +0000 (18:40 +0000)]
Add support for the Intel
82371FB PIIX and 82371SB (PIIX3) southbridges.
Tested on PIIX3 hardware.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Corey Osgood <corey.osgood@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3694
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Uwe Hermann [Sat, 25 Oct 2008 18:03:50 +0000 (18:03 +0000)]
Add support for the VIA VT82C586A/B chipset, improve documentation.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3693
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Urja Rannikko [Thu, 23 Oct 2008 23:33:18 +0000 (23:33 +0000)]
Add support for the ITE IT8661F/IT8770F, IT8673F, and IT8671F/IT8687R.
They all use a different init sequence than the more modern ITE Super I/Os.
For now we only use 0x370 as config port, but 0x3f0 or 0x3bd would also be
valid. Contrary to other Super I/Os, the config port for these is _not_
hardcoded via hardware, instead it can be programmed by software, i.e.
you get to choose whether you want to use 0x370, 0x3f0, or 0x3bd.
Tested on IT8671F by Uwe Hermann and on IT8770F by Urja Rannikko.
Signed-off-by: Urja Rannikko <urjaman@gmail.com>
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Urja Rannikko <urjaman@gmail.com>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3692
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Patrick Georgi [Thu, 23 Oct 2008 12:22:24 +0000 (12:22 +0000)]
make escape code handling for serial terminal more robust
Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Marc Jones <marc.jones@amd.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3691
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Jens Rottmann [Wed, 22 Oct 2008 22:30:17 +0000 (22:30 +0000)]
Made await_ide(), which polls for an ide status change, check the status
reg much more often. In my case this reduced the time spent in coreboot
by 1.5 sec!
The timeout values of course aren't changed, only the granularity. Also,
I didn't see any udelay() implementation that looked like it couldn't
cope with 10 us delays. (Most are written as for (...) inb(0x80) loops.)
Signed-off-by: Jens Rottmann <JRottmann@LiPPERTEmbedded.de>
Acked-by: Marc Jones <marc.jones@amd.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3690
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Jens Rottmann [Wed, 22 Oct 2008 22:26:09 +0000 (22:26 +0000)]
Changed RAM speed calculation to fix RAM modules getting rejected only
due to integer rounding errors. Previously, the formula was:
speed = 2 * (10000/spd_value)
For spd_value=60 this means speed = 2 * 166 = 332, which is less than
333 and coreboot died saying RAM was incompatible. The new formula is:
speed = 20000 / spd_value
For spd_value=60, speed=333, which is fine.
Signed-off-by: Jens Rottmann <JRottmann@LiPPERTEmbedded.de>
Acked-by: Marc Jones <marc.jones@amd.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3689
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Jens Rottmann [Wed, 22 Oct 2008 22:24:47 +0000 (22:24 +0000)]
Speed up copying coreboot to ram by using "movsl" instead of "movsb".
Also use different console messages for copying and uncompressing, like
it's already done in similar code in other places.
Signed-off-by: Jens Rottmann <JRottmann@LiPPERTEmbedded.de>
Acked-by: Marc Jones <marc.jones@amd.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3688
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Jens Rottmann [Wed, 22 Oct 2008 22:20:48 +0000 (22:20 +0000)]
Fixes a off-by-one error when routing the IRQs. This led to IRQ15 not
getting assigned.
Signed-off-by: Jens Rottmann <JRottmann@LiPPERTEmbedded.de>
Acked-by: Marc Jones <marc.jones@amd.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3687
2b7e53f0-3cfb-0310-b3e9-
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Uwe Hermann [Wed, 22 Oct 2008 15:49:20 +0000 (15:49 +0000)]
Fix ordering problem in the libpayload Makefile. The include of
'include util/kconfig/Makefile' must come before certain pattern rules
for compilation of kconfig files, otherwise the build would break
in most situations.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Jordan Crouse <jordan.crouse@amd.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3686
2b7e53f0-3cfb-0310-b3e9-
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Stefan Reinauer [Wed, 22 Oct 2008 11:23:32 +0000 (11:23 +0000)]
add multiboot support to defconfig (trivial)
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3685
2b7e53f0-3cfb-0310-b3e9-
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Stefan Reinauer [Wed, 22 Oct 2008 11:06:20 +0000 (11:06 +0000)]
ouch. something went wrong with applying that old patch
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3684
2b7e53f0-3cfb-0310-b3e9-
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Stefan Reinauer [Wed, 22 Oct 2008 10:49:34 +0000 (10:49 +0000)]
This has been sitting here since a looong time.
* allow versions of "install" that don't know -D
* install libpayload .config and config.h to the target.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Jordan Crouse <jordan.crouse@amd.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3683
2b7e53f0-3cfb-0310-b3e9-
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Uwe Hermann [Tue, 21 Oct 2008 22:09:02 +0000 (22:09 +0000)]
Reduce serial output, otherwise flashing will fail very often (trivial).
This has been tested on hardware by me.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3682
2b7e53f0-3cfb-0310-b3e9-
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Jordan Crouse [Tue, 21 Oct 2008 21:49:48 +0000 (21:49 +0000)]
[PATCH] fix video console init
Move console_add_output-driver() inside the for() loop
Signed-off-by: Jordan Crouse <jordan.crouse@amd.com>
Acked-by: Jordan Crouse <jordan.crouse@amd.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3681
2b7e53f0-3cfb-0310-b3e9-
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Uwe Hermann [Tue, 21 Oct 2008 16:27:38 +0000 (16:27 +0000)]
I/O ports are 16bit, so change 'unsigned long port_base' to 'u16 port_base'.
Also, use more readable #defines instead of hardcoded config ports for
PM/PM2 related functions, and simplify them a bit.
Build-tested with the AMD dbm690t target.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Marc Jones <marc.jones@amd.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3680
2b7e53f0-3cfb-0310-b3e9-
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Patrick Georgi [Tue, 21 Oct 2008 15:08:18 +0000 (15:08 +0000)]
This patch removes most of the #ifdefs in libc/console.c, and
replaces it with two queues (input, output) where drivers (serial,
keyboard, video, usb) can attach.
The only things left with #ifdefs are initialization (at some point
the drivers must get a chance to register)
Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Jordan Crouse <jordan.crouse@amd.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3679
2b7e53f0-3cfb-0310-b3e9-
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Uwe Hermann [Tue, 21 Oct 2008 15:07:53 +0000 (15:07 +0000)]
Add missing license header.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Jordan Crouse <jordan.crouse@amd.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3678
2b7e53f0-3cfb-0310-b3e9-
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Jordan Crouse [Mon, 20 Oct 2008 17:08:08 +0000 (17:08 +0000)]
[PATCH] libpayload: Fix overflow in _delay function
On faster machines, delta might be more then 32 bits
Signed-off-by: Jordan Crouse <jordan.crouse@amd.com>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3677
2b7e53f0-3cfb-0310-b3e9-
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Jordan Crouse [Mon, 20 Oct 2008 17:07:47 +0000 (17:07 +0000)]
[PATCH] libpayload: Add a strtoul() function
Signed-off-by: Jordan Crouse <jordan.crouse@amd.com>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3676
2b7e53f0-3cfb-0310-b3e9-
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Jordan Crouse [Mon, 20 Oct 2008 17:07:26 +0000 (17:07 +0000)]
[PATCH] libpayload: Bail if the keyboard controller isn't there
If the system in question does not have a superIO, then a read of
0x64 will return 0xFF and we will loop forever.
Signed-off-by: Jordan Crouse <jordan.crouse@amd.com>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3675
2b7e53f0-3cfb-0310-b3e9-
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Jordan Crouse [Mon, 20 Oct 2008 16:52:06 +0000 (16:52 +0000)]
[PATCH] libpayload: Fix the PCI search function
Remove a possiblity for evil recusion and fix the function and slot
definition in the PCI search loop
Signed-off-by: Jordan Crouse <jordan.crouse@amd.com>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3674
2b7e53f0-3cfb-0310-b3e9-
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Jordan Crouse [Mon, 20 Oct 2008 16:51:43 +0000 (16:51 +0000)]
[PATCH] libpayload: Add multiboot support
Make libpayload applications multiboot compatible. Add the
multiboot OS table and grok the loader table, especially the
memory map and the command line. This makes libpayload
applications loadable by GRUB.
Signed-off-by: Jordan Crouse <jordan.crouse@amd.com>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3673
2b7e53f0-3cfb-0310-b3e9-
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Jordan Crouse [Mon, 20 Oct 2008 16:51:20 +0000 (16:51 +0000)]
[PATCH] libpayload: Add pci_set_bus_master() function
Allow the payload to enable a PCI device as a bus master.
Signed-off-by: Jordan Crouse <jordan.crouse@amd.com>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3672
2b7e53f0-3cfb-0310-b3e9-
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Jordan Crouse [Mon, 20 Oct 2008 16:50:47 +0000 (16:50 +0000)]
[PATCH] libpayload: Use gcc to compile assembly files
Using gcc to compile assembly files lets us use preprocessor
directives.
Signed-off-by: Jordan Crouse <jordan.crouse@amd.com>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3671
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1