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(parent: debb11f) | patch
Support for Intel Core Duo and Core 2 Duo (tm) CPUs.
authorStefan Reinauer <stepan@coresystems.de>
Wed, 29 Oct 2008 04:48:44 +0000 (04:48 +0000)
committerStefan Reinauer <stepan@openbios.org>
Wed, 29 Oct 2008 04:48:44 +0000 (04:48 +0000)
commit00a889c8aabd7b731622d5ff0e765f69e158de2b
treefb10bfbf6a71bcc8ad583feb6b0c706abb86b6fatree | snapshot
parentdebb11fc1fe5f5560015ab9905f1ccc2e08c73e0commit | diff
Support for Intel Core Duo and Core 2 Duo (tm) CPUs.

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3702 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
17 files changed:
src/cpu/intel/model_6ex/Config.lb [new file with mode: 0644] blob
src/cpu/intel/model_6ex/cache_as_ram.inc [new file with mode: 0644] blob
src/cpu/intel/model_6ex/cache_as_ram_disable.c [new file with mode: 0644] blob
src/cpu/intel/model_6ex/cache_as_ram_post.c [new file with mode: 0644] blob
src/cpu/intel/model_6ex/microcode_m206e839.h [new file with mode: 0644] blob
src/cpu/intel/model_6ex/model_6ex_init.c [new file with mode: 0644] blob
src/cpu/intel/model_6fx/Config.lb [new file with mode: 0644] blob
src/cpu/intel/model_6fx/cache_as_ram.inc [new file with mode: 0644] blob
src/cpu/intel/model_6fx/cache_as_ram_disable.c [new file with mode: 0644] blob
src/cpu/intel/model_6fx/cache_as_ram_post.c [new file with mode: 0644] blob
src/cpu/intel/model_6fx/model_6fx_init.c [new file with mode: 0644] blob
src/cpu/intel/socket_mFCPGA478/Config.lb diff | blob | history
src/cpu/intel/socket_mPGA478/Config.lb [new file with mode: 0644] blob
src/cpu/intel/socket_mPGA478/chip.h [new file with mode: 0644] blob
src/cpu/intel/socket_mPGA478/socket_mPGA478.c [new file with mode: 0644] blob
src/cpu/x86/car/copy_and_run.c diff | blob | history
src/cpu/x86/lapic/lapic_cpu_init.c diff | blob | history
my coreboot WIP stuff (asus m5a99x-evo board)