Use the coreboot pci config read/write functions instead of direct cf8/cfc

access. The fam10 pci functions will use mmio and do not have SMP pci access
issues.

Signed-off-by: Marc Jones <marcj303@gmail.com>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4633 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

diff --git a/src/northbridge/amd/amdmct/mct/mct_d.c b/src/northbridge/amd/amdmct/mct/mct_d.c
index 1a10cafd605c848b7e5b09f96ec71d982070cdfb..22e990255dfd3c0fbd8be0e28872296844c33b4d 100644 (file)
--- a/src/northbridge/amd/amdmct/mct/mct_d.c
+++ b/src/northbridge/amd/amdmct/mct/mct_d.c
@@ -2472,22 +2472,13 @@ static u8 mct_setMode(struct MCTStatStruc *pMCTstat,
 
 u32 Get_NB32(u32 dev, u32 reg)
 {
-       u32 addr;
-
-       addr = (dev>>4) | (reg & 0xFF) | ((reg & 0xf00)<<16);
-       outl((1<<31) | (addr & ~3), 0xcf8);
-
-       return inl(0xcfc);
+       return pci_read_config32(dev, reg);
 }
 
 
 void Set_NB32(u32 dev, u32 reg, u32 val)
 {
-       u32 addr;
-
-       addr = (dev>>4) | (reg & 0xFF) | ((reg & 0xf00)<<16);
-       outl((1<<31) | (addr & ~3), 0xcf8);
-       outl(val, 0xcfc);
+       pci_write_config32(dev, reg, val);
 }